Hi Subhankar,
You can increase the width of the crossbar. Though, I believe after 64B
increasing the width does not make a difference. You could also increase
the clock rate of the crossbar (e.g., 2X the cache clock) to simulate a
multi-ported crossbar. Finally, you could add a new crossbar model,
Hi all,
I am trying to build a hierarchy of caches and tester CPUs using memtest
(configs/examples/memtest.py) as my reference. I am able to connect regular
XBars and caches normally, but I want an *N*-ported connection between a
cache and a XBar (i.e. *N* simultaneous requests should be able to g
Hi all,
I am trying to build a hierarchy of caches and tester CPUs using memtest
(configs/examples/memtest.py) as my reference. I am able to connect regular
XBars and caches normally, but I want an *N*-ported connection between a
cache and a XBar (i.e. *N* simultaneous requests should be able to g
