Re: [gem5-users] Suspecting bubbles in the DRAM controller command bus

m5-users on behalf of Prathap > Kolakkampadath > Reply-To: gem5 users mailing list > Date: Friday, 10 July 2015 18:41 > > To: gem5 users mailing list > Subject: Re: [gem5-users] Suspecting bubbles in the DRAM controller > command bus > >Hello Andreas, > >

Re: [gem5-users] Suspecting bubbles in the DRAM controller command bus

ply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Friday, 10 July 2015 18:41 To: gem5 users mailing list mailto:gem5-users@gem5.org>> Subject: Re: [gem5-users] Suspecting bubbles in the DRAM controller command bus Hello Andreas, Ok. So below code make sure that the

Re: [gem5-users] Suspecting bubbles in the DRAM controller command bus

gt; From: gem5-users on behalf of Prathap > Kolakkampadath > Reply-To: gem5 users mailing list > Date: Friday, 10 July 2015 17:11 > To: gem5 users mailing list > Subject: Re: [gem5-users] Suspecting bubbles in the DRAM controller > command bus > > Hello Andreas, &g

Re: [gem5-users] Suspecting bubbles in the DRAM controller command bus

gem5 users mailing list mailto:gem5-users@gem5.org>> Subject: Re: [gem5-users] Suspecting bubbles in the DRAM controller command bus Hello Andreas, I am still not very clear. >> If we have not already precharged, we need to take the hit and do it now. What If we don't have any row h

Re: [gem5-users] Suspecting bubbles in the DRAM controller command bus

0 > to bank 1 then we can prepare R10 without the need to precharge bank 0. > > Andreas > > From: gem5-users on behalf of Prathap > Kolakkampadath > Reply-To: gem5 users mailing list > Date: Thursday, 9 July 2015 18:26 > To: gem5 users mailing list > Subject: [

Re: [gem5-users] Suspecting bubbles in the DRAM controller command bus

ply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Thursday, 9 July 2015 18:26 To: gem5 users mailing list mailto:gem5-users@gem5.org>> Subject: [gem5-users] Suspecting bubbles in the DRAM controller command bus Hello Users, I suspect the DRAM controller code is adding

[gem5-users] Suspecting bubbles in the DRAM controller command bus

Hello Users, I suspect the DRAM controller code is adding unwanted bubbles in the command bus. Consider there are 10 row hit read requests- R0 and R9- in the queue, all targeting Bank0 and a Row miss request- R10 -to Bank1 of same rank and numbered in the arrival order. According to FR-FCFS in o