I am not using EFI. I am using coreboot with Intel FSP. Intel confirmed
that XHCI controller is initialized by FSP and any standard XHCI driver
should work on top of that.
Problem Details:
Requirement:
My requirement is to load GRUB2 as payload from coreboot and Load Linux
using GRUB2 (from USB p
02.03.2017 06:00, Gailu Singh пишет:
> Thanks for the update. I will try your patches on Apollo lake and report
> back the results. Intel strategy seems to be XHCI only option on newer
> boards so sooner or later xhci support is required in Grub. Thanks for your
> effort to take initiative.
>
On
Thanks for the update. I will try your patches on Apollo lake and report
back the results. Intel strategy seems to be XHCI only option on newer
boards so sooner or later xhci support is required in Grub. Thanks for your
effort to take initiative.
On Wed, Mar 1, 2017 at 4:07 PM, Bjørn Forsman
wrot
Hi Experts,
Is there any development on XHCI support on GRUB2? New Intel boards (e.g.
Apollo Lake) has only XHCI controller so none my USB device (keyboarrd,
mass storage) works on GRUB2 on this board.
If there is any work going on, I can help with testing/development but
don't know where to star
Hi Experts,
I am using GRUB2 on intel apollo lake board. This board does not have IO
mapped uart instead it has 8250 memory mapped UART.
GRUB2 does not recognize memory mapped uart and gives error ("serial port
COM0 not found). There is a 8250 memory mapped driver available in
coreboot. Is it pos
Build problem was due to not running ./configure. I only did make clean and
make. Build issue is now resolved after running configure. Only cosmetic
change in your patch.
=
static void
read_bars(grub_pci_device_t dev, struct grub_serial_board *board)
{
for (unsigned bar = 0; bar < N
On 03/01/2017 11:32 AM, Gailu Singh wrote:
> I checked coreboot where in the memory it is mapped and it seems to be
> on PCIE. Relevant code from coreboot. So I am hopeful that patch will work.
> -
> uintptr_t uart_platform_base(int idx)
> {
> u8 *pcie;
> u32 tmp;
> idx = idx & 3
On 1 March 2017 at 07:57, Andrei Borzenkov wrote:
> Yes, Bjørn Forsman intended to work on implementation.
So now is apparently a good time to tell you about the status of that
implementation :-)
The good:
I ported the xHCI driver from Coreboot / libpayload to GRUB. In basic
tests, it works. (
I checked coreboot where in the memory it is mapped and it seems to be on
PCIE. Relevant code from coreboot. So I am hopeful that patch will work.
-
uintptr_t uart_platform_base(int idx)
{
u8 *pcie;
u32 tmp;
idx = idx & 3;
pcie = (u8 *)PCIE_MMIO(0, PCH_DEV_SLOT_UART, idx, 0);
tmp
On Tue, Feb 28, 2017 at 10:51:51PM +, Vladimir 'phcoder' Serbinenko wrote:
> I will review your patches later. There might be some overlap with my "arm"
> branch. Can you have a look whether it diverges a lot?
Not a lot.
2, 4, 6 and 7 apply cleanly if I merge the others manually.
1 fails on e
Sorry for typo. I meant 8250 instead of 8050 in last email
On Wed, Mar 1, 2017 at 3:21 PM, Gailu Singh wrote:
> My board is Intel Oxbohill CRB (Apollo lake). On my board UART are not
> connected to PCI.
>
> I am using grub2 payload loaded by coreboot. UART works fine in coreboot
> by using memor
My board is Intel Oxbohill CRB (Apollo lake). On my board UART are not
connected to PCI.
I am using grub2 payload loaded by coreboot. UART works fine in coreboot by
using memory mapped 8050 driver (
https://github.com/coreboot/coreboot/blob/master/src/drivers/uart/uart8250mem.c),
however when grub
Hi,
On 03/01/2017 08:00 AM, Andrei Borzenkov wrote:
> please test patches from Matthias Lange
>
> https://lists.gnu.org/archive/html/grub-devel/2017-02/msg00104.html
>
>
> On Wed, Mar 1, 2017 at 9:15 AM, Gailu Singh wrote:
>> Hi Experts,
>>
>> I am using GRUB2 on intel apollo lake board. This
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