Re: Python package for MVS data set I/O

2022-10-28 Thread Wayne Bickerdike
Good job David, Thanks. On Fri, Oct 28, 2022 at 6:26 PM David Crayford wrote: > I've written a Python package [1] to process record oriented MVS data > sets. It supports QSAM, BSAM, VSAM (KSDS, ESDS, RRDS), hiperspaces and > the file system. I would recommend not using it for the file system as

Re: XLC C/C++, __R1 and Register 0

2022-10-28 Thread David Crayford
FINDENVB is reliable. It's designed for languages that don't have access to R0. I use it in all my REXX command processors written in C++. On 29/10/22 08:55, Charles Mills wrote: I would guess that FINDENVB is no better, no different really, than passing 0 and letting IRXEXCOM take a guess. Am

Re: XLC C/C++, __R1 and Register 0

2022-10-28 Thread Charles Mills
I would guess that FINDENVB is no better, no different really, than passing 0 and letting IRXEXCOM take a guess. Am I wrong? The way I read the docs is that method will fail if the caller is using a Rexx "reentrant environment." Am I wrong? Charles -Original Message- From: IBM Mainfra

Re: Crypto Express question

2022-10-28 Thread Lennie Dymoke-Bradshaw
What a shame. However, If you configure your Crypto Express as an accelerator rather than a full processor then it will still work with SSL and TLS. The calls used by SSL and TLS use clear key calls and so do not need the master keys. Master keys are not used by accelerator mode. Running as an acc

Re: XLC C/C++, __R1 and Register 0

2022-10-28 Thread David Crayford
There is a field in the LE Enclave Control Block called CEEEDB_R13_PARENT which is a pointer to a DSA containing the registers of the enclave parent. If you can be bothered. I would just use IRXINIT("FINDENVB ") to get the environment block as opposed to fiddling about with control blocks. On

Re: XLC C/C++, __R1 and Register 0

2022-10-28 Thread Charles Mills
Thanks. What is the relevance to my question? (How do I obtain the contents of R0 on entry to a C program from Rexx?) Charles -Original Message- From: IBM Mainframe Discussion List [mailto:IBM-MAIN@LISTSERV.UA.EDU] On Behalf Of Seymour J Metz Sent: Friday, October 28, 2022 3:02 PM To:

Re: XLC C/C++, __R1 and Register 0

2022-10-28 Thread Seymour J Metz
There are three cases 1. address foo bar baz Pass command bar baz to environment foo address foo bar baz 2. call bar baz Invoke bar with parameter baz; return value optional 3. bar(baz) in an expression Invoke bar with parameter baz; return value required The last tw

64 BIT ULUT list information missing

2022-10-28 Thread Joseph Reichman
The 64 bit ULUT address on my system is 1F0 I was looking for information on it returned by IARV64 REQUEST=LIST I would assume its in common or shared and coded this macro to get more information IARV64 REQUEST=LIST, X

Crypto Express question

2022-10-28 Thread Frank Swarbrick
We are pushing our "host security module" processing off our mainframe back to our card issuer processor, and I have a couple of questions. If we use ICSF just for TLS and the like, does this still require the DES and RSA keys to be loaded? We already don't have AES or ECC master keys, so I am

Re: Location of forms code in z/OS manuals

2022-10-28 Thread Paul Gilmartin
On Fri, 28 Oct 2022 04:32:42 +, Seymour J Metz wrote: >That's true for current z/OS but not true across the board. > >At least the PDF from IBM has title; the ones from bitsavers doesn't even have >that :-( > Ob Samuel Johnson's politically incorrect dog: It's unrealistic to expect a process

Python package for MVS data set I/O

2022-10-28 Thread David Crayford
I've written a Python package [1] to process record oriented MVS data sets. It supports QSAM, BSAM, VSAM (KSDS, ESDS, RRDS), hiperspaces and the file system. I would recommend not using it for the file system as the Python standard library does a better job and supports file tagging. The packag