On 10/12/2023 9:24 AM, Seymour J Metz wrote:
SYNCH creates a PRB, not an IRB.
You are correct. My bad. Not sure what I was thinking.
CIRB and SCHEDIRB are the only ways to create an IRB.
I have only ever used SCHEDIRB. CIRB was before my time...
--
Phoenix Software International
Edward E. J
On Thu, 12 Oct 2023 at 12:03, Ed Jaffe wrote:
> On 9/17/2023 1:39 PM, Seymour J Metz wrote:
> > You use an IRB for any of
> >
> > Obsolete access methods
> > STIMER with exit
> > STAI
> > STAX
>
> An IRB is the vehicle used whenever system code wishes to call an exit
> in appl
Jaffe
Sent: Thursday, October 12, 2023 12:03 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Why it's important to take Seymour's advice
On 9/17/2023 1:39 PM, Seymour J Metz wrote:
> You use an IRB for any of
>
> Obsolete access methods
> STIMER with exit
> ST
SYNCH creates a PRB, not an IRB.
From: IBM Mainframe Discussion List on behalf of Ed
Jaffe
Sent: Thursday, October 12, 2023 12:03 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Why it's important to take Seymour's advice
On 9/17/2023 1:39 PM,
On 9/17/2023 1:39 PM, Seymour J Metz wrote:
You use an IRB for any of
Obsolete access methods
STIMER with exit
STAI
STAX
An IRB is the vehicle used whenever system code wishes to call an exit
in application code -- usually via the SYNCH macro.
For example, all VTAM exits
For address spaces known to always be non-swappable, how about ALESERV
ADD and just load the returned ALET into an AR, then SACF 512?
That is a supported method. The "knowing" can be the sticking point.
Peter Relson
z/OS Core Technology Design
-
For address spaces known to always be non-swappable, how about ALESERV
ADD and just load the returned ALET into an AR, then SACF 512? My
code that does that has never failed (yet). What are the risks, other
than the obvious one of the target A/S going away while the code is
running?
Come to
On Sun, Sep 17, 2023 at 08:39:37PM +, Seymour J Metz wrote:
> You use an IRB for any of
>
> Obsolete access methods
> STIMER with exit
> STAI
> STAX
VTAM RPL and EXLST exit routines
IBM TCP/IP ?
ICUV/VNCF ? {obsolete?}
UCLA/IPC NOTIFY=INTADR {the slowest IPC notify method}
Adam J wrote
Given the proper authorization, you can:
- Issue an AXSET, specifying a value of 1
- Issue an SSAR instruction identifying the target address space as the
secondary address space
- Use MVCP / MVCS instructions to copy data between your primary address space
and the secondary addres
behalf of
>> Joseph Reichman
>> Sent: Tuesday, September 19, 2023 9:20 PM
>> To: IBM-MAIN@LISTSERV.UA.EDU
>> Subject: Re: Why it's important to take Seymour's advice
>>
>> I have a O R5,=X’8000’
>> To set bit 31
--
er 19, 2023 9:20 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Why it's important to take Seymour's advice
>
> I have a O R5,=X’8000’
> To set bit 31
>
> Not home now but I’ll look up and check the SCHEDIRB again
>
> Get Outlook for iOS<https://ak
That's bit 0.
From: IBM Mainframe Discussion List on behalf of
Joseph Reichman
Sent: Tuesday, September 19, 2023 9:20 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Why it's important to take Seymour's advice
I have a O R5,=X’8000’
To
o: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Why it's important to take Seymour's advice
>
As it was recommended to issue SCHEDIRB From an IRB I issue it from a STIMER
routine
The devil is in the details. As coded that does not apply.
>SVAREA=YES,
>
nt: Tuesday, September 19, 2023 8:29 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Why it's important to take Seymour's advice
Here it is
As it was recommended to issue SCHEDIRB From an IRB I issue it from a STIMER
routine
I'll start with the STIMERM I use STIMERM as opposed to
MAIN@LISTSERV.UA.EDU <mailto:IBM-MAIN@LISTSERV.UA.EDU>
Subject: Re: Why it's important to take Seymour's advice
I am looking at the TCB/rb chain in the SVC dump the IRB epa has a 1 as the
last digit I was in amode 31 when I issued schedirb The irb address last digit
was a 0 before i
Show the code.
From: IBM Mainframe Discussion List on behalf of
Joseph Reichman
Sent: Tuesday, September 19, 2023 7:58 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Why it's important to take Seymour's advice
I am looking at the TCB/rb chain
Discussion List on behalf of
> Joseph Reichman
> Sent: Tuesday, September 19, 2023 12:53 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: Re: Why it's important to take Seymour's advice
>
> Hi just did a a SUMM TCBERROR and this is what I got
>
> Now I was doing s
18E76D0
EP... IKJEFT01 ENTPT 852C5000
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of
Lennie Dymoke-Bradshaw
Sent: Tuesday, September 19, 2023 11:25 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Why it's important to take Seymour's advice
My experience i
True, and I've coded cross memory accesses and POST to wake up a TCB (of
mine) in another address space. That's all pretty easy. I can't fully
remember what Omegamon needed the SRB for but I'm pretty sure I read
about it in their doc.
On 9/19/2023 6:40 AM, Adam Johanson wrote:
Tom Brennan w
, September 19, 2023 11:25 AM
:>To: IBM-MAIN@LISTSERV.UA.EDU
:>Subject: Re: Why it's important to take Seymour's advice
:>
:>My experience is that in times past this was definitely true. But nowadays it
no longer is.
:>I am unsure what changed but I think there was a chan
ssion List mailto:IBM-MAIN@LISTSERV.UA.EDU> > On Behalf Of dailom...@aol.com
<mailto:dailom...@aol.com>
Sent: 19 September 2023 16:16
To: IBM-MAIN@LISTSERV.UA.EDU <mailto:IBM-MAIN@LISTSERV.UA.EDU>
Subject: Re: Why it's important to take Seymour's advice
I thi
...@aol.com
Sent: 19 September 2023 16:16
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: Why it's important to take Seymour's advice
I think the other address space needs to be nonswappable.
On Tuesday, September 19, 2023 at 09:40:36 AM EDT, Adam Johanson
<031ca9d720
I think the other address space needs to be nonswappable.
On Tuesday, September 19, 2023 at 09:40:36 AM EDT, Adam Johanson
<031ca9d720a7-dmarc-requ...@listserv.ua.edu> wrote:
Tom Brennan wrote:
> I've never written code that runs as an SRB, but over the years I've
> read about the
Tom Brennan wrote:
> I've never written code that runs as an SRB, but over the years I've
> read about them and seen them in action, such as Omegamon poking code
> into other address spaces to grab data or do things like zap memory.
For what it's worth, you don't need to go through all the rigama
x27;s important to take Seymour's advice
Thanks! So the main points are (as I already thought) that an SRB isn't
related to any TCB's and is dispatched before any TCB's, or even if
there are no TCB's ready for work.
And (what I think you're saying) is that an IRB is relat
STIMER(M) w/o (without) WAIT.
WAIT just places the RB in a wait so no IRB is required.
On Sun, 17 Sep 2023 12:08:38 -0700 Tom Brennan
wrote:
:>Thanks! So the main points are (as I already thought) that an SRB isn't
:>related to any TCB's and is dispatched before any TCB's, or even if
:>ther
Thanks! So the main points are (as I already thought) that an SRB isn't
related to any TCB's and is dispatched before any TCB's, or even if
there are no TCB's ready for work.
And (what I think you're saying) is that an IRB is related to a
particular TCB, which makes it quite different from an
Well, technically an SRB code can get control before the address space is
supposed to get control. The SRB runs without a TCB and is limited in which
system services can be issued.
The IRB is an RB like a PRB and is associated with a TCB. It is usually placed
by something not running under that T
I've never written code that runs as an SRB, but over the years I've
read about them and seen them in action, such as Omegamon poking code
into other address spaces to grab data or do things like zap memory. So
my simple understanding is an SRB is code that once scheduled, gets run
first when
On Fri, Sep 15, 2023 at 06:16:59PM -0400, Joseph Reichman wrote:
> I did schedule the irb in the ikjeft01 TCB against Seymour's advice
> for a return code of zero from schedirb
There are likely many ways to do something like what you are trying
to do and the IRB idea likely wasn't close to the bes
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