On Fri, 18 Mar 2011 16:12:45 -0700, Ben Widawsky b...@bwidawsk.net wrote:
In the failure cases during rc6 initialization, both the power context
and render context may get !refcount without holding struct_mutex.
However, on rc6 disabling, the lock is held by the caller.
Added a simple
On Fri, 18 Mar 2011 16:12:46 -0700, Ben Widawsky b...@bwidawsk.net wrote:
There is a race condition between setting PWRCTXA and executing
MI_SET_CONTEXT. PWRCTXA must not be set until a valid context has been
written (or else the GPU could possible go into rc6, and return to an
invalid
On Sat, 19 Mar 2011 11:19:38 +0100, Alexey Fisher bug-tr...@fisher-privat.net
wrote:
Hi,
i have regression between 2.6.38 and 2.6.38-05646-g08351fc on 945GME.
It can suspend but on resume graphic will freeze.
I can access the netbook per ssh. Here is the interisting part of log:
[
Hi,
Is there an updated version of the native backlight patchset that
Matthew posted in November?
http://thread.gmane.org/gmane.linux.acpi.devel/48145
On my Sony Vaio Y, Intel Ironlake/Arrandale integrated graphics, I'm
having problems setting my backlight level through
In the failure cases during rc6 initialization, both the power context
and render context may get !refcount without holding struct_mutex.
However, on rc6 disabling, the lock is held by the caller.
Rearranged the locking so that it's safe in both cases.
Signed-off-by: Ben Widawsky
On Fri, Mar 18, 2011 at 08:02:10AM +, Chris Wilson wrote:
... even though it was disabled. A mistake in the handling of fence reuse
caused us to skip the vital delay of waiting for the object to finish
rendering before changing the register.
Reviewed-by: Daniel Vetter
On Sat, 19 Mar 2011 23:17:56 +0100, Daniel Vetter dan...@ffwll.ch wrote:
On Fri, Mar 18, 2011 at 08:02:10AM +, Chris Wilson wrote:
... even though it was disabled. A mistake in the handling of fence reuse
caused us to skip the vital delay of waiting for the object to finish
rendering
On Fri, Mar 18, 2011 at 10:35:16PM +, Chris Wilson wrote:
This fixes a bookkeeping error causing an OOPS whilst waiting for an
object to finish using a fence. Now we can simply wait for the fence to
be written independent of the objects currently inhabiting it (past,
present and future).
On Sat, 19 Mar 2011 23:35:55 +0100, Daniel Vetter dan...@ffwll.ch wrote:
@@ -2647,9 +2638,13 @@ i915_gem_object_get_fence(struct drm_i915_gem_object
*obj,
pipelined = NULL;
old-fence_reg = I915_FENCE_REG_NONE;
- old-last_fenced_ring =
On Fri, Mar 18, 2011 at 10:35:17PM +, Chris Wilson wrote:
Whenever we finish reading an object through a fence, for safety we
clear any GPU read domain and so invalidate any TLBs associated with
the fenced region upon its next use.
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
--
On Fri, Mar 18, 2011 at 10:35:19PM +, Chris Wilson wrote:
With the last bug preventing fence pipelining fixed (or at least the
last known bug), re-enable pipelining to avoid stalling on fence
acquisition between batches.
\o/ ... the cleaned-up get_fence code is definitely much less scary,
On Sat, 19 Mar 2011 23:55:11 +0100, Daniel Vetter dan...@ffwll.ch wrote:
A few nitpicks below.
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index 5201f82..2dbf8f7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@
On Sat, Mar 19, 2011 at 07:55:01AM +, Chris Wilson wrote:
Let's make this a more generic function because it does look useful.
static inline int intel_ring_wait_idle(struct intel_ring_buffer *ring)
{
return intel_wait_ring_buffer(ring, ring-space - 8);
}
Sounds good. I'm
In the failure cases during rc6 initialization, both the power context
and render context may get !refcount without holding struct_mutex.
However, on rc6 disabling, the lock is held by the caller.
Rearranged the locking so that it's safe in both cases.
Signed-off-by: Ben Widawsky
Added a new function which waits for the ringbuffer space to be equal to
(total - 8). This is the empty condition of the ringbuffer, and
equivalent to head==tail.
Also modified two users of this functionality elsewhere in the code.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
There is a race condition between setting PWRCTXA and executing
MI_SET_CONTEXT. PWRCTXA must not be set until a valid context has been
written (or else the GPU could possible go into rc6, and return to an
invalid context).
Reported-and-Tested-by: Gu Rui chaos.pro...@gmail.com
Bugzilla:
The previous patches should fix enough of the known issues to try
re-enabling rc6 for general consumption
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_drv.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
17 matches
Mail list logo
