Hi all,
We finished new round Kernel testing. We covered both mobile and desktop
machines on platforms IVB, SNB, ILK, GM965 and PNV.
The Kernel the latest on -testing branch Daniel's tree:
commit 0028cac2e9e91961384ac15aae4196eee0faf4f6
Merge: 121d527 b250da7
Author: Daniel Vetter
On Wed, Mar 28, 2012 at 03:59:17PM -0700, Ben Widawsky wrote:
On Thu, 29 Mar 2012 00:43:00 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Sun, Mar 18, 2012 at 01:39:42PM -0700, Ben Widawsky wrote:
Very basic code for context setup/destruction in the driver.
There are 4 entry points
On Wed, Mar 28, 2012 at 05:20:11PM -0700, Ben Widawsky wrote:
On Thu, 29 Mar 2012 00:36:21 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Sun, Mar 18, 2012 at 01:39:44PM -0700, Ben Widawsky wrote:
Handy mostly for assertions.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
I
On Wed, Mar 28, 2012 at 05:23:08PM -0700, Ben Widawsky wrote:
Daniel, how do you want to handle this?
It's somewhere on my list of things to do. I'd like to play around with
this on my ivb first just to see what's going on, but otherwise nothing to
complain about here.
Yours, Daniel
On Wed,
On Wed, Mar 28, 2012 at 01:39:20PM -0700, Jesse Barnes wrote:
Updated patchset addressing comments. I dropped some:
- display reg offset (we're going to fix this up differently)
- cache handling (not needed)
along with the ones Daniel has already queued.
Hopefully these ones look ok to
On Wed, Mar 28, 2012 at 03:29:04PM +0200, Takashi Iwai wrote:
Hi,
we've encountered a broken LVDS output on some IVY/SNB machines when
the mode is changed (from/to native resolution). When this happens,
the whole laptop panel gets half white and half black. This doesn't
recover until the
On Thu, 29 Mar 2012 14:16:38 +0200, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Mar 28, 2012 at 03:29:04PM +0200, Takashi Iwai wrote:
Hi,
we've encountered a broken LVDS output on some IVY/SNB machines when
the mode is changed (from/to native resolution). When this happens,
the whole
On Thu, Mar 29, 2012 at 01:44:28PM +0100, Chris Wilson wrote:
On Thu, 29 Mar 2012 14:16:38 +0200, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Mar 28, 2012 at 03:29:04PM +0200, Takashi Iwai wrote:
Hi,
we've encountered a broken LVDS output on some IVY/SNB machines when
the mode is
Thanks Kenneth. There isn't a specific extension that I am looking at now. I
was hoping for reference list to check what the extension details on what has
been accelerated, punted to fallback or like the GetGraphicResetStatus() case
implemented as a noop on Ivy Bridge. Right now my best
At Thu, 29 Mar 2012 14:51:32 +0200,
Daniel Vetter wrote:
On Thu, Mar 29, 2012 at 01:44:28PM +0100, Chris Wilson wrote:
On Thu, 29 Mar 2012 14:16:38 +0200, Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Mar 28, 2012 at 03:29:04PM +0200, Takashi Iwai wrote:
Hi,
we've encountered a
#part sign=pgpmime
On Thu, 29 Mar 2012 13:44:28 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
In conjunction with bits Power Sequence Progress field and Power Cycle
Delay Active, this bit set to a one indicates that the panel is
currently powered up or is currently in the power down
This is an updated set of patches for Haswell enablement. I tried to address
all the comments, and re-diffed the patches to simplify their inclusion into
Daniel's tree.
I have also split the PCI IDs definitions and their hook-up into the binding
tables as well. But I think we should wait on
The macro is becoming too complex and with VLV upon us it can lead to
confusion. So transforming this into a feature check instead.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c |6 ++
drivers/gpu/drm/i915/i915_drv.h |3 ++-
2 files
This adds product definitions for desktop, mobile and server boards.
v2: split into a separate patch, add .has_pch_split feature.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/char/agp/intel-agp.h| 11 +++
drivers/char/agp/intel-gtt.c| 14 ++
This patch enabled i915 driver to handle Haswell devices. It should go in
last, when things are working stable enough.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/char/agp/intel-agp.c|4
drivers/gpu/drm/i915/i915_drv.c |7 +++
2 files changed, 11
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c |4
drivers/gpu/drm/i915/i915_drv.h |2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
This defines the registers used by different power wells.
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 13 +
1 file changed, 13 insertions(+)
diff --git
There are 5 DDI ports on Haswell. Port A is always enabled, and is the one
connected to eDP, and Port E is the one that can be connected to the PCH
using FDI protocol. Ports B, C, D and E can be used for digital outputs.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Eugeni
There is one set of such registers for each pipe (A/B/C/EDP).
v2: update to use DDI PORTS enum
v1 Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 26 ++
1 file changed, 26
This is one set of those registers for each pipe.
v2: use port enum to access individual registers
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
There is one set of those registers for each port.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 627e52d..666e319
On Thu, 29 Mar 2012 10:47:56 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Wed, Mar 28, 2012 at 05:20:11PM -0700, Ben Widawsky wrote:
On Thu, 29 Mar 2012 00:36:21 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Sun, Mar 18, 2012 at 01:39:44PM -0700, Ben Widawsky wrote:
Handy mostly
v2: prevent possible conflicts with VLV.
v1 Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
With Lynx Point, we need to use SBI to communicate with the display clock
control. This commit adds helper functions to access the registers via
SBI.
v2: de-inline the function and address changes in bits names
v1 Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
Signed-off-by: Eugeni Dodonov
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_hdmi.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index cae3e5f..de54c01 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++
On Haswell, we need to properly train the DDI buffers prior to enabling
HDMI.
Note that we do enable the DDI Function for the corresponding pipe, in a
similar fashion as we do with FDI. This ensures that the pipe DDI
transport is left in a almost-ready state, and we only need to enable the
pipe
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 09c18f8..0324250 100644
---
Those are driven by DDIs on Haswell architecture, so we need to keep track
of which DDI is being used on each output.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_hdmi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8e5f5be..5e226ad 100644
---
This needs proper enablement to avoid machine hangs, so let's just avoid
it for now.
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |4
1 file changed, 4 insertions(+)
diff --git
This should be already configured when FDI auto-negotiation is done.
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
This attempts to enable all the available power wells during the
initialization.
Those power wells can be enabled in parallel or on-demand, and disabled
when no longer needed, but this is out of scope of this initial
enablement. Proper tracking of who uses which power well will require
a
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 880c4f7..58fcfae 100644
---
The line time can be programmed according to the number of horizontal
pixels vs effective pixel rate ratio.
v2: improve comment as per Chris Wilson suggestion
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 13 +
1 file changed, 13
Digital port detection on Haswell is indicated by the presence of a bit in
DDI_BUF_CTL for port A, and by a different register for ports B, C and D.
So we check for those bits during the initialization time and let the hdmi
function know about those.
Note that this bit does not indicates whether
Those registers are used to train DDI buffer translations for each link
type.
v2: access each port registers through the DDI_BUF_TRANS macro
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |7 +++
1 file changed, 7 insertions(+)
diff --git
They work differently, but the count is the same.
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c
Watermark line time registers for display low power watermark.
v2: improve bit names as suggested by Chris Wilson
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++
1 file changed, 10 insertions(+)
diff --git
The WR PLL can drive the DDI ports at fixed frequencies for HDMI, DVI, DP
and FDI.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
-- THIS PATCH IS NOT INTENDED FOR MERGING. IT IS MERELY HERE TO SIMPLIFY
THE DEBUGGING --
This patch is here for make debugging and log tracing easier, it should
go away in the future, when we'll stop hitting those code paths.
v2: cope with changes in bit names
Signed-off-by: Eugeni Dodonov
There is one instance of those registers for each DDI port.
v2: access registers via the DDI_BUF_CTL() macro
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 23 +++
1 file
This PLL control can drive DDI ports at desired frequencies for
DisplayPort and FDI connections.
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff
The iCLKIP clock is used to drive the VGA pixel clock on the PCH. In order
to do so, it must be programmed to properly do the clock ticks according
to the divisor, phase direction, phase increments and a special auxiliary
divisor for 20MHz clock.
Those values can be programmed individually, by
Pixel clock gating control for Lynx point.
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
Different registers are identified by their target id and offset. To
simplify their programming, they are called as RegisterNameTargetId.
For example, SSCCTL register accessed through SBI at target id 6 and
offset 0c is called SBI_SSCCTL6.
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
Those are used to control the display core clock.
v2: change the enable bit setting, spotted by Rodrigo Vivi.
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |7 +++
1 file changed, 7
Buffer translations for DDI links must be initialized prior to enablement.
For FDI and DP, first 9 pairs of values are used to select the connection
parameters. HDMI uses the last pair of values and ignores the first 9
pairs. So we program HDMI values in both cases, which allows HDMI to work
over
This patch attempts at following the modeset sequence closely, retrying
with different voltages if the DP_TP_STATUS reports a failed training.
For training, we add a table of recommended settings for FDI, HDMI and DP
connections. For FDI and DP modes, we also add the HDMI buffer
translation as
Those are responsible for the Sideband Interface programming.
v2: rename SBI bits to better reflect their meaning
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 12
1 file changed, 12
At Thu, 29 Mar 2012 08:07:05 -0700,
Keith Packard wrote:
On Thu, 29 Mar 2012 13:44:28 +0100, Chris Wilson ch...@chris-wilson.co.uk
wrote:
In conjunction with bits Power Sequence Progress field and Power Cycle
Delay Active, this bit set to a one indicates that the panel is
currently
#part sign=pgpmime
On Thu, 29 Mar 2012 18:12:56 +0200, Takashi Iwai ti...@suse.de wrote:
The strange thing is that, although you can recover the display by
turning off LVDS and on again once when the problem happens, but then
the display starts flickering. And, the flickering continues even
At Thu, 29 Mar 2012 09:57:41 -0700,
Keith Packard wrote:
#part sign=pgpmime
On Thu, 29 Mar 2012 18:12:56 +0200, Takashi Iwai ti...@suse.de wrote:
The strange thing is that, although you can recover the display by
turning off LVDS and on again once when the problem happens, but then
the
On Sun, Mar 18, 2012 at 01:39:45PM -0700, Ben Widawsky wrote:
Implement the context switch code as well as the interfaces to do the
context switch. This patch also doesn't match 1:1 with the RFC patches.
The main difference is that from Daniel's responses the last context
object is now stored
On Thu, 29 Mar 2012 20:24:11 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Sun, Mar 18, 2012 at 01:39:45PM -0700, Ben Widawsky wrote:
Implement the context switch code as well as the interfaces to do the
context switch. This patch also doesn't match 1:1 with the RFC patches.
The main
On Sun, Mar 18, 2012 at 01:39:45PM -0700, Ben Widawsky wrote:
Implement the context switch code as well as the interfaces to do the
context switch. This patch also doesn't match 1:1 with the RFC patches.
The main difference is that from Daniel's responses the last context
object is now stored
On Thu, Mar 29, 2012 at 11:43:12AM -0700, Ben Widawsky wrote:
On Thu, 29 Mar 2012 20:24:11 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Sun, Mar 18, 2012 at 01:39:45PM -0700, Ben Widawsky wrote:
Implement the context switch code as well as the interfaces to do the
context switch. This
On Sun, Mar 18, 2012 at 01:39:49PM -0700, Ben Widawsky wrote:
From http://intellinuxgraphics.org/documentation/SNB/IHD_OS_Vol1_Part3.pdf
[DevSNB] If Flush TLB invalidation Mode is enabled it’s the driver’s
responsibility to invalidate the TLBs at least once after the previous
context switch
On Sun, Mar 18, 2012 at 01:39:51PM -0700, Ben Widawsky wrote:
To keep things as sane as possible, switch to the default context before
idling. This should help free context objects, as well as put things in
a more well defined state before suspending.
Signed-off-by: Ben Widawsky
Before Chris get's all mad and complains that I did the opposite with
semaphores - semaphores did have a bit of logic which many had found
confusing and it was greatly simplified by abstracting it.
Anyhow, this removes a few lines that really didn't serve much purpose.
It also seems I can
On Sun, Mar 18, 2012 at 01:39:52PM -0700, Ben Widawsky wrote:
paranoia
For context support the HW expects the default context to always be
available as there is no way to shut off HW contexts once turned on
(afaics). This is problematic when unloading the driver as we have no
way to prevent
On Sun, Mar 18, 2012 at 01:39:53PM -0700, Ben Widawsky wrote:
Add the interfaces to allow user space to create and destroy contexts.
Contexts are destroyed automatically if the file descriptor for the dri
device is closed.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
On Sun, Mar 18, 2012 at 01:39:54PM -0700, Ben Widawsky wrote:
Use the rsvd1 field in execbuf2 to specify the context ID associated
with the workload. This will allow the driver to do the proper context
switch when/if needed.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
On Sun, Mar 18, 2012 at 01:39:56PM -0700, Ben Widawsky wrote:
Ironlake RC6 needs to allocate a power context object which the hardware
can automatically switch to. Since the new context code nicely handles
contexts, create some interfaces so we can hook up the existing code to
the new code.
On Sun, Mar 18, 2012 at 01:39:57PM -0700, Ben Widawsky wrote:
Use the context interfaces to create the power context. Assuming we
have a default context, there should be no need to switch to
the render context anymore as the default context should already serve
this purpose.
As a double
On Mon, Mar 19, 2012 at 11:14:32AM +0100, Daniel Vetter wrote:
On Sun, Mar 18, 2012 at 01:39:40PM -0700, Ben Widawsky wrote:
The patches have changed quite a bit since the RFC, and therefore I
didn't feel comfortable trying to do v2 information. I didn't feel
comfortable taking the few r-bs
On Thu, Mar 29, 2012 at 12:32:28PM -0300, Eugeni Dodonov wrote:
Reviewed-by: Rodrigo Vivi rodrigo.v...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |3 +++
1 file changed, 3 insertions(+)
diff --git
On Thu, Mar 29, 2012 at 12:32:30PM -0300, Eugeni Dodonov wrote:
With Lynx Point, we need to use SBI to communicate with the display clock
control. This commit adds helper functions to access the registers via
SBI.
v2: de-inline the function and address changes in bits names
v1
On Thu, 29 Mar 2012 21:29:05 +0200, Daniel Vetter dan...@ffwll.ch wrote:
On Sun, Mar 18, 2012 at 01:39:51PM -0700, Ben Widawsky wrote:
To keep things as sane as possible, switch to the default context before
idling. This should help free context objects, as well as put things in
a more well
On Thu, 29 Mar 2012 12:26:49 -0700, Ben Widawsky b...@bwidawsk.net wrote:
Before Chris get's all mad and complains that I did the opposite with
semaphores - semaphores did have a bit of logic which many had found
confusing and it was greatly simplified by abstracting it.
Anyhow, this removes
On Thu, Mar 29, 2012 at 12:32:38PM -0300, Eugeni Dodonov wrote:
DDIA is detected via the DDI_BUF_CTL registers bit 0, but for DDIB, DDIC
and DDID we need to consult SFUSE_STRAP values.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h |7 +++
This adds PCI ID for IVB GT2 server variant which we were missing.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/char/agp/intel-agp.h|1 +
drivers/char/agp/intel-gtt.c|2 ++
drivers/gpu/drm/i915/i915_drv.c |1 +
3 files changed, 4 insertions(+)
diff
From: Eugeni Dodonov eug...@dodonov.net
We were missing this one and it is being used by Bromolow.
Signed-off-by: Eugeni Dodonov eug...@dodonov.net
---
intel/intel_chipset.h |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
This is the GT2 variant of Ivy Bridge server chip.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
src/intel_driver.h |1 +
src/intel_module.c |2 ++
2 files changed, 3 insertions(+)
diff --git a/src/intel_driver.h b/src/intel_driver.h
index e9d6d9e..98973e5 100644
---
We can now open-code the get/put irq functions as they were just
abstracting single register definitions.
It would be nice to merge this in with the IRQ handling code... but that
is too much work for me at present. In addition I could probably
collapse this in to a lot of the Ironlake stuff, but
- gen6 put/get only need one argument
rflags and gflags are always the same (see above explanation)
- remove a couple redundantly defined IRQs
- reordered some lines to make things go in descending order
Every ring has its own interrupts, enables, masks, and status bits that
are fed into the
#part sign=pgpmime
On Thu, 29 Mar 2012 20:02:01 +0200, Takashi Iwai ti...@suse.de wrote:
Sure, that'd be a preferred option.
If you have any easy test in mind, let me know.
The way I'd love to see it tested would be to capture signal traces on
the LVDS link across mode set and see what
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