Hi Jesse,
-Original Message-
From: Barnes, Jesse
Sent: Monday, April 29, 2013 11:02 PM
To: Daniel Vetter
Cc: Wang, Xingchao; Takashi Iwai; Li, Jocelyn; Daniel Vetter; Zanoni, Paulo R;
ville.syrj...@linux.intel.com; Lin, Mengdong; Girdwood, Liam R;
intel-gfx@lists.freedesktop.org;
Ben Widawsky b...@bwidawsk.net writes:
On Tue, Apr 30, 2013 at 01:30:34PM +0300, Mika Kuoppala wrote:
Before module unload is called, gpu_idle() will switch
to default context. This will increment ref count of base
object as the default context is 'running' on module unload
time. Unreference
Due to possible scheduling latencies wait_event_timeout doesn't
guarantee a non-zero return value, even if the condition becomes true
before the specified timeout expires. Thus we can incorrectly signal a
timeout and abort a DP AUX transaction.
If wait_event_timeout returns 0, it's guaranteed
On Thu, May 02, 2013 at 12:00:03PM +0300, Imre Deak wrote:
Due to possible scheduling latencies wait_event_timeout doesn't
guarantee a non-zero return value, even if the condition becomes true
before the specified timeout expires. Thus we can incorrectly signal a
timeout and abort a DP AUX
On Thu, May 2, 2013 at 11:17 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Thu, May 02, 2013 at 12:00:03PM +0300, Imre Deak wrote:
Due to possible scheduling latencies wait_event_timeout doesn't
guarantee a non-zero return value, even if the condition becomes true
before the specified
On Wed, May 01, 2013 at 05:26:38PM +0200, Daniel Vetter wrote:
On Tue, Apr 30, 2013 at 11:53 PM, Mel Gorman mgor...@suse.de wrote:
On Sat, Apr 27, 2013 at 03:19:13AM +0400, Glauber Costa wrote:
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index
On Thu, May 2, 2013 at 11:31 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, May 2, 2013 at 11:17 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Thu, May 02, 2013 at 12:00:03PM +0300, Imre Deak wrote:
Due to possible scheduling latencies wait_event_timeout doesn't
guarantee a non-zero
On Thu, 2013-05-02 at 10:17 +0100, Chris Wilson wrote:
On Thu, May 02, 2013 at 12:00:03PM +0300, Imre Deak wrote:
Due to possible scheduling latencies wait_event_timeout doesn't
guarantee a non-zero return value, even if the condition becomes true
before the specified timeout expires. Thus
On Tue, Apr 30, 2013 at 03:00:50PM -0700, Kent Overstreet wrote:
On Tue, Apr 30, 2013 at 10:53:55PM +0100, Mel Gorman wrote:
On Sat, Apr 27, 2013 at 03:19:13AM +0400, Glauber Costa wrote:
diff --git a/drivers/md/bcache/btree.c b/drivers/md/bcache/btree.c
index 03e44c1..8b9c1a6 100644
On Thu, 2013-05-02 at 11:33 +0200, Daniel Vetter wrote:
On Thu, May 2, 2013 at 11:31 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, May 2, 2013 at 11:17 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Thu, May 02, 2013 at 12:00:03PM +0300, Imre Deak wrote:
Due to possible
2013/4/30 Daniel Vetter daniel.vet...@ffwll.ch:
If we ever leak a non-DP compliant port width through here, we have a
pretty serious issue. So just rip out all these WARNs - if we need
them it's probably better to have them at a central place where we
compute the dp lane count.
Also use the
From: Chris Wilson ch...@chris-wilson.co.uk
In order to be notified of when the context and all of its associated
objects is idle (for if the context maps to a ppgtt) we need a callback
from the retire handler. We can arrange this by using the kref_get/put
of the context for request tracking and
Storing context reference into request struct
allows us to inspect context and its associated
objects when requests are retired.
Both ppgtt and arb robustness work will need
this.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |3 +++
On Thu, May 02, 2013 at 10:34:23AM -0300, Paulo Zanoni wrote:
2013/4/30 Daniel Vetter daniel.vet...@ffwll.ch:
If we ever leak a non-DP compliant port width through here, we have a
pretty serious issue. So just rip out all these WARNs - if we need
them it's probably better to have them at a
On 04/30/2013 04:41 PM, Liam Girdwood wrote:
On Tue, 2013-04-30 at 12:29 +0200, David Henningsson wrote:
On 04/29/2013 05:02 PM, Jesse Barnes wrote:
On Sat, 27 Apr 2013 13:35:29 +0200
Daniel Vetter dan...@ffwll.ch wrote:
On Sat, Apr 27, 2013 at 09:20:39AM +, Wang, Xingchao wrote:
Let me
Sorry for the following crappy message. I came travelling without my laptop.
Please note that one of my patches implement one shot shrinkers onto of
vmpressure mechanism. It can still be called frequently, because right now it
is called every time userspace would get an event. But at least it
On Thu, May 02, 2013 at 11:37:02AM +0300, Mika Kuoppala wrote:
Ben Widawsky b...@bwidawsk.net writes:
On Tue, Apr 30, 2013 at 01:30:34PM +0300, Mika Kuoppala wrote:
Before module unload is called, gpu_idle() will switch
to default context. This will increment ref count of base
object as
2013/5/2 Daniel Vetter dan...@ffwll.ch:
On Thu, May 02, 2013 at 10:34:23AM -0300, Paulo Zanoni wrote:
2013/4/30 Daniel Vetter daniel.vet...@ffwll.ch:
If we ever leak a non-DP compliant port width through here, we have a
pretty serious issue. So just rip out all these WARNs - if we need
Hi
2013/4/29 Imre Deak imre.d...@intel.com:
According to BSpec the link training sequence for eDP on HSW port-A
should be as follows:
1. link training: clock recovery
2. link training: equalization
3. link training: set idle transmission mode
4. display pipe enable
5. link training:
Instead of returning the cached value, which is just what the kernel
requested.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_sysfs.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff
Both the docs and the existing code were wrong. So fix both and use a
switch statement like we do elsewhere to make things simple clear.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_pm.c | 13 -
1 file changed, 12 insertions(+), 1
But we need to get the right stolen base and make pre-allocated objects
for BIOS stuff so we don't clobber it. If the BIOS hasn't allocated a
power context, we allocate one here too, from stolen space as required
by the docs.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
Supposedly we should use the DAC divider for 300MHz pixel clocks, but as
that doesn't actually work as well as the high freq divider here in
practice, just use the high freq divider all the time.
v2: remove unconditional write (Jesse)
check for pixel rate properly (Jesse)
v3: give up, the DAC
Hi
2013/5/1 Daniel Vetter daniel.vet...@ffwll.ch:
Every time I read hsw code I get completely confused about this. So
call it what it is more explicitly.
Also, add an LPT_TRANSCONF for the pch transcoder A and use it in
lpt-only code, to really unconfuse me.
Signed-off-by: Daniel Vetter
2013/5/1 Daniel Vetter daniel.vet...@ffwll.ch:
While at it, also extract a common helper to copy the timings from the
cpu transcoder to the pch transcoder. That way it's really explicit
how the lpt transcoder is hardcoded.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
2013/5/1 Daniel Vetter daniel.vet...@ffwll.ch:
This is possible thanks to moving the m/n stuff into pipe_config.
Unfortunately we need to move them a bit to avoid forward
declarations.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
On Thu, 2013-05-02 at 14:45 -0300, Paulo Zanoni wrote:
Hi
2013/4/29 Imre Deak imre.d...@intel.com:
According to BSpec the link training sequence for eDP on HSW port-A
should be as follows:
1. link training: clock recovery
2. link training: equalization
3. link training: set idle
On Thu, May 02, 2013 at 02:38:09PM -0300, Paulo Zanoni wrote:
2013/5/2 Daniel Vetter dan...@ffwll.ch:
On Thu, May 02, 2013 at 10:34:23AM -0300, Paulo Zanoni wrote:
2013/4/30 Daniel Vetter daniel.vet...@ffwll.ch:
If we ever leak a non-DP compliant port width through here, we have a
On Tue, 23 Apr 2013 23:15:29 -0700
Ben Widawsky b...@bwidawsk.net wrote:
Because our context refcounting doesn't grab a ref at lookup time, it is
unsafe to do so without the lock.
NOTE: We don't have an easy way to put the assertion in the lookup
function which is where this really belongs.
On Tue, 23 Apr 2013 23:15:30 -0700
Ben Widawsky b...@bwidawsk.net wrote:
Because PPGTT PDEs within the GTT are calculated in cachelines
(HW guys consistency ftw) we do a divide which will wreak havoc if this
is wrong, and I know that from experience).
If/when we move to multiple PPGTTs this
Hi
2013/5/1 Daniel Vetter daniel.vet...@ffwll.ch:
- PCH_ prefix for pch registers on ibx/cpt/ppt.
- Drop the DP_ from the link defines, redundant.
- Drop the GMCH from the data defines and instead give the special g4x
registers a consistent _G4X postfix.
Signed-off-by: Daniel Vetter
2013/5/1 Daniel Vetter daniel.vet...@ffwll.ch:
Only one caller. Also drop the intel_ prefix as is now customary for
platform specific and static functions.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com
---
On Tue, 23 Apr 2013 23:15:31 -0700
Ben Widawsky b...@bwidawsk.net wrote:
Accomplish this be removing the PDE count define which is (and has
always been) part of the PPGTT structure anyway. With the addition of
the gen specific init function, we can nicely tuck away the magic number
in there.
On Tue, 23 Apr 2013 23:15:32 -0700
Ben Widawsky b...@bwidawsk.net wrote:
It also makes some sense IMO to have these two functions separate
irrespective of the number of callers.
Only the single caller for now, but that will change as we add more
PPGTTs.
Signed-off-by: Ben Widawsky
On Tue, 23 Apr 2013 23:15:34 -0700
Ben Widawsky b...@bwidawsk.net wrote:
I think this is a nice generalization on it's own, but it's primarily
prep work for my PPGTT support. Does this bother anyone?
The only down side I can see is we waste 2k of cpu unmappable space
(unless we have
Hi
2013/4/25 Jesse Barnes jbar...@virtuousgeek.org:
And put the pfit stuff into substructs while we're at it.
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h |2 --
drivers/gpu/drm/i915/intel_ddi.c |2 +-
We can't read the pfit regs if the power well is off, so use the cached
value.
However, I think this check is incorrect (it was taken from an earlier
check against dev_priv). We should probably just drop it altogether,
since the panel fitter isn't useful without a pipe to fetch from and
an
We can't read the pfit regs if the power well is off, so use the cached
value.
v2: re-add lost comment (Jesse)
make sure the crtc using the fitter is actually enabled (Jesse)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file
On Thu, May 02, 2013 at 02:26:17PM -0700, Jesse Barnes wrote:
On Tue, 23 Apr 2013 23:15:31 -0700
Ben Widawsky b...@bwidawsk.net wrote:
Accomplish this be removing the PDE count define which is (and has
always been) part of the PPGTT structure anyway. With the addition of
the gen specific
On Thu, 2 May 2013 15:49:17 -0700
Ben Widawsky b...@bwidawsk.net wrote:
On Thu, May 02, 2013 at 02:26:17PM -0700, Jesse Barnes wrote:
On Tue, 23 Apr 2013 23:15:31 -0700
Ben Widawsky b...@bwidawsk.net wrote:
Accomplish this be removing the PDE count define which is (and has
always
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