On Fri, May 03, 2013 at 10:40:17PM +0200, Daniel Vetter wrote:
>On Fri, May 3, 2013 at 10:31 PM, Josh Boyer wrote:
>> OK. Git bisect tells me this:
>>
>> 57c219633275c7e7413f8bc7be250dc092887458 is the first bad commit
>> commit 57c219633275c7e7413f8bc7be250dc092887458
>> Author: Daniel Vetter
>
On Fri, May 03, 2013 at 03:55:34PM +0800, Zhong Li wrote:
> Signed-off-by: Zhong Li
> ---
> tests/gem_dummy_reloc_loop.c | 21 +
> 1 file changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/tests/gem_dummy_reloc_loop.c b/tests/gem_dummy_reloc_loop.c
> index b67c7d3..
On Fri, May 03, 2013 at 03:54:48PM +0800, Zhong Li wrote:
> Signed-off-by: Zhong Li
>
> 1. add functions check kernel enable a ring or not.
> 2. add function gem_get_num_rings() to check how many rings kernel has enable.
> 3. gem_ring_sync_loop.c will call gem_get_num_rings() directly instead of
When the recent pde calculation was fixed in:
commit 43b27290dd42b40f3f23f49677a7faa5a4eb1eff
Author: Zhang, Xiong Y
Date: Sat Apr 27 09:53:33 2013 +
drm/i915: correct the calculation of first_pd_entry_in_global_pt
It had whitespace errors which I thought Daniel caught and fixed on
mer
On Thu, May 02, 2013 at 04:48:08PM +0300, Mika Kuoppala wrote:
> Storing context reference into request struct
> allows us to inspect context and its associated
> objects when requests are retired.
>
> Both ppgtt and arb robustness work will need
> this.
>
> Signed-off-by: Mika Kuoppala
Both 1&
On Fri, 3 May 2013 15:34:41 -0700
Jesse Barnes wrote:
> We need this for comparing modes between configuration changes.
>
> v2: try harder to calulate non-simple pixel clocks (Daniel)
> call get_clock after getting the encoder config, needed for pixel multiply
> (Jesse)
>
In reply to
commit b7eab0f52c47c06fc5daa20d40359a97d5d5d3a7
Author: Jesse Barnes
Date: Thu May 2 15:30:47 2013 -0700
drm/i915: fix Haswell pfit power well check v2
The above commit got rid of the I915_WRITE making the dev_priv no longer
used. Should be squashed if not too late.
CC: Jesse Barnes
Sign
We need this for comparing modes between configuration changes.
v2: try harder to calulate non-simple pixel clocks (Daniel)
call get_clock after getting the encoder config, needed for pixel multiply
(Jesse)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h |1 +
d
We need this for comparing modes between configuration changes.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 49 +-
1 file changed, 43 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i
On Fri, May 3, 2013 at 10:31 PM, Josh Boyer wrote:
> OK. Git bisect tells me this:
>
> 57c219633275c7e7413f8bc7be250dc092887458 is the first bad commit
> commit 57c219633275c7e7413f8bc7be250dc092887458
> Author: Daniel Vetter
> Date: Thu Apr 4 17:19:37 2013 +0200
>
> drm/i915: revert eDP b
On Fri, May 03, 2013 at 12:57:20PM -0400, Josh Boyer wrote:
>On Fri, May 03, 2013 at 06:08:52PM +0200, Daniel Vetter wrote:
>>On Fri, May 3, 2013 at 4:39 PM, Josh Boyer wrote:
>>> On Fri, May 03, 2013 at 02:25:57AM +0100, Dave Airlie wrote:
The following changes since commit b6a9b7f6b1f21735a7
This regression was introduced in:
commit b074cec8c652f2d273907a4b35239b4766c894ac
Author: Jesse Barnes
Date: Thu Apr 25 12:55:02 2013 -0700
drm/i915: move PCH pfit controls into pipe_config
In refactoring this, it was only applied to eDP, which is incorrect. In
fact, if we ever use the
From: Paulo Zanoni
Commit 1544d9d57396d5c0c6b7644ed5ae1f4d6caad07a added a workaround
inside haswell_init_clock_gating and mentioned it is "a workaround for
early silicon revisions and should be removed later". This workaround
is documented in bit 31 of PRI_CTL. I asked Arthur and he mentioned
th
From: Paulo Zanoni
And the SNB_READ_WM0_LATENCY macro is not valid anymore because we
have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if
the new one is not zero.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c |2 +-
1 file changed, 1 insertion(+), 1 delet
From: Paulo Zanoni
Remove the "placeholder" comment and set the actual value described by
the specification. We still don't enable IPS, but it won't hurt to
already have the value set here.
While at it, fully set the register value instead of just masking the
values we're changing.
Signed-off-b
From: Paulo Zanoni
With this, that 338 can finally become the correct 337500.
Due to the change we need to adjust the intel_dp_aux_ch function to
set the correct value, so adjust the division and also use
DIV_ROUND_CLOSEST instead of the old "round down" behavior because the
spec says the value
From: Paulo Zanoni
If we're using DP/eDP, adjusted_mode->clock may be just the port link
clock, but we also can't use mode->clock because it's wrong when we're
using the using panel fitter.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c |8 +++-
1 file changed, 7 inser
From: Paulo Zanoni
Move the "*8" calculation to the left side so we don't propagate
rounding errors. Also use DIV_ROUND_CLOSEST because that's what the
spec says we need to do.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c |2 +-
1 file changed, 1 insertion(+), 1 deletio
From: Paulo Zanoni
... instead of mode->crtc_display. The spec says "pipe horizontal
total number of pixels" and the "Haswell Watermark Calculator" tool
uses the "Pipe H Total" instead of "Pipe H Src" as the value.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_pm.c |2 +-
1 fi
From: Paulo Zanoni
The spec says the linetime watermarks must be programmed before
enabling any display low power watermarks, but we're currently
updating the linetime watermarks after we call intel_update_watermarks
(and only at crtc_mode_set, not at crtc_{enable,disable}). So IMHO the
best way
From: Paulo Zanoni
So don't call intel_update_linetime_watermarks from
ironlake_crtc_mode_set. Only Haswell has these watermarks.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c |2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b
From: Paulo Zanoni
Hi
All our Haswell watermarks code does not follow our specifications, and this
series only does some small fixes and also fixes the linetime watermarks. For
the other watermarks we're still calling the old sandybridge update_wm
functions, so the next patches will implement Ha
On Fri, 3 May 2013 22:15:27 +0200
Daniel Vetter wrote:
> On Fri, May 3, 2013 at 10:03 PM, Jesse Barnes
> wrote:
> > In refactoring this, it was only applied to eDP, which is incorrect. In
> > fact, if we ever use the panel fitter to deal with overscan on HDMI,
> > we'll need to extend it again
On Fri, May 3, 2013 at 10:03 PM, Jesse Barnes wrote:
> In refactoring this, it was only applied to eDP, which is incorrect. In
> fact, if we ever use the panel fitter to deal with overscan on HDMI,
> we'll need to extend it again.
>
> Signed-off-by: Jesse Barnes
Citation of regressing commit is
This allows us to drop a bunch of ugly hacks and finally implement
what
commit cc464b2a17c59adedbdc02cc54341d630354edc3
Author: Paulo Zanoni
Date: Fri Jan 25 16:59:16 2013 -0200
drm/i915: set TRANSCODER_EDP even earlier
tried to achieve, but that was reverted again in
commit bba2181c49f1
In refactoring this, it was only applied to eDP, which is incorrect. In
fact, if we ever use the panel fitter to deal with overscan on HDMI,
we'll need to extend it again.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c |3 ++-
1 file changed, 2 insertions(+), 1 deletio
Hi all,
Merge windows opens, so we'll start with the first feature batch for 3.11.
Highlights (part of it already in the previous testing cycle, but
postponed for 3.11):
- fixes for the gmch modeset sequence
- a bit of OCD around plane/pipe usage (Ville)
- vlv turbo support (Jesse)
- tons of vlv m
On Thu, May 02, 2013 at 10:48:10AM -0700, Jesse Barnes wrote:
> But we need to get the right stolen base and make pre-allocated objects
> for BIOS stuff so we don't clobber it. If the BIOS hasn't allocated a
> power context, we allocate one here too, from stolen space as required
> by the docs.
>
On Thu, May 02, 2013 at 10:48:08AM -0700, Jesse Barnes wrote:
> Both the docs and the existing code were wrong. So fix both and use a
> switch statement like we do elsewhere to make things simple & clear.
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel_pm.c | 13 +++
We did not mention the workaround name when implementing those. This
should help us track what we already implement.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_gem_context.c | 1 +
drivers/gpu/drm/i915/intel_ddi.c| 2 ++
drivers/gpu/drm/i915/intel_display.c| 4 ++--
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/i915_drv.c | 6 ++--
drivers/gpu/drm/i915/intel_pm.c | 77 +
2 files changed, 42 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 624
We document the implemented workarounds with
workaround_name:platforms
with platforms being a comma separated list of 3-letters platform names.
This scripts gather those tags and output a summary of implemented work
arounds. Example usages:
$ ./scripts/list-workarounds ~/gfx/sources/linux-2.6
From: Imre Deak
Currently the driver's assumed behavior for a modeset with an attached
FB is that the corresponding connector will be switched to DPMS ON mode
if it happened to be in DPMS OFF (or another power save mode). This
wasn't enforced though if only the FB changed, everything else (format
On Fri, May 03, 2013 at 02:22:09PM +0300, Imre Deak wrote:
> Currently the driver's assumed behavior for a modeset with an attached
> FB is that the corresponding connector will be switched to DPMS ON mode
> if it happened to be in DPMS OFF (or another power save mode). This
> wasn't enforced thoug
Read the current hardware state to retrieve the active mode and populate
our CRTC config if that mode matches our presumptions.
v2: check that get_hw_state gave us a valid pipe (Imre)
add clock_get for ILK+ (Jesse)
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_crt.c | 22
On Fri, May 03, 2013 at 06:08:52PM +0200, Daniel Vetter wrote:
>On Fri, May 3, 2013 at 4:39 PM, Josh Boyer wrote:
>> On Fri, May 03, 2013 at 02:25:57AM +0100, Dave Airlie wrote:
>>>The following changes since commit b6a9b7f6b1f21735a7456d534dc0e68e61359d2c:
>>>
>>> mm: prevent mmap_cache race in
On Fri, May 3, 2013 at 6:36 PM, Chris Wilson wrote:
> Along the modesetting short cut where we skip trying to do a full
> modeset and instead simply update the framebuffer base registers, we
> failed to handle any errors reported.
>
> Signed-off-by: Chris Wilson
This regression has been introdu
On Fri, May 3, 2013 at 6:28 PM, Chris Wilson wrote:
> Not quite. It was added afterwards, I know for it is one of my mistakes
> that I belatedly recognised as trying to workaround a bug in UXA. And we
> then layered on further bugs to try and patch up the glaring holes then
> introduced.
I've don
Along the modesetting short cut where we skip trying to do a full
modeset and instead simply update the framebuffer base registers, we
failed to handle any errors reported.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_display.c | 25 ++---
1 file changed, 10 i
On Fri, May 03, 2013 at 05:55:31PM +0200, Daniel Vetter wrote:
> On Fri, May 3, 2013 at 2:22 PM, Chris Wilson wrote:
> > On Fri, May 03, 2013 at 02:55:45PM +0300, Imre Deak wrote:
> >> On Fri, 2013-05-03 at 12:44 +0100, Chris Wilson wrote:
> >> > On Fri, May 03, 2013 at 02:22:09PM +0300, Imre Deak
On Fri, 3 May 2013 17:55:31 +0200
Daniel Vetter wrote:
> On Fri, May 3, 2013 at 2:22 PM, Chris Wilson wrote:
> > On Fri, May 03, 2013 at 02:55:45PM +0300, Imre Deak wrote:
> >> On Fri, 2013-05-03 at 12:44 +0100, Chris Wilson wrote:
> >> > On Fri, May 03, 2013 at 02:22:09PM +0300, Imre Deak wrote
On Fri, May 03, 2013 at 08:53:20AM -0700, Ben Widawsky wrote:
> On Fri, May 03, 2013 at 04:29:08PM +0300, Mika Kuoppala wrote:
> > Before module unload is called, gpu_idle() will switch
> > to default context. This will increment ref count of base
> > object as the default context is 'running' on m
On Fri, May 03, 2013 at 12:01:49PM -0300, Paulo Zanoni wrote:
> 2013/5/3 Mika Kuoppala :
> > Jesse Barnes writes:
> >
> >> We can't read the pfit regs if the power well is off, so use the cached
> >> value.
> >>
> >> v2: re-add lost comment (Jesse)
> >> make sure the crtc using the fitter is a
From: Jan-Simon Möller
Description:
intel_gmbus_is_forced_bit is no extern as its body is right below.
Likewise for intel_gmbus_is_port_valid.
This fixes a compilation issue with clang. An initial version of this patch
was developed by PaX Team .
This is respin of this patch.
Signed-off-by: Jan
On Fri, May 03, 2013 at 03:03:37PM +0300, Jani Nikula wrote:
> On Fri, 03 May 2013, Daniel Vetter wrote:
> > On Fri, May 03, 2013 at 11:17:42AM +0200, dl...@gmx.de wrote:
> >> From: Jan-Simon Möller
> >>
> >> Description:
> >> intel_gmbus_is_forced_bit is no extern as its body is right below.
>
On Fri, May 3, 2013 at 4:39 PM, Josh Boyer wrote:
> On Fri, May 03, 2013 at 02:25:57AM +0100, Dave Airlie wrote:
>>The following changes since commit b6a9b7f6b1f21735a7456d534dc0e68e61359d2c:
>>
>> mm: prevent mmap_cache race in find_vma() (2013-04-04 11:46:28 -0700)
>>
>>are available in the git
On Fri, May 3, 2013 at 2:22 PM, Chris Wilson wrote:
> On Fri, May 03, 2013 at 02:55:45PM +0300, Imre Deak wrote:
>> On Fri, 2013-05-03 at 12:44 +0100, Chris Wilson wrote:
>> > On Fri, May 03, 2013 at 02:22:09PM +0300, Imre Deak wrote:
>> > > Currently the driver's assumed behavior for a modeset wi
On Fri, May 03, 2013 at 04:29:08PM +0300, Mika Kuoppala wrote:
> Before module unload is called, gpu_idle() will switch
> to default context. This will increment ref count of base
> object as the default context is 'running' on module unload
> time. Unreference the drm object so that when context
>
Hi Takashi,
> -Original Message-
> From: Takashi Iwai [mailto:ti...@suse.de]
> Sent: Friday, May 03, 2013 10:27 PM
> To: Barnes, Jesse
> Cc: Daniel Vetter; Wang, Xingchao; Li, Jocelyn; Daniel Vetter; Zanoni, Paulo
> R;
> ville.syrj...@linux.intel.com; Lin, Mengdong; Girdwood, Liam R;
> in
From: Paulo Zanoni
We already have the same check on intel_enable_ddi. This patch
prevents "unclaimed register" messages when the power well is
disabled.
V2: Reset intel_crtc->eld_vld to false after the mode_set function.
V3: Add both "type != INTEL_OUTPUT_EDP" requested.
Signed-off-by: Paulo Z
From: Paulo Zanoni
This fixes "unclaimed register" messages when the power well is
disabled and there's a GPU hang.
v2: Use the new intel_display_power_enabled().
v3: Use the new domains for intel_display_power_enabled().
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c |4
From: Paulo Zanoni
In the error state function we read the registers without checking if
the power well is on, so after doing this we have to clear the
FPGA_DBG_RM_NOCLAIM bit to prevent the next I915_WRITE from detecting
it and printing an error message.
The first version of this patch was chec
From: Paulo Zanoni
We need to dump these registers if we want to properly interpret the
others.
Signed-off-by: Paulo Zanoni
Reviewed-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_display.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_disp
From: Paulo Zanoni
This should replace intel_using_power_well. The idea is that we're
adding the requested power domain as an argument, so this might enable
the code to look less platform-specific and also allows us to easily
add new domains in case we need.
v2: Add more domains to enum intel_di
2013/5/3 Mika Kuoppala :
> Jesse Barnes writes:
>
>> We can't read the pfit regs if the power well is off, so use the cached
>> value.
>>
>> v2: re-add lost comment (Jesse)
>> make sure the crtc using the fitter is actually enabled (Jesse)
>>
>> Signed-off-by: Jesse Barnes
>> ---
>> drivers/
2013/5/3 Daniel Vetter :
> On Fri, May 3, 2013 at 11:49 AM, Daniel Vetter wrote:
>> With the hw state readout&check code it's important that the values we
>> keep around are the canonical ones. Unfortunately when adding the pipe
>> timings readout support I've missed that the write side adjusts th
At Fri, 03 May 2013 14:02:04 +0200,
David Henningsson wrote:
>
> On 05/03/2013 10:28 AM, Wang, Xingchao wrote:
> > Hi David,
> >
> > Thank you very much for your draft patch.
> > I have some more work on a new patchset, some ideas are from your patch.
>
> Thanks.
>
> > Here's a brief introductio
At Mon, 29 Apr 2013 08:02:19 -0700,
Jesse Barnes wrote:
>
> On Sat, 27 Apr 2013 13:35:29 +0200
> Daniel Vetter wrote:
>
> > On Sat, Apr 27, 2013 at 09:20:39AM +, Wang, Xingchao wrote:
> > > Let me throw a basic proposal on Audio driver side, please give your
> > > comments freely.
> > >
>
2013/5/3 Daniel Vetter :
> While at it, also extract a common helper to copy the timings from the
> cpu transcoder to the pch transcoder. That way it's really explicit
> how the lpt transcoder is hardcoded.
>
> v2:
> - Re-align #defines properly (Paulo).
> - Use cpu_transcoder when copying pipe tim
This is a probable reason for some of the sporadic kms_flip failures.
One such is https://bugs.freedesktop.org/show_bug.cgi?id=59834.
v2:
- use unsigned long for KDSETMODE/KDGETMODE
- fix passing the parameter to KDGETMODE as it should be by value
- actually testing that it works..
Signed-off-by:
Before module unload is called, gpu_idle() will switch
to default context. This will increment ref count of base
object as the default context is 'running' on module unload
time. Unreference the drm object so that when context
is freed, base object is freed as well.
v2: added comment to explain th
Jesse Barnes writes:
> We can't read the pfit regs if the power well is off, so use the cached
> value.
>
> v2: re-add lost comment (Jesse)
> make sure the crtc using the fitter is actually enabled (Jesse)
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel_display.c |2 +
This is a probable reason for some of the sporadic kms_flip failures.
One such is https://bugs.freedesktop.org/show_bug.cgi?id=59834.
Signed-off-by: Imre Deak
---
tests/kms_flip.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/tests/kms_fli
On Fri, 2013-05-03 at 13:22 +0100, Chris Wilson wrote:
> On Fri, May 03, 2013 at 02:55:45PM +0300, Imre Deak wrote:
> > On Fri, 2013-05-03 at 12:44 +0100, Chris Wilson wrote:
> > > On Fri, May 03, 2013 at 02:22:09PM +0300, Imre Deak wrote:
> > > > Currently the driver's assumed behavior for a modes
On Fri, May 03, 2013 at 02:55:45PM +0300, Imre Deak wrote:
> On Fri, 2013-05-03 at 12:44 +0100, Chris Wilson wrote:
> > On Fri, May 03, 2013 at 02:22:09PM +0300, Imre Deak wrote:
> > > Currently the driver's assumed behavior for a modeset with an attached
> > > FB is that the corresponding connecto
On Fri, 03 May 2013, Daniel Vetter wrote:
> On Fri, May 03, 2013 at 11:17:42AM +0200, dl...@gmx.de wrote:
>> From: Jan-Simon Möller
>>
>> Description:
>> intel_gmbus_is_forced_bit is no extern as its body is right below.
>> Likewise for intel_gmbus_is_port_valid.
>>
>> This fixes a compilation
On 05/03/2013 10:28 AM, Wang, Xingchao wrote:
Hi David,
Thank you very much for your draft patch.
I have some more work on a new patchset, some ideas are from your patch.
Thanks.
Here's a brief introduction of attached patchset:
1. a new bus type in /sound/had_bus.c, used to bind the single
On Fri, 2013-05-03 at 12:44 +0100, Chris Wilson wrote:
> On Fri, May 03, 2013 at 02:22:09PM +0300, Imre Deak wrote:
> > Currently the driver's assumed behavior for a modeset with an attached
> > FB is that the corresponding connector will be switched to DPMS ON mode
> > if it happened to be in DPMS
On Fri, 03 May 2013, Imre Deak wrote:
> Currently the driver's assumed behavior for a modeset with an attached
> FB is that the corresponding connector will be switched to DPMS ON mode
> if it happened to be in DPMS OFF (or another power save mode). This
> wasn't enforced though if only the FB cha
On Fri, May 03, 2013 at 02:22:09PM +0300, Imre Deak wrote:
> Currently the driver's assumed behavior for a modeset with an attached
> FB is that the corresponding connector will be switched to DPMS ON mode
> if it happened to be in DPMS OFF (or another power save mode). This
> wasn't enforced thoug
On Fri, 2013-05-03 at 13:32 +0200, Daniel Vetter wrote:
> On Fri, May 3, 2013 at 1:27 PM, Daniel Vetter wrote:
> > On Fri, May 3, 2013 at 1:22 PM, Imre Deak wrote:
> >> Currently the driver's assumed behavior for a modeset with an attached
> >> FB is that the corresponding connector will be switc
On Fri, May 3, 2013 at 1:27 PM, Daniel Vetter wrote:
> On Fri, May 3, 2013 at 1:22 PM, Imre Deak wrote:
>> Currently the driver's assumed behavior for a modeset with an attached
>> FB is that the corresponding connector will be switched to DPMS ON mode
>> if it happened to be in DPMS OFF (or anot
On Fri, May 3, 2013 at 1:22 PM, Imre Deak wrote:
> Currently the driver's assumed behavior for a modeset with an attached
> FB is that the corresponding connector will be switched to DPMS ON mode
> if it happened to be in DPMS OFF (or another power save mode). This
> wasn't enforced though if only
On Fri, May 3, 2013 at 11:49 AM, Daniel Vetter wrote:
> With the hw state readout&check code it's important that the values we
> keep around are the canonical ones. Unfortunately when adding the pipe
> timings readout support I've missed that the write side adjusts the
> timings in the pipe config
On Fri, May 3, 2013 at 12:30 AM, Jesse Barnes wrote:
> We can't read the pfit regs if the power well is off, so use the cached
> value.
>
> v2: re-add lost comment (Jesse)
> make sure the crtc using the fitter is actually enabled (Jesse)
>
> Signed-off-by: Jesse Barnes
Just a quick maintaine
Currently the driver's assumed behavior for a modeset with an attached
FB is that the corresponding connector will be switched to DPMS ON mode
if it happened to be in DPMS OFF (or another power save mode). This
wasn't enforced though if only the FB changed, everything else (format,
connector etc.)
According to BSpec the link training sequence for eDP on HSW port-A
should be as follows:
1. link training: clock recovery
2. link training: equalization
3. link training: set idle transmission mode
4. display pipe enable
5. link training: disable (set normal mode)
Contrary to this at the moment
With the hw state readout&check code it's important that the values we
keep around are the canonical ones. Unfortunately when adding the pipe
timings readout support I've missed that the write side adjusts the
timings in the pipe config.
Fix this up.
Reported-by: Paulo Zanoni
Signed-off-by: Dani
Only one caller. Also drop the intel_ prefix as is now customary for
platform specific and static functions.
Reviewed-by: Paulo Zanoni
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 1 -
2 files changed, 2 insertions(+), 3
- PCH_ prefix for pch registers on ibx/cpt/ppt.
- Drop the DP_ from the link defines, redundant.
- Drop the GMCH from the data defines and instead give the special g4x
registers a consistent _G4X postfix.
v2:
- Realign #defines and use tabs (Paulo).
Reviewed-by: Paulo Zanoni
Signed-off-by: Dan
This is possible thanks to moving the m/n stuff into pipe_config.
Unfortunately we need to move them a bit to avoid forward
declarations.
Reviewed-by: Paulo Zanoni
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 68 ++--
drivers/gpu/drm/i
While at it, also extract a common helper to copy the timings from the
cpu transcoder to the pch transcoder. That way it's really explicit
how the lpt transcoder is hardcoded.
v2:
- Re-align #defines properly (Paulo).
- Use cpu_transcoder when copying pipe timings (Paulo).
- s/intel_pch_transcoder
Every time I read hsw code I get completely confused about this. So
call it what it is more explicitly.
Also, add an LPT_TRANSCONF for the pch transcoder A and use it in
lpt-only code, to really unconfuse me.
v2: s/plane/pipe/ in the TRANSCONF #define (Paulo).
Reviewed-by: Paulo Zanoni
Signed-o
On Fri, May 03, 2013 at 11:17:42AM +0200, dl...@gmx.de wrote:
> From: Jan-Simon Möller
>
> Description:
> intel_gmbus_is_forced_bit is no extern as its body is right below.
> Likewise for intel_gmbus_is_port_valid.
>
> This fixes a compilation issue with clang. An initial version of this patch
>
On Thu, May 02, 2013 at 03:12:07PM -0300, Paulo Zanoni wrote:
> Hi
>
> 2013/5/1 Daniel Vetter :
> > Every time I read hsw code I get completely confused about this. So
> > call it what it is more explicitly.
> >
> > Also, add an LPT_TRANSCONF for the pch transcoder A and use it in
> > lpt-only cod
On Thu, May 02, 2013 at 05:36:33PM -0300, Paulo Zanoni wrote:
> Hi
>
> 2013/5/1 Daniel Vetter :
> > - PCH_ prefix for pch registers on ibx/cpt/ppt.
> > - Drop the DP_ from the link defines, redundant.
> > - Drop the GMCH from the data defines and instead give the special g4x
> > registers a cons
Hi David,
Thank you very much for your draft patch.
I have some more work on a new patchset, some ideas are from your patch.
Here's a brief introduction of attached patchset:
1. a new bus type in /sound/had_bus.c, used to bind the single module and codec
device
It looks like ac97_bus.c
2. add
On Fri, May 3, 2013 at 12:02 AM, Paulo Zanoni wrote:
>> static void valleyview_crtc_enable(struct drm_crtc *crtc)
>> @@ -5800,6 +5798,9 @@ static void haswell_modeset_global_resources(struct
>> drm_device *dev)
>> /* XXX: Should check for edp transcoder here, but thanks to
>> in
Signed-off-by: Zhong Li
---
tests/gem_dummy_reloc_loop.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/tests/gem_dummy_reloc_loop.c b/tests/gem_dummy_reloc_loop.c
index b67c7d3..b5da577 100644
--- a/tests/gem_dummy_reloc_loop.c
+++ b/tests/gem_dummy_
Signed-off-by: Zhong Li
1. add functions check kernel enable a ring or not.
2. add function gem_get_num_rings() to check how many rings kernel has enable.
3. gem_ring_sync_loop.c will call gem_get_num_rings() directly instead of
original static fucntion get_number_rings().
---
lib/drmtest.c
I made a mistake for the patch subject. I will send a new series of patch.
Please ignore this patch.
-Original Message-
From: Li, Zhong
Sent: Friday, May 03, 2013 2:26 PM
To: intel-gfx@lists.freedesktop.org
Cc: Li, Zhong; Xiang, Haihao; Li, Jocelyn; Vetter, Daniel; b...@bwidawsk.net
Subj
I made a mistake for the patch subject and drmtest.h. I will send a new series
of patch. Please ignore this patch.
-Original Message-
From: Li, Zhong
Sent: Friday, May 03, 2013 2:26 PM
To: intel-gfx@lists.freedesktop.org
Cc: Li, Zhong; Xiang, Haihao; Li, Jocelyn; Vetter, Daniel; b...@bwi
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