On Wed, Jan 29, 2014 at 10:52:33AM +0200, Imre Deak wrote:
Also we should check whether jiffies has overflowed since the timestamp
for event A was taken. This is highly unlikely on 64 bit, but on 32 bit
machines jiffies initially is -300*HZ. If the panel power is initially
off the first wait
On Wed, 29 Jan 2014, Imre Deak imre.d...@intel.com wrote:
schedule_timeout_uninterruptible() takes jiffies not ms.
Also we should check whether jiffies has overflowed since the timestamp
for event A was taken. This is highly unlikely on 64 bit, but on 32 bit
machines jiffies initially is
On Wed, Jan 29, 2014 at 12:50:17PM +0200, Antti Koskipaa wrote:
RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.
v1: Fixed offsets for VLV, proper eDP handling
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
On Wed, Jan 22, 2014 at 5:32 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
WaDisableVDSUtnitClockGating was only relevant for early steepings of
VLV.
Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
On Wed, Jan 22, 2014 at 5:32 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
WaDisableTDLUnitClockGating is only relevant for early steppings of VLV.
Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
On Wed, Jan 22, 2014 at 5:32 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The current comments indicate that this function implements
WaVSRefCountFullforceMissDisable, which is only true for HSW.
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
On Wed, Jan 22, 2014 at 5:33 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
BSpec states that the thread override values set by
gen7_setup_fixed_func_scheduler() are invalid for HSW. So let's not
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
On Wed, Jan 22, 2014 at 5:33 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We're disabling a boatload of clock gating features on VLV. Maybe these
days we don't need to do that. At least I'm not
On Wed, Jan 29, 2014 at 01:25:41PM +0200, Imre Deak wrote:
The initial jiffies value can be non-0, so set the inital panel power
sequencer timestamps accordingly. This didn't cause a problem on 64 bit
machines but on 32 bit jiffies is initially -300*HZ, so if the panel
power is initally off in
On Wed, Jan 29, 2014 at 01:25:40PM +0200, Imre Deak wrote:
schedule_timeout_uninterruptible() takes jiffies not ms.
v2:
- ignore the overflow issue, the practical part of that should
be solved instead in the caller (Chris)
Signed-off-by: Imre Deak imre.d...@intel.com
Reviewed-by: Chris
On Wed, Jan 29, 2014 at 11:27 AM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, Jan 29, 2014 at 11:24:44AM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 11:12 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, Jan 29, 2014 at 10:47:54AM -0200, Rodrigo Vivi wrote:
This
On Wed, Jan 29, 2014 at 11:54:00AM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 11:27 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, Jan 29, 2014 at 11:24:44AM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 11:12 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On
ok, got it.
So, the correct here is to remove inactivate from set_domain and add
gem_bo_busy call on MMAP_GTT testcase?
On Wed, Jan 29, 2014 at 12:02 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, Jan 29, 2014 at 11:54:00AM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 11:27 AM,
Not your fault, just exposed under recent testing
On Wed, Jan 29, 2014 at 01:30:54PM +, Tvrtko Ursulin wrote:
+int igt_minor_evictions(int fd, struct igt_eviction_test_ops *ops,
+ int surface_size, int nr_surfaces)
+{
+ uint32_t *bo, *sel;
+ int n, m, pass,
v2: Wait psr enable with timeout and more subtest added.
v3: Add wait for v_blank leeting test more reliable and preparing to
add Baytrail per-pipe tests.
v4: Call busy_ioctl on mmap_gtt to match the real usage and remove the need
of inactivate on set_domain, what was semantically wrong.
On Wed, Jan 29, 2014 at 10:47:54AM -0200, Rodrigo Vivi wrote:
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, set_domain, sw_finish and mark_busy
and update to enable it back on next display
If we have stopped rings then we know that test is running
so no need for spam. In addition, only spam when default
context gets banned.
v2: - make sure default context ban gets shown (Chris)
- use helper for checking for default context, everywhere (Chris)
Reference:
With full ppgtt support drm_i915_file_private gained knowledge
about the default context. Also reset stats are now inside
i915_hw_context so we can use proper abstraction.
Suggested-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
These are on top of drm-intel-nightly.
Series tries to address Ben's concerns on the previous
version at: 1389968431-24123-1-git-send-email-mika.kuopp...@intel.com
Mika Kuoppala (4):
drm/i915: Use i915_hw_context to set reset stats
drm/i915: Tune down debug output when context is banned
With full ppgtt using acthd is not enough to find guilty
batch buffer. We get multiple false positives as acthd is
per vm.
Instead of scanning which vm was running on a ring,
to find corressponding context, use a different, simpler,
strategy of finding batches that caused gpu hang:
If hangcheck
Ben Widawsky b...@bwidawsk.net writes:
On Wed, Jan 22, 2014 at 05:41:29PM +0200, Mika Kuoppala wrote:
If we have stopped rings then we know that test is running
so no need for spam. In addition, only spam when default
context gets banned.
v2: - make sure default context ban gets shown
Ben Widawsky b...@bwidawsk.net writes:
On Fri, Jan 17, 2014 at 04:20:30PM +0200, Mika Kuoppala wrote:
Instead of going through all the requests to find a batch that
hanged the machine, use hangcheck score and the fact that
hung, hanged???
first noncompleted request on hanged ring is, with
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen updates and force PSR exit.
So we inactivate it on {busy_ioctl, sw_finish and mark_busy}
and update to enable it back on next display mark_idle.
v2: Also inactivate PSR on cursor update.
v3: Inactivate PSR on
On Mon, Jan 27, 2014 at 09:35:05PM +0530, deepa...@intel.com wrote:
From: Deepak S deepa...@intel.com
When current delay is already at max delay, Let's disable the PM UP
THRESHOLD INTRRUPTS, so that we will not get further interrupts until
current delay is less than max delay, Also request
The goal of this test is to ensure that we respect inter ring
dependencies. A more detailed description of what it tests is in a
comment.
The tests relies on having a blit function for the ring, so is currently
only checking synchronization between the render and blitter ring.
Signed-off-by:
On Wed, Jan 29, 2014 at 01:47:00PM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 12:56 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Wed, Jan 29, 2014 at 10:47:54AM -0200, Rodrigo Vivi wrote:
This patch adds PSR Support to Baytrail.
Baytrail cannot easily detect screen
From: Deepak S deepa...@intel.com
When current delay is already at max delay, Let's disable the PM UP
THRESHOLD INTRRUPTS, so that we will not get further interrupts until
current delay is less than max delay, Also request for the PM DOWN
THRESHOLD INTRRUPTS to indicate the decrease in clock
On Wed, Jan 29, 2014 at 2:38 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Wed, Jan 29, 2014 at 01:47:00PM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 12:56 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Wed, Jan 29, 2014 at 10:47:54AM -0200, Rodrigo Vivi wrote:
On Tue, Jan 28, 2014 at 6:29 AM, Chia-I Wu olva...@gmail.com wrote:
From: Chia-I Wu o...@lunarg.com
The optimization is available on Ivy Bridge and later, and is disabled by
default. Enabling it helps certain workloads such as GLBenchmark TRex test.
No piglit regression.
v2
- no need to
On Wed, Jan 29, 2014 at 03:48:21PM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 2:38 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Wed, Jan 29, 2014 at 01:47:00PM -0200, Rodrigo Vivi wrote:
On Wed, Jan 29, 2014 at 12:56 PM, Ville Syrjälä
ville.syrj...@linux.intel.com
On Wed, Jan 29, 2014 at 11:11:57AM -0200, Rodrigo Vivi wrote:
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
Ok, I've pulled in the last batch of reviewed patches into dinq. But I'm
not sure whether I haven't missed anything or whether there's still an
earlier patch that needs review or
On Wed, Jan 29, 2014 at 12:56:26PM -0200, Rodrigo Vivi wrote:
v2: Wait psr enable with timeout and more subtest added.
v3: Add wait for v_blank leeting test more reliable and preparing to
add Baytrail per-pipe tests.
v4: Call busy_ioctl on mmap_gtt to match the real usage and remove the
On Wed, Jan 29, 2014 at 01:37:53PM +0200, Jani Nikula wrote:
On Wed, 29 Jan 2014, Imre Deak imre.d...@intel.com wrote:
schedule_timeout_uninterruptible() takes jiffies not ms.
Also we should check whether jiffies has overflowed since the timestamp
for event A was taken. This is highly
On Wed, Jan 29, 2014 at 01:26:27PM +, Chris Wilson wrote:
On Wed, Jan 29, 2014 at 01:25:41PM +0200, Imre Deak wrote:
The initial jiffies value can be non-0, so set the inital panel power
sequencer timestamps accordingly. This didn't cause a problem on 64 bit
machines but on 32 bit
Add_request has always contained both the semaphore mailbox updates as
well as the breadcrumb writes. Since the semaphore signal is the one
which actually knows about the number of dwords it needs to emit to the
ring, we move the ring_begin to that function. This allows us to remove
the hideously
These are the remaining patches for enabling HW semaphores on Broadwell.
The patches are rebased against the latest drm-intel-nightly, and the
only other intentional modifications were those requested by Chris. The
functionality they provide is the same as before. Unfortunately, I will
not have
This abstraction again is in preparation for gen8. Gen8 will bring new
semantics for doing this operation.
While here, make the writes of MI_NOOPs explicit for non-existent rings.
This should have been implicit before.
NOTE: This is going to be removed in a few patches.
Signed-off-by: Ben
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3cfcc78..3a3ba81 100644
---
With the ring mask we now have an easy way to know the number of rings
in the system, and therefore can accurately predict the number of dwords
to emit for semaphore signalling. This was not possible (easily)
previously.
There should be no functional impact, simply fewer instructions emitted.
Gen8 has already had some differentiation with how it handles rings.
Semaphores bring yet more differences, and now is as good a time as any
to do the split.
Also, since gen8 doesn't actually use semaphores up until this point,
put the proper NULL values in for the mbox info.
v2: v1 had a stale
Since the semaphore information is in an object, just dump it, and let
the user parse it later.
NOTE: The page being used for the semaphores are incoherent with the
CPU. No matter what I do, I cannot figure out a way to read anything but
0s. Note that the semaphore waits are indeed working.
v2:
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gpu_error.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index a8b91fc..efaad96
Semaphore waits use a new instruction, MI_SEMAPHORE_WAIT. The seqno to
wait on is all well defined by the table in the previous patch. There is
nothing else different from previous GEN's semaphore synchronization
code.
v2: Update macros to not require the other ring's ring-id (Chris)
Semaphore signalling works similarly to previous GENs with the exception
that the per ring mailboxes no longer exist. Instead you must define
your own space, somewhere in the GTT.
The comments in the code define the layout I've opted for, which should
be fairly future proof. Ie. I tried to define
Simple debugfs file to display the current state of semaphores. This is
useful if you want to see the state without hanging the GPU.
NOTE: This patch is optional to the series.
NOTE2: Like the GPU error state collection, the reads are currently
incoherent.
Signed-off-by: Ben Widawsky
This will be helpful in abstracting some of the code in preparation for
gen8 semaphores.
Cc: Mika Kuoppala mika.kuopp...@linux.intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem.c | 10 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 6 +--
On Tue, Jan 28, 2014 at 06:08:38PM +, Chris Wilson wrote:
During eviction, we are only considering how to free up space within the
current address space and not concerned with freeing up physical memory.
As such we need only skip nodes that pinned in the current VM and not
globally.
From: Paulo Zanoni paulo.r.zan...@intel.com
I previously chose to keep the POSTING_READ calls as something to be
done by the macro callers, but the conclusion after discussing this on
the mailing list is that leaving the POSTING_READ calls to the macros
makes the code safer, and the additional
On Wed, Jan 29, 2014 at 01:30:54PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
A set of userptr test cases to support the new feature.
For the eviction and swapping stress testing I have extracted
some common behaviour from gem_evict_everything and made both
We need to do the print after we've done the math.
This was broken when we introduced VLV support. Personally, I think the
interface should go away now that we support it in sysfs. Historically
it has allowed users to do stupid things which we might not allow in the
sysfs interface - so we can
Blargh this isn't specific to HSW. Title should be s/HSW/gen6|gen7/
On Wed, Jan 29, 2014 at 12:20:54PM -0800, Ben Widawsky wrote:
We need to do the print after we've done the math.
This was broken when we introduced VLV support. Personally, I think the
interface should go away now that
On Tue, Jan 28, 2014 at 01:16:46PM +, Chris Wilson wrote:
By exporting the ability to map user address and inserting PTEs
representing their backing pages into the GTT, we can exploit UMA in order
to utilize normal application data as a texture source or even as a
render target (depending
Actually I've found something else to complain about:
On Tue, Jan 28, 2014 at 2:16 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
+#define I915_USERPTR_READ_ONLY 0x1
This smells like an insta-root-exploit:
1. mmap /lib/ld-linux.so as read-only
2. userptr bind that mmap'ed area as READ_ONLY
3.
On Wed, Jan 29, 2014 at 05:05:36PM +0200, Mika Kuoppala wrote:
With full ppgtt support drm_i915_file_private gained knowledge
about the default context. Also reset stats are now inside
i915_hw_context so we can use proper abstraction.
Suggested-by: Ben Widawsky b...@bwidawsk.net
On Wed, Jan 29, 2014 at 12:22:44PM -0800, Ben Widawsky wrote:
Blargh this isn't specific to HSW. Title should be s/HSW/gen6|gen7/
Fixed and merged to dinq.
-Daniel
On Wed, Jan 29, 2014 at 12:20:54PM -0800, Ben Widawsky wrote:
We need to do the print after we've done the math.
This
On Wed, Jan 29, 2014 at 05:05:37PM +0200, Mika Kuoppala wrote:
If we have stopped rings then we know that test is running
so no need for spam. In addition, only spam when default
context gets banned.
v2: - make sure default context ban gets shown (Chris)
- use helper for checking for
On Wed, Jan 29, 2014 at 12:47:13PM -0800, Ben Widawsky wrote:
On Wed, Jan 29, 2014 at 05:05:37PM +0200, Mika Kuoppala wrote:
If we have stopped rings then we know that test is running
so no need for spam. In addition, only spam when default
context gets banned.
v2: - make sure default
Request by Ben Widawsky in his review of a patch touching this code.
v2: Clarify the disdinction between evicting vmas (to free up virtual
address space) and evicting objects (to free up actual system memory).
Suggested by Ben.
Cc: Ben Widawsky benjamin.widaw...@intel.com
Acked-by: Ben Widawsky
On Wed, Jan 29, 2014 at 12:06:36PM -0800, Ben Widawsky wrote:
On Tue, Jan 28, 2014 at 06:08:38PM +, Chris Wilson wrote:
During eviction, we are only considering how to free up space within the
current address space and not concerned with freeing up physical memory.
As such we need only
On Wed, Jan 29, 2014 at 05:05:39PM +0200, Mika Kuoppala wrote:
As we seek the guilty batch using request and hangcheck
score, this code is not needed anymore.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 91
On Wed, Jan 29, 2014 at 09:34:42PM +0100, Daniel Vetter wrote:
Actually I've found something else to complain about:
On Tue, Jan 28, 2014 at 2:16 PM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
+#define I915_USERPTR_READ_ONLY 0x1
This smells like an insta-root-exploit:
1. mmap
On Wed, Jan 29, 2014 at 09:25:51PM +0100, Daniel Vetter wrote:
So originally I've thought we need this due to the massive overhead of the
mmu notifier. But now with the nice shared mmu notifiers I've thought that
overhead is gone I prefer to also ditch this option.
Same goes about the
On Wed, Jan 29, 2014 at 12:06:36PM -0800, Ben Widawsky wrote:
On Tue, Jan 28, 2014 at 06:08:38PM +, Chris Wilson wrote:
During eviction, we are only considering how to free up space within the
current address space and not concerned with freeing up physical memory.
As such we need only
From: Brad Volkin bradley.d.vol...@intel.com
Certain OpenGL features (e.g. transform feedback, performance monitoring)
require userspace code to submit batches containing commands such as
MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
generations of the hardware will noop
From: Brad Volkin bradley.d.vol...@intel.com
These are used to implement scanline waits in the X server.
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 30 ++
1 file changed, 30 insertions(+)
diff --git
From: Brad Volkin bradley.d.vol...@intel.com
These registers are currently used by mesa for blitting,
transform feedback extensions, and performance monitoring
extensions.
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 55
From: Brad Volkin bradley.d.vol...@intel.com
The spec defines most of these commands as privileged. A few others,
like the semaphore mbox command and some display commands, are also
reserved for the driver's use. Subsequent patches relax some of
these restrictions.
Signed-off-by: Brad Volkin
From: Brad Volkin bradley.d.vol...@intel.com
The driver leaves most interrupts masked during normal operation,
so there would have to be additional work to enable userspace to
safely request/receive an interrupt.
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
From: Brad Volkin bradley.d.vol...@intel.com
OTC-Tracker: AXIA-4631
Change-Id: I6747457e1fe7494bd42787af51198fcba398ad78
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Brad Volkin bradley.d.vol...@intel.com
So userspace can query the kernel for command parser support.
OTC-Tracker: AXIA-4631
Change-Id: I58af650db9f6753c2dcac9c54ab432fd31db302f
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c | 4
From: Brad Volkin bradley.d.vol...@intel.com
The command parser is going to need the same synchronization and
setup logic, so factor it out for reuse.
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_gem.c | 48
From: Brad Volkin bradley.d.vol...@intel.com
Add command tables defining irregular length commands for each ring.
This requires a few new command opcode definitions.
OTC-Tracker: AXIA-4631
Change-Id: I064bceb457e15f46928058352afe76d918c58ef5
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
From: Brad Volkin bradley.d.vol...@intel.com
The command parser scans batch buffers submitted via execbuffer ioctls before
the driver submits them to hardware. At a high level, it looks for several
things:
1) Commands which are explicitly defined as privileged or which should only be
used by
From: Brad Volkin bradley.d.vol...@intel.com
The Intel DDX uses these to implement scanline waits in the X server.
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
From: Brad Volkin bradley.d.vol...@intel.com
Various commands that access memory have a bit to determine whether
the graphics address specified in the command should use the GGTT or
PPGTT for translation. These checks ensure that the bit indicates
PPGTT translation.
Most of these checks use the
From: Brad Volkin bradley.d.vol...@intel.com
PIPE_CONTROL and MI_FLUSH_DW have bits that would write to the
hardware status page. The driver stores request tracking info
there, so don't let userspace overwrite it.
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
From: Brad Volkin bradley.d.vol...@intel.com
Start with a simple testcase that should pass.
v2: Switch to I915_PARAM_CMD_PARSER_VERSION
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
tests/.gitignore | 1 +
tests/Makefile.sources | 1 +
tests/gem_exec_parse.c | 140
From: Brad Volkin bradley.d.vol...@intel.com
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
tests/gem_exec_parse.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index 9e90408..004c3bf 100644
--- a/tests/gem_exec_parse.c
From: Brad Volkin bradley.d.vol...@intel.com
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
tests/gem_exec_parse.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index 48fde25..9e90408 100644
---
From: Brad Volkin bradley.d.vol...@intel.com
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
tests/gem_exec_parse.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index ebf7116..48fde25 100644
---
From: Brad Volkin bradley.d.vol...@intel.com
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
include/drm/i915_drm.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 2f4eb8c..ba863c4 100644
---
From: Brad Volkin bradley.d.vol...@intel.com
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
tests/gem_exec_parse.c | 81 ++
1 file changed, 81 insertions(+)
diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index
From: Brad Volkin bradley.d.vol...@intel.com
MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM, and MI_LOAD_REGISTER_IMM
commands allow userspace access to registers. Only certain registers
should be allowed for such access, so enable checking for those commands.
Each ring gets its own register
From: Brad Volkin bradley.d.vol...@intel.com
This is a speculative test in that it's not particularly relevant
today, but is important if we switch the parser implementation to
use kmap_atomic instead of vmap.
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
tests/gem_exec_parse.c | 68
On Wed, Jan 29, 2014 at 10:53 PM, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Wed, Jan 29, 2014 at 09:25:51PM +0100, Daniel Vetter wrote:
So originally I've thought we need this due to the massive overhead of the
mmu notifier. But now with the nice shared mmu notifiers I've thought that
On Wed, Jan 29, 2014 at 01:58:29PM -0800, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
tests/gem_exec_parse.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tests/gem_exec_parse.c
On Wed, Jan 29, 2014 at 01:55:01PM -0800, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
3) Coherency. I've found a coherency issue on VLV when reading the batch
buffer
from the CPU during execbuffer2. Userspace writes the batch via pwrite fast
path
On Wed, Jan 29, 2014 at 01:58:30PM -0800, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
This is a speculative test in that it's not particularly relevant
today, but is important if we switch the parser implementation to
use kmap_atomic instead of vmap.
Do
On Wed, Jan 29, 2014 at 02:11:17PM -0800, Daniel Vetter wrote:
On Wed, Jan 29, 2014 at 01:55:01PM -0800, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
3) Coherency. I've found a coherency issue on VLV when reading the batch
buffer
from the CPU during
On Wed, Jan 29, 2014 at 02:13:21PM -0800, Chris Wilson wrote:
On Wed, Jan 29, 2014 at 01:57:28PM -0800, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
include/drm/i915_drm.h | 5 +++--
1 file
On Wed, Jan 29, 2014 at 01:55:03PM -0800, bradley.d.vol...@intel.com wrote:
+/*
+ * Returns a pointer to a descriptor for the command specified by cmd_header.
+ *
+ * The caller must supply space for a default descriptor via the default_desc
+ * parameter. If no descriptor for the specified
On Wed, Jan 29, 2014 at 01:55:11PM -0800, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
Various commands that access memory have a bit to determine whether
the graphics address specified in the command should use the GGTT or
PPGTT for translation. These
On Wed, Jan 29, 2014 at 01:55:08PM -0800, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
These are used to implement scanline waits in the X server.
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 30
On Wed, Jan 29, 2014 at 02:33:55PM -0800, Chris Wilson wrote:
On Wed, Jan 29, 2014 at 01:55:11PM -0800, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
Various commands that access memory have a bit to determine whether
the graphics address specified in the
On Wed, Jan 29, 2014 at 03:00:11PM -0800, Volkin, Bradley D wrote:
On Wed, Jan 29, 2014 at 02:33:55PM -0800, Chris Wilson wrote:
On Wed, Jan 29, 2014 at 01:55:11PM -0800, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
Various commands that access memory
On Wed, Jan 29, 2014 at 02:37:25PM -0800, Chris Wilson wrote:
On Wed, Jan 29, 2014 at 01:55:08PM -0800, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
These are used to implement scanline waits in the X server.
Signed-off-by: Brad Volkin
On Wed, Jan 29, 2014 at 02:22:49PM -0800, Volkin, Bradley D wrote:
On Wed, Jan 29, 2014 at 02:11:17PM -0800, Daniel Vetter wrote:
On Wed, Jan 29, 2014 at 01:55:01PM -0800, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
3) Coherency. I've found a coherency
On Wed, Jan 29, 2014 at 9:56 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Tue, Jan 28, 2014 at 6:29 AM, Chia-I Wu olva...@gmail.com wrote:
From: Chia-I Wu o...@lunarg.com
The optimization is available on Ivy Bridge and later, and is disabled by
default. Enabling it helps certain workloads
On Jan-22-2014 6:39 PM, Jani Nikula wrote:
On Mon, 23 Dec 2013, Vandana Kannan vandana.kan...@intel.com wrote:
From: Pradeep Bhat pradeep.b...@intel.com
This patch reads the DRRS support and Mode type from VBT fields.
The read information will be stored in VBT struct during BIOS
parsing. The
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