On 9 April 2014 11:41, Dave Airlie airl...@gmail.com wrote:
On Tue, Apr 8, 2014 at 5:32 PM, Daniel J Blueman dan...@quora.org wrote:
On 8 April 2014 15:14, Jani Nikula jani.nik...@linux.intel.com wrote:
On Tue, 08 Apr 2014, Daniel J Blueman dan...@quora.org wrote:
Ville et al,
It looks like
On Tue, Apr 08, 2014 at 09:09:14PM -0700, Ben Widawsky wrote:
This is no more or less flagrant than any other use. Evict CANNOT finish
if we get interrupted by a signal. If we can't properly evict everything
from the address space, I can't make any guarantee about anything being
clean when we
Hi Chris!
The intel xorg driver cursor code is broken, at least on my system.
The last good commit is 3810cff42bca1badc5844002694a6f582c0f423.
Hardware: AOpen i915GMm-hfs with Pentium-M Dothan cpu
Software: openSuSE 13.1, kernel 3.14, xorg git master, kde
Expected behavior:
===
Hi, Sharma, Shashank
Is there any following patches to make it happen?
Thanks
Regards
Quanxian Wang
-Original Message-
From: intel-gfx-boun...@lists.freedesktop.org
[mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of Sharma, Shashank
Sent: Tuesday, January 14, 2014 1:20 AM
On Tue, Apr 08, 2014 at 10:21:44AM -0700, Ben Widawsky wrote:
I am not convinced this is the correct solution. At least the way we
used this interface, it isn't meant to ever fail. I also didn't look
into exactly why we depend an ENOSPC return. That sounds fragile to me,
especially for a
Hello Quanxian Wang
This patch is available and working on all MCG tree's (Main, R42B and R44B)
We were trying to opensource this patch, but due to the dependency on
live_status reg, we had to change the design.
I was working on that, but couldn't finish the activity yet, Thanks for
reminding
On Wed, Apr 9, 2014 at 4:07 PM, Daniel J Blueman dan...@quora.org wrote:
On 9 April 2014 11:41, Dave Airlie airl...@gmail.com wrote:
On Tue, Apr 8, 2014 at 5:32 PM, Daniel J Blueman dan...@quora.org wrote:
On 8 April 2014 15:14, Jani Nikula jani.nik...@linux.intel.com wrote:
On Tue, 08 Apr
We neither report any unfinished operations during releasing GEM objects
associated with the file, and even if we did, it is bad form to report
-EINTR from a close().
The root cause of the bug that first showed itself during close is that
we do not do proper live tracking of vma and contexts
On Wed, 09 Apr 2014, Dave Airlie airl...@gmail.com wrote:
On Wed, Apr 9, 2014 at 4:07 PM, Daniel J Blueman dan...@quora.org wrote:
On 9 April 2014 11:41, Dave Airlie airl...@gmail.com wrote:
On Tue, Apr 8, 2014 at 5:32 PM, Daniel J Blueman dan...@quora.org wrote:
On 8 April 2014 15:14, Jani
+ req = (struct drm_i915_gem_request *)
+ kmalloc(sizeof(struct drm_i915_gem_request), GFP_KERNEL);
+ req-ring = ring;
+ req-ctx = to;
+ i915_gem_context_reference(req-ctx);
+ req-tail = tail;
Need to test if the allocation has succeeded and return an error if not.
On Mon, Apr 07, 2014 at 03:05:39PM +0100, Damien Lespiau wrote:
Execlist are relatively new, and so it'd be wise to be able to merge
that support disabled by default while still allowing a module
parameter to enable that feature.
Even if we end up enabling execlists by default, it'll be
You're always calling gen8_write_pdp_ctx() and gen8_write_tail_ctx()
together, kmapping the page twice is a bit wastful.
You are totally right... I´ll join them in the next version.
-- Oscar
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
If we always initialize kref for the context, even if we are using fake
contexts for hangstats when there is no hw support, we can forgo the
dance to dereference the ctx-obj and inspect whether we are permitted
to use kref inside i915_gem_context_reference() and _unreference().
My ulterior motive
It seems to be completely managed by SW, for SW (or, at least, it does not seem
to have any visible effect in the HW). But you are right, it is probably worth
updating.
-- Oscar
-Original Message-
From: Lespiau, Damien
Sent: Thursday, April 03, 2014 3:25 PM
To: Mateo Lozano, Oscar
If we include the expected values for the failing ring register checks,
it makes it marginally easier to see which is the culprit.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
Tearing down the ring buffers across resume is overkill, risks
unnecessary failure and increases fragmentation.
After failure, since the device is still active we may end up trying to
write into the dangling iomapping and trigger an oops.
v2: stop_ringbuffers() was meant to call stop(ring) not
For readibility and guess at the meaning behind the constants.
v2: Claim only the meagerest connections with reality.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 34 -
1 file changed, 21 insertions(+), 13
Even without enabling the ringbuffers to allow command execution, we can
still control the display engines to enable modesetting. So make the
ringbuffer initialization failure soft, and mark the GPU as wedged
instead.
v2: Only treat an EIO from ring initialisation as a soft failure, and
abort
During module load, if we fail to initialise the rings, we abort the
load reporting EIO. However during resume, even though we report EIO as
we fail to reinitialize the ringbuffers, the resume continues and the
device is restored - albeit in a non-functional state. As we cannot
execute any
On g4x, we have an issue where the register write to setup the rings do
not always take. However, it appears that the current check also passes
only by chance, a second reading of the register returns a different
broekn value - but the GPU appears to function. Based on that
observation, lets try
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index
Some MIPI panels might not have resolution which is a multiple of 64 like
1366x768. Enable this feature for such panels by default
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 7 ++-
1 file changed,
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index
Hi,
The changes in DSI sequence are as suggested by HW and SV teams. Notable
difference apart form few WAs is that for MIPI it is suggetsed that the
PORT is enabled before PIPE and PLANE. The patch makes these changes.
So few sequence changes, few workarounds and few new feature support like
In preparation for Generic driver
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 11 +--
drivers/gpu/drm/i915/intel_dsi.h | 4 +++-
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git
As per the hw team's recommendation we need to enable the MIPI port
before enabling the plane and pipe. So call MIPI port enable in
pre_enable phase itself
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c |
Otherwise, this can stall pipe. We also need DPLL REFA always
enabled
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff
Though HS mode also should work.
v2: Change parameter as bool hs as suggested by Jani
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Reviewed-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c | 5 +++--
drivers/gpu/drm/i915/intel_dsi_cmd.c | 4 ++--
From: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
From: Ville Syrjälä ville.syrj...@linux.intel.com
We will treat Cherryview like Valleyview for most parts. Add a macro
for cases when we need to tell the two apart.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1
From: Rafael Barbalho rafael.barba...@intel.com
Page table updates were getting stuck in the CPU cache on chv causing
spurious page faults and strange behaviour.
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
[vsyrjala: Add !HAS_LLC checks]
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä ville.syrj...@linux.intel.com
Cherryview (CHV) is the latest Intel(r) Atom(tm) Processor from Intel
containing Intel(r) HD Graphics.
The major GPU hardware features include:
- Gen8 Intel(r) HD Graphics graphics
- three display pipes
- three HDMI/DP/eDP display ports
- two
From: Ville Syrjälä ville.syrj...@linux.intel.com
Due to Pipe C DPINVGTT has more bits on CHV.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä ville.syrj...@linux.intel.com
Enable aliasing PPGTT for CHV, but keep full PPGTT still disabled until
it gets enabled for BDW.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 7 ---
1 file changed, 4 insertions(+), 3
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV clock gating isn't identical to VLV, so add a new function
for it. This is only a start, and further changes are needed as
the details become available.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
Ignore the cache bits in PPAT and just set the snoop bit where
appropriate. BDW WB is mapped to snooped access, while all other
modes are mapped to non-snooped access.
The hardware supposedly ignores everything except the snoop bit
in the PPAT
From: Daniel Vetter daniel.vet...@ffwll.ch
v2: Update to also fill in the new num_pipes field.
v3: Rebase on top of the pciid extraction.
v4: Switch from info-has*ring to info-ring mask. Also add VEBOX support whiel
at it.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com (v1)
From: Daniel Vetter daniel.vet...@ffwll.ch
CHV has the Gen8 master interrupt register, as well as Gen8
GT/PCU interrupt registers.
The display block is based on VLV, with the main difference
of adding pipe C.
FIXME: Lot of this is copy pasted from either VLV or BDW. We should
probably refactor
From: Ville Syrjälä ville.syrj...@linux.intel.com
v2: Rebase on top of Ben's GT interrupt shuffling.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV has pipe C and PSR which cause changes to DPFLIPSTAT.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä ville.syrj...@linux.intel.com
FIXME: We probably want to sprinkle _CHV suffixes over these.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git
From: Daniel Vetter daniel.vet...@ffwll.ch
Same as on other gen8 devices.
Cc: Ingo Molnar mi...@kernel.org
Cc: H. Peter Anvin h...@zytor.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
arch/x86/kernel/early-quirks.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Ville Syrjälä ville.syrj...@linux.intel.com
Make i915_gem_interrupt debugfs file functional on CHV.
FIXME: Extract helpers for gt/display blocks to shrink the function a
bit and avoid duplication between bdw/chv (and other similar cases for
upstream).
Signed-off-by: Ville Syrjälä
From: Chon Ming Lee chon.ming@intel.com
CHV has 2 display phys. First phy (IOSF offset 0x1A) has two channels,
and second phy (IOSF offset 0x12) has single channel. The first phy is
used for port B and port C, while second phy is only for port D.
v2: Move the pipe to determine which phy to
From: Ville Syrjälä ville.syrj...@linux.intel.com
Fill in the sprite bits for DDL1/DDL2 registers, and add DDL3.
Still need to write the code to use these...
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 29 +
1
From: Chon Ming Lee chon.ming@intel.com
During cold boot, the display controller needs to deassert the common
lane reset. Only do it once during intel_init_dpio for both PHYx2 and
PHYx1.
Besides, assert the common lane reset when disable pll. This still
to be determined whether need to do
From: Chon Ming Lee chon.ming@intel.com
Cherryview has 3 pipes. Some of the pll dpio offset calculation is
based on pipe number. Need to use vlv_pipe_to_channel to calculate the
correct phy channel to use for the pipe.
Signed-off-by: Chon Ming Lee chon.ming@intel.com
---
From: Chon Ming Lee chon.ming@intel.com
Added programming phy layer for CHV based on Application note for 1273
CHV Display phy.
v2: Rebase the code and do some cleanup.
v3: Rework based on Ville review.
-Fix the macro where the ch info need to swap, and add parens to ?
operator.
From: Chon Ming Lee chon.ming@intel.com
Based on the chv clock limit, find the best divisor.
The divisor data has been verified with this spreadsheet.
P1273_DPLL_Programming Spreadsheet.
v2: Rebase the code and change the chv_find_best_dpll based on new
standard way to use
From: Chon Ming Lee chon.ming@intel.com
The additional DPLL registers added to support Port D. Besides, add
some new PHY control and status registers based on B-spec.
v2: Based on Ville review
- Corrected DPIO_PHY_STATUS offset and name.
- Rebase based on upstream change after
From: Deepak S deepa...@intel.com
v2: Mass rename of the dev_priv-rps variables in upstream.
Signed-off-by: Deepak S deepa...@intel.com (v1)
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_pm.c | 43 +
1 file changed, 43
From: Ville Syrjälä ville.syrj...@linux.intel.com
No CRT output on CHV, so don't call intel_crt_init().
v2: Don't disable CRT on HAS.
FIXME: Split out the is_simulator check again, we need it for now to keep HAS
going.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com (v1)
From: Deepak S deepa...@intel.com
Support to individually control Media/Render well based on the register access.
Add CHV specific write function to habdle difference between registers
that are sadowed vs those that need forcewake even for writes.
v2: Drop write FIFO for CHV and add comman well
From: Chon Ming Lee chon.ming@intel.com
Added programming PLL for CHV based on Application note for 1273 CHV
Display phy.
v2: -Break the common lane reset into another patch.
-Break the clock calculation into another patch.
-The changes are based on Ville review.
-Rework based
From: Deepak S deepa...@intel.com
v2: Remove vfuncs and add if else block to differentiate platform
(Daniel)
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 49 +++--
1 file changed, 47 insertions(+), 2 deletions(-)
diff
From: Deepak S deepa...@intel.com
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2aa65ce..fb533a3 100644
From: Deepak S deepa...@intel.com
v2: Configure PCBR if BIOS fails allocate pcbr (deepak)
Signed-off-by: Deepak S deepa...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 101 ++--
1 file changed, 98 insertions(+), 3 deletions(-)
diff --git
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add chv_crtc_clock_get() to read out the DPLL settings.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 34 +-
1 file changed, 33 insertions(+), 1 deletion(-)
From: Chon Ming Lee chon.ming@intel.com
With additional of pipe C, current 1 bit registers for pipe select
for HDMI and DP are no longer able to gather for 3 pipes. As a result,
new bits location in the same registers are added.
For HDMI, VLV uses bit 30, CHV uses bit 24-25.
For DP, VLV
From: Damien Lespiau damien.lesp...@intel.com
CHV uses the same bits as SNB/VLV to code the Graphics Mode Select field
(GFX stolen memory size) with the addition of finer granularity modes:
4MB increments from 0x11 (8MB) to 0x1d.
Values strictly above 0x1d are either reserved or not supported.
From: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
From: Deepak S deepa...@intel.com
v2: Added chv support for opcode to freq conversion and viceversa (Deepak)
Signed-off-by: Deepak S deepa...@intel.com
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
From: Deepak S deepa...@intel.com
v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)
v3: Mass rename of the dev_priv-rps variables in upstream.
Signed-off-by: Deepak S deepa...@intel.com (v1)
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_drv.h
From: Ville Syrjälä ville.syrj...@linux.intel.com
We implement the following workarounds:
* WaDisableAsyncFlipPerfMode:chv
* WaDisableSemaphoreAndSyncFlipWait:chv (at least partially)
* WaProgramMiArbOnOffAroundMiSetContext:chv
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
BDW has the same requirement but the w/a database doens't list
this w/a for BDW. Seems to be another one of those stick a bunch
of known workarounds into this bag and write something on the label
type of things.
Reviewed-by: Mika Kuoppala
From: Ville Syrjälä ville.syrj...@linux.intel.com
Skip __gen6_gt_wait_for_thread_c0() on CHV.
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 4 ++--
1 file changed, 2 insertions(+), 2
From: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index
From: Ville Syrjälä ville.syrj...@linux.intel.com
On CHV pipe C can driver only port D, and pipes A and B can drivbe only
ports B and C. Configure the crtc_mask appropriately to reflect that.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_dp.c | 8
From: Rafael Barbalho rafael.barba...@intel.com
Cherryview also needs this WA.
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
[vsyrjala: Looks like it's for pre-prodution hw only]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 4
From: Ville Syrjälä ville.syrj...@linux.intel.com
On CHV the GMBUS port for port D is different from other gmch platforms
which have port D. Fix it up.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 5
From: Rafael Barbalho rafael.barba...@intel.com
Add support for the third pipe in cherrview
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
[vsyrjala: slightly massaged the patch]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 7
From: Ville Syrjälä ville.syrj...@linux.intel.com
Streamline the CHV forcewake functions just like was done for VLV.
This will also fix a bug in accessing the common well registers,
where we'd end up trying to wake up the wells too many times
since we'd call force_wake_get/put twice per register
From: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
From: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 91 -
1 file changed, 17 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV uses the gen8 shadow register mechanism so we shouldn't be
checking the GT FIFO status.
This effectively removes the posting read, so add an explicit
posting read using FORCEWAKE_ACK_VLV (which is what use in
vlv_forcewake_reset()).
From: Deepak S deepa...@intel.com
This was fumbled in chv specific forcewake count during mmio reg read/write.
Issue introduced in
commit 95cf8b69f647322048929baffa8c7865aa6df2ad
Author: Deepak S deepa...@intel.com
Date: Mon Dec 16 12:16:54 2013 +0530
Subject: drm/i915/chv: Added CHV specific
From: Ville Syrjälä ville.syrj...@linux.intel.com
The following workarounds should be needed for pre-production hardware
only:
* WaDisablePwrmtrEvent:chv
* WaSetMaskForGfxBusyness:chv
* WaDisableGunitClockGating:chv
* WaDisableFfDopClockGating:chv
* WaDisableDopClockGating:chv
Signed-off-by:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
From: Rafael Barbalho rafael.barba...@intel.com
The i9xx_update_plane function was rejecting plane C when it is now a
valid plane.
Signed-off-by: Rafael Barbalho rafael.barba...@intel.com
[vsyrjala: Use PLANE_C instead of the number 2]
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
From: Ville Syrjälä ville.syrj...@linux.intel.com
Unsurprisingly the cursor C regiters are also at a weird offset on CHV.
Add more pipe offsets to handle them.
This also gets rid of most of the differences between the i9xx vs. ivb
cursor code. We can unify the remaining code as well, but I'll
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV has three pipes so let's expose them all.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
From: Ville Syrjälä ville.syrj...@linux.intel.com
This workaround is listed for CHV, but not for BDW. However BSpec notes
that on BDW CSunit clock gating is always disabled irrespective of the
relevant bit in the GEN6_UGCTL1 registers. For CHV however, such text
is not present in BSpec, so it
From: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
From: Ville Syrjälä ville.syrj...@linux.intel.com
We need to pick the correct data lanes based on the port not the
pipe, so move the data lane deassert into the encoder .pre_enable()
hook from the chv_enable_pll().
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
Seems like we shouldn't leave the data lane resert deasserted when
the port if disabled. So propagate the reset the data lanes in
the encoder .post_disable() hook.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
The bits we've been setting so far only progagate the reset singal to
the data lanes. To actaully force the reset signal we need to set another
override bit.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
Setup the pipe config dpll state correctly for CHV. Also add
a assert_pipe_disabled() to chv_disable_pll(), and program the
DPLL_MD registers in chv_enable_pll().
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
The spec only tells us to set individual bits here and there. So we use
RMW for most things. Do the same for the swing calc init.
Eventually we should optimize things to just blast the final value in
with group access whenever possible. But to do
From: Ville Syrjälä ville.syrj...@linux.intel.com
Like PCS, TX group reads return 0x. So we need to target each
lane separately if we want to use RMW cycles to update the registers.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 11
From: Ville Syrjälä ville.syrj...@linux.intel.com
Fix the encoder .get_config hooks to report the correct active pipe for
CHV.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 2 ++
From: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 9 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
From: Ville Syrjälä ville.syrj...@linux.intel.com
During the enable sequence we first enable the dclkp output to the
display controller, and then enable the PLL. Do the opposite during
the disable sequence.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
All PCS groups access reads return 0x, so we can't use group
access for RMW cycles. Instead target each spline separately.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 14
From: Ville Syrjälä ville.syrj...@linux.intel.com
These should make it possible to feed port C from pipe A or port B from
pipe B. Didn't quite seem to work though.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 7 ++
From: Ville Syrjälä ville.syrj...@linux.intel.com
Try to force the PHY clock buffer enables to make the clock routing
work.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 18 ++
drivers/gpu/drm/i915/intel_dp.c | 19
From: Ville Syrjälä ville.syrj...@linux.intel.com
These are just single registers so wasting space for the pipe offsets
seems a bit pointless. So just use the _PIPE3() macro instead.
Also rewrite the _PIPE3() macro to be more obvious, and protect the
arguments properly.
Signed-off-by: Ville
From: Ville Syrjälä ville.syrj...@linux.intel.com
Now that we forced the clock buffers on in .pre_pll_enable() we
should probably undo the damage after we've turned the PLL off. So
add new .post_pll_disable() hooks where we do that.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
The DIP registers are a mess on VLV and CHV. The register block on pipe
A is different than the register block on pipes B and C. In order to
handle that using the pipe offsets, we'd need a new pipe offset per
register, which seems wasteful. So
Some machines use an external EC for controlling the backlight. Info
about this is present in the VBT. Do not setup native backlight control
if no PWM backlight is available or supported according to VBT. The
acpi_backlight interface appears to work for the EC control.
In most cases there has
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