On Wed, 10 Dec 2014, Daniel Vetter daniel.vet...@ffwll.ch wrote:
Faster feedback to errors is always better. This is inspired by the
addition to WARN_ONs to mask/enable helpers for registers to make sure
callers have the arguments ordered correctly: Pretty much always the
arguments are static.
There exists a current workaround to prevent a hang on context switch
should the ring go to sleep in the middle of the restore,
WaProgramMiArbOnOffAroundMiSetContext (applicable to all gen7+). In
spite of disabling arbitration (which prevents the ring from powering
down during the critical
In the gen7 pipe control there is an extra bit to flush the media
caches, so let's set it during cache invalidation flushes.
Cc: Simon Farnsworth si...@farnz.org.uk
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
In order to act as a full command barrier by itself, we need to tell the
pipecontrol to actually stall the command streamer while the flush runs.
We require the full command barrier before operations like
MI_SET_CONTEXT, which currently rely on a prior invalidate flush.
References:
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
From: Deepak S deepa...@linux.intel.com
With cherryview onwards, Gunit hardware itself save and restore all the
Gunit registers. Skipping the vlv_save_gunit_s0ix_state
vlv_restore_gunit_s0ix_state for cherryview in S3/S0ix sequence.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
From: Deepak S deepa...@linux.intel.com
Use new Sideband offset to read max/min/gaur freq based on the SKU it
is running on. Based on the Number of EU, we read different bits to
identify the max frequencies at which system can run.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
From: Deepak S deepa...@linux.intel.com
Starting with Cherryview, devices may have a varying number of EU for
a given ID due to creative fusing. Punit support different frequency for
different fuse data. We use this patch to help get total eu enabled and
read the right offset to get RP0
Based
From: Deepak S deepa...@linux.intel.com
Higher RC6 residency is observed using timeout mode
instead of EI mode. It's Recommended to use TO Method for RC6.
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 5
On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:
From: Chris Wilson ch...@chris-wilson.co.uk
Calling intel_runtime_pm_put() is illegal from a soft-irq context, so
revert the crude hack
commit aa0b3b5bb8768c1a6a6788869d9c7015eae7e80c
Author: Paulo Zanoni paulo.r.zan...@intel.com
Date:
On Fri, Dec 12, 2014 at 03:30:14PM +0530, Deepak S wrote:
On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:
From: Chris Wilson ch...@chris-wilson.co.uk
Calling intel_runtime_pm_put() is illegal from a soft-irq context, so
revert the crude hack
commit
On 12/10/2014 5:27 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Things like reliable GGTT mappings and mirrored 2d-on-3d display will need
to map objects into the same address space multiple times.
Added a GGTT view concept and linked it with the VMA to distinguish
On 12/10/2014 5:27 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
A short section describing background, implementation and intended usage.
v2:
* Align section name between template and DOC comment. (Michel Thierry)
For: VIZ-4544
Signed-off-by: Tvrtko Ursulin
Execlist support in the i915 driver is now considered good enough for the
feature to be enabled by default on Gen8 and later and routinely tested.
Adjusted i915 parameters structure initialization to reflect this and updated
the comment in intel_sanitize_enable_execlists().
Issue: VIZ-2020
On Thursday 11 December 2014 03:45 PM, Chris Wilson wrote:
On Fri, Dec 12, 2014 at 03:30:14PM +0530, Deepak S wrote:
On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:
From: Chris Wilson ch...@chris-wilson.co.uk
Calling intel_runtime_pm_put() is illegal from a soft-irq context, so
On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:
From: Chris Wilson ch...@chris-wilson.co.uk
On user forcewake access, assert that runtime pm reference is held.
Fix and cleanup the callsites accordingly.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Mika
On Fri, Dec 12, 2014 at 05:09:26PM +0530, Deepak S wrote:
@@ -564,17 +542,20 @@ void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv, int fw_engine)
intel_runtime_pm_get(dev_priv);
I think we need to remove intel_runtime_pm_get here?
I see runtime_put is removed from
On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:
From: Chris Wilson ch...@chris-wilson.co.uk
With gen 6 we don't need to take uncore lock as we
don't have anything to protect from concurrent access.
v2: rebase and account for gen9 changes
Signed-off-by: Chris Wilson
On Thu, 11 Dec 2014, Thomas Daniel thomas.dan...@intel.com wrote:
Execlist support in the i915 driver is now considered good enough for the
feature to be enabled by default on Gen8 and later and routinely tested.
Adjusted i915 parameters structure initialization to reflect this and updated
the
On Thursday 11 December 2014 05:23 PM, Chris Wilson wrote:
On Fri, Dec 12, 2014 at 05:09:26PM +0530, Deepak S wrote:
@@ -564,17 +542,20 @@ void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv, int fw_engine)
intel_runtime_pm_get(dev_priv);
I think we need to remove
On Fri, Dec 12, 2014 at 02:18:16PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
With cherryview onwards, Gunit hardware itself save and restore all the
Gunit registers. Skipping the vlv_save_gunit_s0ix_state
vlv_restore_gunit_s0ix_state for cherryview in
When execlists submission is enabled, try full ppgtt by default.
Note, this patch considers that execlist support has been enabled by
default on Gen8.
Signed-off-by: Michel Thierry michel.thie...@intel.com
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++---
1 file changed, 6 insertions(+), 3
On Fri, 12 Dec 2014, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Starting with Cherryview, devices may have a varying number of EU for
a given ID due to creative fusing. Punit support different frequency for
different fuse data. We use this patch to help get total
On Thursday 11 December 2014 05:39 PM, Jani Nikula wrote:
On Fri, 12 Dec 2014, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Starting with Cherryview, devices may have a varying number of EU for
a given ID due to creative fusing. Punit support different frequency for
On Thu, Dec 11, 2014 at 08:16:59AM +, Chris Wilson wrote:
In the gen7 pipe control there is an extra bit to flush the media
caches, so let's set it during cache invalidation flushes.
Bspec is telling me this bit is already present in snb, and calls it
'Generic Media State Clear'. Older
From: Sonika Jindal sonika.jin...@intel.com
We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c |3 +--
1 file changed, 1 insertion(+), 2
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
From: Deepak S deepa...@linux.intel.com
Starting with Cherryview, devices may have a varying number of EU for
a given ID due to creative fusing. Punit support different frequency for
different fuse data. We use this patch to help get total eu enabled and
read the right offset to get RP0
Based
I'm resending this series, now without the RFC status. Code is
unchanged from the RFC.
Ander Conselvan de Oliveira (8):
drm/i915: Rename struct intel_crtc_config to intel_crtc_state
drm/i915: Embedded struct drm_crtc_state in intel_crtc_state
drm/i915: Pass new_config down do
So that we can get rid of the new_config pointer later.
Signed-off-by: Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 30 ++
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git
There are no more users of that pointer since the new config is now
passed down the call chain during mode set. Also, when the switch to
atomic happens, the right config (state) should be derived from an
atomic state structure.
Signed-off-by: Ander Conselvan de Oliveira
The objective is to make this structure usable with the atomic helpers,
so let's start with the rename. Patch generated with coccinelle:
@@ @@
-struct intel_crtc_config
+struct intel_crtc_state
Signed-off-by: Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com
---
In function that define a local pipe_config variable to point to
crtc-config, replace remaining references to crtc-config with
the local variable. This makes the code more consistent and easier
to change in an automated manner.
Signed-off-by: Ander Conselvan de Oliveira
This reduces the number of direct users of crtc-new_config. At some
point we'll be able to get rid of that pointer altogether, in favor
of drm core state structs.
Signed-off-by: Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 3 +-
And get rid of the duplicate mode structures. The bulk of the patch
was generated with the following semantic patch.
@@ struct intel_crtc_state *state; @@
-state-adjusted_mode
+state-base.adjusted_mode
@@ struct intel_crtc_state *state; @@
-state-requested_mode
+state-base.mode
@@ struct
To match the semantics of drm_crtc-state, which this will eventually
become.
@@ struct intel_crtc *crtc; @@
-crtc-config
+crtc-config
@@ struct intel_crtc *crtc; identifier member; @@
-crtc-config.member
+crtc-config-member
@@ struct drm_crtc *crtc; @@
-to_intel_crtc(crtc)-config
So that atomic operations will reference the right crtc state.
Signed-off-by: Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
Execlist support in the i915 driver is now considered good enough for the
feature to be enabled by default on Gen8 and later and routinely tested.
Adjusted i915 parameters structure initialization to reflect this and updated
the comment in intel_sanitize_enable_execlists().
v2: Update the
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:
From: Chris Wilson ch...@chris-wilson.co.uk
Introduce a structure to track the individual forcewake domains and use
that to eliminate duplicate logic.
v2: - Rebase on latest dinq (Mika)
- for_each_fw_domain macro (Mika)
-
Currently out of tree build fails because the version.h.tmp is generated
into the source directory instead of the build directory where it is
later looked for. This commit fixes it.
From 2c0617e21101d69e7219c6660936c0015f93f8ee Mon Sep 17 00:00:00 2001
From: Joonas Lahtinen
Currently out of tree build fails because the version.h.tmp is generated
into the source directory instead of the build directory where it is
later looked for. This commit fixes it.
From 2c0617e21101d69e7219c6660936c0015f93f8ee Mon Sep 17 00:00:00 2001
From: Joonas Lahtinen
On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:
As we now have forcewake domains, take advantage of it
by putting the differences in gen fw handling in data rather
than in code.
In past we have opencoded this quite extensively as the fw handling
is in the fast path. There has also
On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:
These two were using a fw dance logic where posting read was done
after both domain bit were set. When in other gens, the posting
read is done immediately after setting the forcewake bit for each
domain.
Now bring these in line with
On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:
We have multiple forcewake domains now on recent gens. Change the
function naming to reflect this.
v2: More verbose names (Chris)
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 8
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_opregion.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
b/drivers/gpu/drm/i915/intel_opregion.c
index d8de1d5140a7..bce9bbe05549 100644
---
Hi all, here's a few updates to opregion. Patches 1-4 should be pretty
trivial and not do anything drastic. Patch 5 starts using the extended
DIDL, but I doubt it will make a huge difference anyway. It might prove
to be useful prep stuff for adding more sense to our CADL handling.
BR,
Jani.
Inluding extended didl and cpdl fields
Present since opregion version 3.0.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_opregion.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
Adding support for did2, or the extended support display devices ID
list, increases the total to 15.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_opregion.c | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git
On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:
Forcewake domain code uses unsigned int as a type for 'domains mask'.
Bring the hw accessors inline with this.
Suggested-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
Conform to same style as the rest of the driver.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_opregion.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_opregion.c
Make it easier to handle the extended didl. No functional changes.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_opregion.c | 50 +++
1 file changed, 39 insertions(+), 11 deletions(-)
diff --git
On Tuesday 09 December 2014 05:16 PM, Mika Kuoppala wrote:
Make the domains and domain identifiers enums. To emphasize
the difference in order to avoid mistakes.
Suggested-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
-Original Message-
From: Nguyen, Michael H
Sent: Monday, December 08, 2014 10:34 PM
To: intel-gfx@lists.freedesktop.org
Cc: Bloomfield, Jon; Brad Volkin
Subject: [PATCH v6 4/5] drm/i915: Mark shadow batch buffers as purgeable
From: Brad Volkin bradley.d.vol...@intel.com
By
On Wed, 10 Dec 2014, Jesse Barnes jbar...@virtuousgeek.org wrote:
On Wed, 10 Dec 2014 22:35:37 +0200
Ville Syrjälä ville.syrj...@linux.intel.com wrote:
On Wed, Dec 10, 2014 at 12:16:05PM -0800, Jesse Barnes wrote:
Should probably just init this in the GMbus code all the time,
based on the
Hi Dave -
Here's a batch of i915 fixes for 3.19.
BR,
Jani.
The following changes since commit 00f0b3781028605910cb4662a0f8a4849b445fc2:
drm/i915: Reject modeset when the same digital port is used more than once
(2014-12-03 09:31:53 +0100)
are available in the git repository at:
-Original Message-
From: Nguyen, Michael H
Sent: Monday, December 08, 2014 10:34 PM
To: intel-gfx@lists.freedesktop.org
Cc: Bloomfield, Jon; Brad Volkin
Subject: [PATCH v6 5/5] drm/i915: Tidy up execbuffer command parsing code
From: Brad Volkin bradley.d.vol...@intel.com
Move
On Wed, 10 Dec 2014, Ville Syrjälä ville.syrj...@linux.intel.com wrote:
On Thu, Nov 20, 2014 at 04:05:55PM +0200, Imre Deak wrote:
irq_mask should include all IRQ bits that we want to mask, but atm we
set it incorrectly to the inverse of this. If the mask is used
subsequently to enable/disable
This e-mail can be disregarded. It contains no secrets no nothing,
simply sent from wrong address.
On to, 2014-12-11 at 13:11 +, Lahtinen, Joonas wrote:
Currently out of tree build fails because the version.h.tmp is generated
into the source directory instead of the build directory where it
drm_plane_helper_check_update() currently uses crtc before testing whether
we're disabling the plane (fb == NULL). Move the fb test before the first crtc
usage so that crtc == NULL doesn't have to be handled by the caller.
Signed-off-by: Matt Roper matthew.d.ro...@intel.com
---
On 11 Dec 2014 00:40:28 -0800
shuang...@intel.com wrote:
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series
On 12/11/2014 12:28 PM, sonika.jin...@intel.com wrote:
From: Sonika Jindal sonika.jin...@intel.com
We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Eliminate six needless spin lock/unlock pairs when writing ELSP.
RFC for now with some #define copy and paste.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Cc: Dave Gordon david.s.gor...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 16
On Thu, Dec 11, 2014 at 07:20:57AM -0800, Matt Roper wrote:
drm_plane_helper_check_update() currently uses crtc before testing whether
we're disabling the plane (fb == NULL). Move the fb test before the first
crtc
usage so that crtc == NULL doesn't have to be handled by the caller.
Hi,
I'll try to do the detailed review of your series in the following few
days. I might ask some questions on the design also to help me
understand the bigger picture.
First thing, I see that patches are checkpatch.pl clean, apart when run
in strict mode. I think Daniel prefers --strict
On 11/13/2014 12:02 PM, Yu Zhang wrote:
Introduce a PV INFO structure, to facilitate the Intel GVT-g
technology, which is a GPU virtualization solution with mediated
pass-through. This page contains the shared information between
i915 driver and the host emulator. For now, this structure
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
On 12/11/2014 05:26 AM, Bloomfield, Jon wrote:
-Original Message-
From: Nguyen, Michael H
Sent: Monday, December 08, 2014 10:34 PM
To: intel-gfx@lists.freedesktop.org
Cc: Bloomfield, Jon; Brad Volkin
Subject: [PATCH v6 4/5] drm/i915: Mark shadow batch buffers as purgeable
From: Brad
On 12/11/2014 05:49 AM, Bloomfield, Jon wrote:
-Original Message-
From: Nguyen, Michael H
Sent: Monday, December 08, 2014 10:34 PM
To: intel-gfx@lists.freedesktop.org
Cc: Bloomfield, Jon; Brad Volkin
Subject: [PATCH v6 5/5] drm/i915: Tidy up execbuffer command parsing code
From:
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
From: Brad Volkin bradley.d.vol...@intel.com
By adding a new exec_entry flag, we cleanly mark the shadow objects
as purgeable after they are on the active list.
v2:
- Move 'shadow_batch_obj-madv = I915_MADV_WILLNEED' inside _get
fnc (danvet, from v4 6/7 feedback)
v3:
- Remove duplicate 'madv
From: Brad Volkin bradley.d.vol...@intel.com
Previously we couldn't trust the user-supplied batch length because
it came directly from userspace (i.e. untrusted code). It would have
affected what commands software parsed without regard to what hardware
would actually execute, leaving a potential
From: Brad Volkin bradley.d.vol...@intel.com
This adds a small module for managing a pool of batch buffers.
The only current use case is for the command parser, as described
in the kerneldoc in the patch. The code is simple, but separating
it out makes it easier to change the underlying
From: Brad Volkin bradley.d.vol...@intel.com
Move it to a separate function since the main do_execbuffer function
already has so much going on.
v2:
- Move pin/unpin calls inside i915_parse_cmds() (Chris W, v4 7/7
feedback)
Issue: VIZ-4719
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
From: Michael H. Nguyen michael.h.ngu...@intel.com
This is v7 in response to
http://lists.freedesktop.org/archives/intel-gfx/2014-December/057033.html
Minor updates from the last rev
- Keep batch pool in LRU order (Daniel)
- Remove duplicate madv assignments (Daniel)
Brad Volkin (5):
From: Brad Volkin bradley.d.vol...@intel.com
This patch sets up all of the tracking and copying necessary to
use batch pools with the command parser and dispatches the copied
(shadow) batch to the hardware.
After this patch, the parser is in 'enabling' mode.
Note that performance takes a hit
This will allow us to read the number of dispatched compute threads
for GL_ARB_pipeline_statistics_query.
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Cc: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +++-
drivers/gpu/drm/i915/i915_reg.h| 23
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 364/364
On Thu, Dec 11, 2014 at 01:28:09PM -0800, Jordan Justen wrote:
This will allow us to read the number of dispatched compute threads
for GL_ARB_pipeline_statistics_query.
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
Cc: Ben Widawsky b...@bwidawsk.net
Reviewed-by: Ben Widawsky
Once we integrate our work into the atomic pipeline, plane commit
operations will need to happen with interrupts disabled, due to vblank
evasion. Our commit functions today include sleepable work, so those
operations need to be split out and run either before or after the
atomic register
Add the new driver entrypoints that will be called by the atomic plane
helpers.
This patch does not actually switch over to the new plane helpers yet,
so there should be no functional change here. Also note that although
plane programming was already split into check/prepare/commit steps,
some
From: Deepak S deepa...@linux.intel.com
Higher RC6 residency is observed using timeout mode
instead of EI mode. It's Recommended to use TO Method for RC6.
v2: Add comment about timeout threshold. (Tom)
Signed-off-by: Deepak S deepa...@linux.intel.com
Signed-off-by: Rodrigo Vivi
Summary
We covered the platform: Braswell, Broadwell, Baytrail, Haswell, Ivybridge,
Ironlake
In this circle, 3 new bugs are filed:
87253https://bugs.freedesktop.org/show_bug.cgi?id=87253
[BSW drm-intel-fixes]Display is blank after system boots
On 12/10/2014 7:38 PM, Gaurav K Singh wrote:
For CHT changes are required for calculating the correct m,n p with
minimal error +/- for the required DSI clock, so that the correct dividor
ctrl values are written in cck regs for DSI. This patch has been tested
on CHT RVP with 1200 x 1920 panel.
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