For the atomic conversion, the mode set paths need to be changed to rely
on an atomic state instead of using the staged config. By using an
atomic state for the legacy code, we will be able to convert the code
base in small chunks.
v2: Squash patch that adds stat argument to intel_set_mode(). (And
On ti, 2015-03-17 at 07:31 +0200, Joonas Lahtinen wrote:
> On ma, 2015-03-16 at 18:50 +0100, Daniel Vetter wrote:
> > On Mon, Mar 16, 2015 at 02:11:13PM +0200, Joonas Lahtinen wrote:
> > [snip]
> > > int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level
> > > cache_level,
> > >
On ma, 2015-03-16 at 18:50 +0100, Daniel Vetter wrote:
> On Mon, Mar 16, 2015 at 02:11:13PM +0200, Joonas Lahtinen wrote:
> [snip]
> > int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
> > u32 flags);
> > @@ -2800,60 +2796,48 @@ struct dma_buf *i915_gem_prim
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Jesse Barnes
> Sent: Tuesday, March 17, 2015 4:10 AM
> To: Daniel Vetter; Song, Ruiling
> Cc: Vetter, Daniel; intel-gfx@lists.freedesktop.org; Yang, Rong R;
> beig...@lists.freedesktop.org
On Mon, Mar 16, 2015 at 01:10:28PM -0700, Jesse Barnes wrote:
> On 03/16/2015 01:52 AM, Daniel Vetter wrote:
> > On Mon, Mar 16, 2015 at 02:29:24AM +, Song, Ruiling wrote:
> >>
> >>
> >>> -Original Message-
> >>> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5966
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 275/275
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5962
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 275/275
This is an extention of igt_debug_wait_for_keypress that also can have
customized message and return key pressed.
v2: This is actualy a v2. V1 was an extension of original
igt_debug_wait_for_keypress but it was nacked.
v3: Make [Y/n] check inside aux function as suggested by Daniel.
Also
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5961
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 275/275
On Mon, Mar 16, 2015 at 05:58:12PM +0200, Mika Kuoppala wrote:
> Sometimes when first batch is run with blitter ring,
> @@ -931,7 +931,6 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
> intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
> intel_ring_emit(ring, get_pd_offset(ppgtt
On Mon, Mar 16, 2015 at 06:53:40PM +0100, Daniel Vetter wrote:
> On Mon, Mar 16, 2015 at 03:46:35PM +0200, Mika Kuoppala wrote:
> > From: Chris Wilson
> >
> > On Sandybridge+, the GPU provides the ERROR register for detecting page
> > faults. Hook this up to our hangcheck so that we can dump the
From: Mika Kuoppala
commit 939fd762083f988be271da8c96398178daf9baf0
Author: Mika Kuoppala
Date: Thu Jan 30 19:04:44 2014 +0200
drm/i915: Get rid of acthd based guilty batch search
Failed to cleanup properly as it made the head obsolete.
Signed-off-by: Mika Kuoppala
Signed-off-by: Rodri
This is another drm-intel-collector updated notice:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
Here goes the update list in order for better reviewers assignment:
Patch drm/i915: Remove pinned check from madvise_ioctl - Reviewer:
Patch drm/i915/vlv: check p
From: Chris Wilson
We don't need to incur the overhead of checking whether the object is
pinned prior to changing its madvise. If the object is pinned, the
madvise will not take effect until it is unpinned and so we cannot free
the pages being pointed at by hardware. Marking a pinned object with
From: Jesse Barnes
Same as IBX and G4x, they all share the same genetic material.
v2: we all need a bit more port in our lives
Signed-off-by: Jesse Barnes
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/
From: Imre Deak
Due this typo we don't save/restore the GFX_MAX_REQ_COUNT register across
suspend/resume, so fix this.
This was introduced in
commit ddeea5b0c36f3665446518c609be91f9336ef674
Author: Imre Deak
Date: Mon May 5 15:19:56 2014 +0300
drm/i915: vlv: add runtime PM support
I no
From: Mika Kuoppala
We just allocated the intel_ringbuffer with kzalloc. There
is no chance of the ringbuf->obj being other than NULL
so remove the redudant check.
Signed-off-by: Mika Kuoppala
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_lrc.c | 29 +
On Mon, 2015-03-16 at 09:59 +0100, Daniel Vetter wrote:
> On Fri, Mar 13, 2015 at 06:19:19PM -0400, Rodrigo Vivi wrote:
> > This will allow manual tests when crc isn't available.
> >
> > Signed-off-by: Rodrigo Vivi
> > ---
> > tests/kms_psr_sink_crc.c | 4 ++--
> > 1 file changed, 2 insertions(+
On 03/16/2015 01:52 AM, Daniel Vetter wrote:
> On Mon, Mar 16, 2015 at 02:29:24AM +, Song, Ruiling wrote:
>>
>>
>>> -Original Message-
>>> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
>>> Vetter
>>> Sent: Saturday, March 14, 2015 1:14 AM
>>> To: Chris Wilson;
On 03/16/2015 01:52 AM, Daniel Vetter wrote:
> On Mon, Mar 16, 2015 at 02:29:24AM +, Song, Ruiling wrote:
>>
>>
>>> -Original Message-
>>> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
>>> Vetter
>>> Sent: Saturday, March 14, 2015 1:14 AM
>>> To: Chris Wilson;
This patch was listed to -collector but got a hard conflict.
If it is still needed please consider to rebase and resend.
On Fri, Jan 23, 2015 at 7:46 AM, Mika Kuoppala
wrote:
> Add a tunable to set forcewake hysteresis timer for those
> who want explore the perf/power impacts.
>
> Signed-off-by:
On Mon, Mar 16, 2015 at 03:46:35PM +0200, Mika Kuoppala wrote:
> From: Chris Wilson
>
> On Sandybridge+, the GPU provides the ERROR register for detecting page
> faults. Hook this up to our hangcheck so that we can dump the error
> state soon after such an event occurs. This would be better insid
On Mon, Mar 16, 2015 at 02:11:13PM +0200, Joonas Lahtinen wrote:
> GGTT views are only applicable when dealing with GGTT. Change the code to
> reject ggtt_view where it should not be used and require it when it should
> be.
>
> v2:
> - Dropped _ppgtt_ infixes, allow both types to be passed
> - Dis
On Haswell and Broadwell with link in standby when exit event happens
between vblank and VSC packet, PSR exit on panel but DPA transmitter
still sends black pixel. When this condition hits, panel will intermittently
display black frame.
The known W/A for this case involve the of single_frame updat
On Haswell and Broadwell with link in standby when exit event happens
between vblank and VSC packet, PSR exit on panel but DPA transmitter
still sends black pixel. When this condition hits, panel will intermittently
display black frame.
The known W/A for this case involve the of single_frame updat
Since the begining there is a missunderstanding on the meaning of this
dpcd bit.
This bit shouldn't indicate whether to use link standby or not, but just
be used to configure TP1, TP2 and TP3 times and tell hw aux should be skiped
since HW is the responsible one.
Even with help of frontbuffer trac
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5958
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -2 275/275
On Mon, 16 Mar 2015 17:43:33 +0100
Daniel Vetter wrote:
> Is linux-next also affected or is this just a case of i915 maintainers
> having failed to push the right patch to -fixes?
I just confirmed, linux-next boots without the warning.
>
> I'll try to figure out what fell apart here meanwhile
On Mon, Mar 16, 2015 at 11:45:03AM -0400, Steven Rostedt wrote:
>
> Any movement on this? I still get this warning on 4.0-rc4.
Sorry for not looking into this, I've thought we've addressed this already
and the fix is simply still in-flight to 4.0-rc. Seems it's not :(
Is linux-next also affected
Splitting this prep work should ease the code review and help identify
problems (and also shrink the Gen8 patch series, which is of more interest).
4 patches have already been sent as part of the main patchset, only "page
table generalizations" is brand new (suggested by Mika) and should help to
c
From: Ben Widawsky
This patch was formerly known as, "Force pd restore when PDEs change,
gen6-7." I had to change the name because it is needed for GEN8 too.
The real issue this is trying to solve is when a new object is mapped
into the current address space. The GPU does not snoop the new mappi
From: Ben Widawsky
Instead of implementing the full tracking + dynamic allocation, this
patch does a bit less than half of the work, by tracking and warning on
unexpected conditions. The tracking itself follows which PTEs within a
page table are currently being used for objects. The next patch wi
From: Ben Widawsky
In Gen8, PDPs are saved and restored with legacy contexts (legacy contexts
only exist on the render ring). So change the ordering of LRI vs MI_SET_CONTEXT
for the initialization of the context. Also the only cases in which we
need to manually update the PDPs are when MI_RESTORE
From: Ben Widawsky
The problem is we're going to switch to a new context, which could be
the default context. The plan was to use restore inhibit, which would be
fine, except if we are using dynamic page tables (which we will). If we
use dynamic page tables and we don't load new page tables, the
No functional changes, but will improve code clarity and removed some
duplicated defines.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 160 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 28 ---
2 files changed, 96 insertions(+), 92 del
Sometimes when first batch is run with blitter ring,
and even tho its PP_BASE has been properly set, the ring
seems to be very confused about its memory view. The ring
ACHTD keeps progressing past batch boundary, towards the end
off address space. Eventually after quite amount of time,
hangcheck wi
Chris Wilson writes:
> On Mon, Mar 16, 2015 at 04:20:46PM +0200, Mika Kuoppala wrote:
>> Perhaps not in the golden state, but do we push any workarounds through
>> render ring init, that are global in scope and required by the other rings?
>
> No. Afaict the w/a only apply to render. Or else we h
Any movement on this? I still get this warning on 4.0-rc4.
-- Steve
On Thu, 5 Mar 2015 09:27:28 -0500
Steven Rostedt wrote:
> On Mon, Feb 23, 2015 at 11:12:39PM +0300, Andrey Skvortsov wrote:
> >
> > This warning is moved from linux-next to v4.0-rc1 now. After system boot is
> > just a blac
Currently, we only track the last request globally across all engines.
This prevents us from issuing concurrent read requests on e.g. the RCS
and BCS engines (or more likely the render and media engines). Without
semaphores, we incur costly stalls as we synchronise between rings -
greatly impacting
Signed-off-by: Chris Wilson
---
tests/.gitignore| 1 +
tests/Makefile.sources | 1 +
tests/gem_read_read_speed.c | 193
3 files changed, 195 insertions(+)
create mode 100644 tests/gem_read_read_speed.c
diff --git a/tests/.gitigno
On Mon, 16 Mar 2015, Xi Ruoyao wrote:
> On 03/16/2015 at 10:30 AM, Stephen Rothwell wrote:
>> Hi Dave,
>>
>> Today's linux-next merge of the drm tree got a conflict in
>> drivers/gpu/drm/i915/intel_display.c between commit 2dccc9898d45
>> ("drm/i915: Ensure plane->state->fb stays in sync with plan
On 03/16/2015 02:48 PM, Joonas Lahtinen wrote:
Hi,
Regression testing completed without problems for BYT, HSW and BDW
already.
On ma, 2015-03-16 at 13:26 +, Tvrtko Ursulin wrote:
Hi,
On 03/16/2015 12:11 PM, Joonas Lahtinen wrote:
GGTT views are only applicable when dealing with GGTT. Ch
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5957
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 275/275
Hi,
Regression testing completed without problems for BYT, HSW and BDW
already.
On ma, 2015-03-16 at 13:26 +, Tvrtko Ursulin wrote:
> Hi,
>
> On 03/16/2015 12:11 PM, Joonas Lahtinen wrote:
> > GGTT views are only applicable when dealing with GGTT. Change the code to
> > reject ggtt_view wher
On Mon, Mar 16, 2015 at 04:20:46PM +0200, Mika Kuoppala wrote:
> Perhaps not in the golden state, but do we push any workarounds through
> render ring init, that are global in scope and required by the other rings?
No. Afaict the w/a only apply to render. Or else we have been horribly
misinformed.
Since we are considering implementing read-read optimisations for mixed
engine workloads, make sure that we at least have a few tests that check
for coherency when doing so.
Signed-off-by: Chris Wilson
---
tests/gem_concurrent_blit.c | 65 -
1 file cha
The choice is to either move the igt_require from the buffer allocation
(and allow the allocation to fail) inside the igt_fixture, or move the
buffer allocation to the subtest. Moving it to the subtest has the
advantage of ensuring that every test has the same initial state (no
chance of leaking st
Chris Wilson writes:
> On Mon, Mar 16, 2015 at 03:46:34PM +0200, Mika Kuoppala wrote:
>> We are freeing the batch that is just pushed to ring.
>
> Kill this. It is not correct.
>
>> Further, other ring inits should assume that the render
>> context with the workarounds are pushed before their rin
On Mon, Mar 16, 2015 at 03:46:34PM +0200, Mika Kuoppala wrote:
> We are freeing the batch that is just pushed to ring.
Kill this. It is not correct.
> Further, other ring inits should assume that the render
> context with the workarounds are pushed before their rings
> execute anything.
>
> This
Hi,
Testing dynamic page tables series, there has
been also problems with our codebase interacting badly
with the patchset. These are the essentials I have needed
to testrun/debug the series on my gen7.
Chris Wilson (2):
drm/i915: Detect page faults during hangcheck
drm/i915: Reorder hw init
From: Chris Wilson
On Sandybridge+, the GPU provides the ERROR register for detecting page
faults. Hook this up to our hangcheck so that we can dump the error
state soon after such an event occurs. This would be better inside an
interrupt handler, but it serves a purpose here as it detects that o
From: Chris Wilson
Currently we initialise the rings, add the first context switch to the
ring and execute our golden state then enable (aliasing or full) ppgtt.
However, as we enable ppgtt using direct MMIO but load the PD using
MI_LRI, we end up executing the context switch and golden render st
We are freeing the batch that is just pushed to ring.
Further, other ring inits should assume that the render
context with the workarounds are pushed before their rings
execute anything.
This fixes (or papers over) a problem where with full ppgtt
the blitter ring init sometimes fails, where the bl
On 03/16/2015 at 10:30 AM, Stephen Rothwell wrote:
Hi Dave,
Today's linux-next merge of the drm tree got a conflict in
drivers/gpu/drm/i915/intel_display.c between commit 2dccc9898d45
("drm/i915: Ensure plane->state->fb stays in sync with plane->fb") from
the drm-intel-fixes tree and commit afd
Hi,
On 03/16/2015 12:11 PM, Joonas Lahtinen wrote:
GGTT views are only applicable when dealing with GGTT. Change the code to
reject ggtt_view where it should not be used and require it when it should
be.
v2:
- Dropped _ppgtt_ infixes, allow both types to be passed
- Disregard other but normal
So that the compiler warns if we get something wrong.
v2: Don't break 'if (foo) for_each_*' usage. (Jani & Chris)
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/i915_drv.h | 63 ++---
1 file changed, 40 insertions(+), 23 deletions(-)
dif
On to, 2015-03-12 at 12:21 +, Tvrtko Ursulin wrote:
> Hi,
>
> Much more likeable in general, some comments inline:
>
> On 03/12/2015 11:10 AM, Joonas Lahtinen wrote:
> > GGTT views are only applicable when dealing with GGTT. Change the code to
> > reject ggtt_view where it should not be used
GGTT views are only applicable when dealing with GGTT. Change the code to
reject ggtt_view where it should not be used and require it when it should
be.
v2:
- Dropped _ppgtt_ infixes, allow both types to be passed
- Disregard other but normal views when no view is specified
- More checks that vali
On Mon, Mar 16, 2015 at 05:03:28PM +0530, sonika wrote:
>
> On Monday 16 March 2015 04:25 PM, Ville Syrjälä wrote:
> > On Mon, Mar 16, 2015 at 03:07:05PM +0530, Jindal, Sonika wrote:
> >>
> >> On 3/16/2015 3:04 PM, Ville Syrjälä wrote:
> >>> On Mon, Mar 16, 2015 at 02:43:19PM +0530, Jindal, Sonika
On Monday 16 March 2015 04:25 PM, Ville Syrjälä wrote:
On Mon, Mar 16, 2015 at 03:07:05PM +0530, Jindal, Sonika wrote:
On 3/16/2015 3:04 PM, Ville Syrjälä wrote:
On Mon, Mar 16, 2015 at 02:43:19PM +0530, Jindal, Sonika wrote:
On 3/12/2015 8:40 PM, ville.syrj...@linux.intel.com wrote:
From:
On Mon, Mar 16, 2015 at 03:07:05PM +0530, Jindal, Sonika wrote:
>
>
> On 3/16/2015 3:04 PM, Ville Syrjälä wrote:
> > On Mon, Mar 16, 2015 at 02:43:19PM +0530, Jindal, Sonika wrote:
> >>
> >>
> >> On 3/12/2015 8:40 PM, ville.syrj...@linux.intel.com wrote:
> >>> From: Ville Syrjälä
> >>>
> >>> The
On Mon, Mar 16, 2015 at 12:00:35PM +0200, Jani Nikula wrote:
> On Mon, 16 Mar 2015, Ander Conselvan de Oliveira
> wrote:
> > So that the compiler warns if we get something wrong.
> >
> > Signed-off-by: Ander Conselvan de Oliveira
> >
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 39
> > ++
On Mon, 16 Mar 2015, Ander Conselvan de Oliveira
wrote:
> So that the compiler warns if we get something wrong.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 39 ++-
> 1 file changed, 26 insertions(+), 13 deletion
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5954
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV 268/268
On 3/16/2015 3:04 PM, Ville Syrjälä wrote:
On Mon, Mar 16, 2015 at 02:43:19PM +0530, Jindal, Sonika wrote:
On 3/12/2015 8:40 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
The source rates don't change, so we can just point the caller at the
const arrays.
Signed-off-by: Vil
On Mon, Mar 16, 2015 at 02:43:19PM +0530, Jindal, Sonika wrote:
>
>
> On 3/12/2015 8:40 PM, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > The source rates don't change, so we can just point the caller at the
> > const arrays.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
>
On 3/12/2015 8:40 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
The source rates don't change, so we can just point the caller at the
const arrays.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_dp.c | 24 ++--
1 file changed, 10 insertions
On Mon, Mar 16, 2015 at 09:15:22AM +1000, Dave Airlie wrote:
> On 16 March 2015 at 05:31, Chris Wilson wrote:
> > On Sun, Mar 15, 2015 at 08:22:36PM +0100, Krzysztof Kolasa wrote:
> >> Problem solved and tested:
> >>
> >> [PATCH] drm/mm: Fix support 4 GiB and larger ranges
> >>
> >> bad argument i
On Mon, Mar 16, 2015 at 10:04:28AM +0100, Daniel Vetter wrote:
> On Fri, Mar 13, 2015 at 06:19:24PM -0400, Rodrigo Vivi wrote:
> > This is useful when 1 person is running all tests and other one is reading
> > log willing
> > to know what tests passed and which failed. So tester is able to run all
On Fri, Mar 13, 2015 at 06:19:24PM -0400, Rodrigo Vivi wrote:
> This is useful when 1 person is running all tests and other one is reading
> log willing
> to know what tests passed and which failed. So tester is able to run all
> tests without
> stop and send log to developer.
>
> v2: Rebased af
On Fri, Mar 13, 2015 at 06:19:19PM -0400, Rodrigo Vivi wrote:
> This will allow manual tests when crc isn't available.
>
> Signed-off-by: Rodrigo Vivi
> ---
> tests/kms_psr_sink_crc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/tests/kms_psr_sink_crc.c b/tests/k
On Mon, Mar 16, 2015 at 02:29:24AM +, Song, Ruiling wrote:
>
>
> > -Original Message-
> > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> > Vetter
> > Sent: Saturday, March 14, 2015 1:14 AM
> > To: Chris Wilson; Daniel Vetter; Weinehall, David; Zou, Nanhai; S
So that the compiler warns if we get something wrong.
Signed-off-by: Ander Conselvan de Oliveira
---
drivers/gpu/drm/i915/i915_drv.h | 39 ++-
1 file changed, 26 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i9
On Fri, 2015-03-13 at 16:13 -0700, Rodrigo Vivi wrote:
> Regressed by this commit:
>
> commit 3455454e18ca3f92c565700539e744c620d8276b
> Author: Ander Conselvan de Oliveira
> Date: Tue Mar 3 15:21:56 2015 +0200
>
> drm/i915: Add a for_each_intel_connector macro
>
> Cc: Ander Conselvan de
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