On Thu, Apr 02, 2015 at 06:28:07PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
../drivers/gpu/drm/i915/intel_pm.c:3185:45: warning: Initializer entry
defined twice
../drivers/gpu/drm/i915/intel_pm.c:3185:52: also defined here
On Thu, Apr 02, 2015 at 02:50:09PM -0700, Jeff McGee wrote:
On Wed, Apr 01, 2015 at 08:20:44AM +0200, Daniel Vetter wrote:
On Tue, Mar 31, 2015 at 09:59:22AM -0700, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
BXT uses a subset of the SKL fuse registers, because
On 4/7/2015 1:46 PM, Daniel Vetter wrote:
On Mon, Apr 06, 2015 at 10:50:51AM +0530, Jindal, Sonika wrote:
On 4/2/2015 9:18 PM, Matt Roper wrote:
On Thu, Apr 02, 2015 at 10:08:27AM +0530, Jindal, Sonika wrote:
On 4/1/2015 11:51 PM, Matt Roper wrote:
On Mon, Mar 30, 2015 at 02:04:56PM
On Mon, Apr 06, 2015 at 10:50:51AM +0530, Jindal, Sonika wrote:
On 4/2/2015 9:18 PM, Matt Roper wrote:
On Thu, Apr 02, 2015 at 10:08:27AM +0530, Jindal, Sonika wrote:
On 4/1/2015 11:51 PM, Matt Roper wrote:
On Mon, Mar 30, 2015 at 02:04:56PM +0530, Sonika Jindal wrote:
Signed-off-by:
On Wed, Apr 01, 2015 at 06:41:32PM +0300, Ville Syrjälä wrote:
On Tue, Mar 31, 2015 at 04:03:21PM -0700, Rodrigo Vivi wrote:
Program the default initial value of the L3SqcReg1 on BDW for performance
v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
v3: Spec shows
On Thu, Apr 02, 2015 at 06:49:38PM +0530, Deepak S wrote:
On Monday 30 March 2015 09:13 PM, Daniel Vetter wrote:
On Mon, Mar 30, 2015 at 08:03:58PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Cleanup idr table if any error happens after
On Tue, Apr 07, 2015 at 12:33:40PM +0530, Sivakumar Thulasimani wrote:
sorry if i am missing something, HSW and BDW requires display audio
controller to be updated with new values once CD clock is modified. how
is this accomplished here ?
I'm hoping the audio driver will query the cdclk
On Wed, Apr 01, 2015 at 01:43:46PM +0200, Daniel Vetter wrote:
We stopped handling them in
commit aaecdf611a05cac26a94713bad25297e60225c29
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Tue Nov 4 15:52:22 2014 +0100
drm/i915: Stop gathering error states for CS error interrupts
On Thu, Apr 02, 2015 at 04:03:22PM -0700, Matt Roper wrote:
On Wed, Apr 01, 2015 at 07:59:35PM -0700, Chandra Konduru wrote:
This patch converts intel_plane_state-src rect from 16.16
values into regular ints.
This approach aligns with sprite_plane_state-src rects
which are already in
On Thu, Apr 02, 2015 at 04:04:14PM +0100, Chris Wilson wrote:
Once userptr becomes part of client API, it is almost a certainly that
eventually someone will try to create a new object from a mapping of
another client object, e.g.
new = vaImport(vaMap(old, size), size);
(using a
On Fri, Apr 03, 2015 at 10:43:29AM +0100, Chris Wilson wrote:
On Thu, Nov 20, 2014 at 09:26:30AM +0100, Daniel Vetter wrote:
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c
b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 749ab485569e..03c675a4476e 100644
---
On 4/7/2015 1:43 PM, Daniel Vetter wrote:
On Thu, Apr 02, 2015 at 08:59:33AM -0700, Matt Roper wrote:
On Thu, Apr 02, 2015 at 10:24:02AM +0530, Jindal, Sonika wrote:
I am not sure how it will help. drm_plane_check_pixel_format should
be used to check the pixel format of the fb which we
On Tue, Apr 07, 2015 at 11:57:23AM +0530, Sivakumar Thulasimani wrote:
On 3/31/2015 4:44 PM, Mika Kahola wrote:
Implement support for changing the cdclk frequency during runtime on
HSW. VLV/CHV already have support for this, so we can follow their
example for the most part. Only the
On Tue, Apr 07, 2015 at 10:20:15AM +0200, Daniel Vetter wrote:
On Thu, Apr 02, 2015 at 06:49:38PM +0530, Deepak S wrote:
On Monday 30 March 2015 09:13 PM, Daniel Vetter wrote:
On Mon, Mar 30, 2015 at 08:03:58PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
On Thu, Apr 02, 2015 at 12:15:13AM +0100, Chris Wilson wrote:
On Wed, Apr 01, 2015 at 07:40:59PM -0300, Paulo Zanoni wrote:
+static void draw_rect_mmap_wc(int fd, struct buf_data *buf, struct rect
*rect,
+ uint32_t color)
+{
+ uint32_t *ptr;
+ uint32_t
Return the return value of the set_property ioctl and add check for
the failure.
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
lib/igt_kms.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 6cb1f08..14abae8 100644
---
Adding 90/270 rotation testcase for primary and sprite planes.
v2: Added position test for sprite. Checking for gen 9 for 90/270.
Some cleanup and rebase.
v3: Added test for unsupported tiling and unsupported pixel format for 90/270
Signed-off-by: Sonika Jindal sonika.jin...@intel.com
---
where can i check this (audio driver) ? since there was no need for them
to check CD clock value till now i don't think they will be doing it.
also this needs to be changed in Display Audio controller, so not sure
if audio driver has access to it in the first place. will be good to
confirm
On Tue, Apr 07, 2015 at 10:10:25AM +0200, Daniel Vetter wrote:
On Thu, Apr 02, 2015 at 12:15:13AM +0100, Chris Wilson wrote:
On Wed, Apr 01, 2015 at 07:40:59PM -0300, Paulo Zanoni wrote:
+static void draw_rect_mmap_wc(int fd, struct buf_data *buf, struct rect
*rect,
+
On Fri, Apr 03, 2015 at 06:01:12PM -0700, jeff.mc...@intel.com wrote:
From: Jeff McGee jeff.mc...@intel.com
Pre-Gen8 devices should be skipped early instead of failing
when test resources are not found.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89822
Signed-off-by: Jeff McGee
On Thu, Apr 02, 2015 at 11:02:44AM +0530, Sonika Jindal wrote:
We make use of HW tracking for Selective update region and enable frame sync
on
sink. We use hardware's hardcoded data values for frame sync and GTC.
v2: Add 3200x2000 resolution restriction with PSR2, move psr2_support to
On Thu, Apr 02, 2015 at 08:59:33AM -0700, Matt Roper wrote:
On Thu, Apr 02, 2015 at 10:24:02AM +0530, Jindal, Sonika wrote:
I am not sure how it will help. drm_plane_check_pixel_format should
be used to check the pixel format of the fb which we should be doing
in some -check functions (I
On Wed, Apr 01, 2015 at 09:37:22PM +0300, Jani Nikula wrote:
Hi all -
I think having several overlapping register read/write/dump/etc. tools
is just silly. I've been working on unsillifying the situation a bit on
the background, in the idle moments (while my kernel's compiling).
Here's
v2: Moving creation of property in a function, checking for 90/270
rotation simultaneously (Chris)
Letting primary plane to be positioned
v3: Adding if/else for 90/270 and rest params programming, adding check for
pixel_format, some cleanup (review comments)
v4: Adding right pixel_formats, using
On Fri, Apr 03, 2015 at 02:27:46PM -0700, Matt Roper wrote:
Add tests for destination rectangle integer overflow before calling the
driver's check function. This will ensure that the transitional plane
helpers match the behavior of the full atomic helpers by always
returning -ERANGE for
On 3/31/2015 4:44 PM, Mika Kahola wrote:
Implement support for changing the cdclk frequency during runtime on
HSW. VLV/CHV already have support for this, so we can follow their
example for the most part. Only the actual hardware programming differs,
the rest is pretty much the same.
The pipe
sorry if i am missing something, HSW and BDW requires display audio
controller to be updated with new values once CD clock is modified. how
is this accomplished here ?
regards,
Sivakumar
On 4/7/2015 11:57 AM, Sivakumar Thulasimani wrote:
On 3/31/2015 4:44 PM, Mika Kahola wrote:
Implement
On Thu, Apr 02, 2015 at 02:47:56PM +0300, Ander Conselvan de Oliveira wrote:
-static void valleyview_modeset_global_pipes(struct drm_device *dev,
+static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
unsigned *prepare_pipes)
{
-
On Thu, Apr 02, 2015 at 02:47:57PM +0300, Ander Conselvan de Oliveira wrote:
Move towards atomic by using the atomic state instead.
Signed-off-by: Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 15 +++
1 file
On Thu, Apr 02, 2015 at 02:47:55PM +0300, Ander Conselvan de Oliveira wrote:
These patches remove usage of the staged config from the modeset path
that I overlooked in my previous patch series.
Ander Conselvan de Oliveira (6):
drm/i915: Don't use staged config for VLV cdclk calculations
Definitely a good idea to check the audio part as well if there is
a doubt that by changing CD clock the audio would fail. I can check
this and I'll get back once I have the results.
Cheers,
Mika
On Tue, Apr 07, 2015 at 02:06:50PM +0530, Sivakumar Thulasimani wrote:
where can i check this
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b13c5526a73b..7aaf8eddf19c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2146,14 +2146,14 @@
Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
into one function 'intel_modeset_global_pipes()'
v2:
- we don't modify 'disable_pipes', so passing this as a pointer
is removed (based on Ville's comment)
- introduced a new function 'intel_calc_cdclk()' that combines
Please try v4.0-rc7.
BR,
Jani.
On Mon, 06 Apr 2015, Winkler, Tomas tomas.wink...@intel.com wrote:
Ubuntu 14.04.2 LTS
00:02.0 VGA compatible controller: Intel Corporation Xeon E3-1200 v3/4th Gen
Core Processor Integrated Graphics Controller (rev 06) (prog-if 00 [VGA
controller])
On Mon, 06 Apr 2015, Chandra Konduru chandra.kond...@intel.com wrote:
At end of intel_crtc_set_config, reset crtc_state's
drm_state back pointer to null.
This does not tell me anything that reading the patch already
didn't. Please explain *why* this is needed in the commit message. What
breaks
On Tue, Apr 07, 2015 at 09:36:37AM +0100, Chris Wilson wrote:
On Tue, Apr 07, 2015 at 10:10:25AM +0200, Daniel Vetter wrote:
On Thu, Apr 02, 2015 at 12:15:13AM +0100, Chris Wilson wrote:
On Wed, Apr 01, 2015 at 07:40:59PM -0300, Paulo Zanoni wrote:
+static void draw_rect_mmap_wc(int fd,
Hey,
Op 20-03-15 om 18:48 schreef john.c.harri...@intel.com:
From: John Harrison john.c.harri...@intel.com
There is a construct in the linux kernel called 'struct fence' that is
intended
to keep track of work that is executed on hardware. I.e. it solves the basic
problem that the drivers
On Thu, Apr 02, 2015 at 02:47:59PM +0300, Ander Conselvan de Oliveira wrote:
Reduce dependency on the staged config by using the atomic state
instead.
Signed-off-by: Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 22
On Tue, Apr 07, 2015 at 11:07:07AM +0200, Daniel Vetter wrote:
On Tue, Apr 07, 2015 at 09:36:37AM +0100, Chris Wilson wrote:
On Tue, Apr 07, 2015 at 10:10:25AM +0200, Daniel Vetter wrote:
On Thu, Apr 02, 2015 at 12:15:13AM +0100, Chris Wilson wrote:
On Wed, Apr 01, 2015 at 07:40:59PM
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 53 +++--
3 files changed, 41 insertions(+), 22 deletions(-)
diff
Hey,
Op 07-04-15 om 12:59 schreef John Harrison:
On 07/04/2015 10:18, Maarten Lankhorst wrote:
Hey,
Op 20-03-15 om 18:48 schreef john.c.harri...@intel.com:
From: John Harrison john.c.harri...@intel.com
There is a construct in the linux kernel called 'struct fence' that is
intended
to
On Tue, Apr 07, 2015 at 10:53:20AM +0200, Daniel Vetter wrote:
On Thu, Apr 02, 2015 at 04:04:14PM +0100, Chris Wilson wrote:
Once userptr becomes part of client API, it is almost a certainly that
eventually someone will try to create a new object from a mapping of
another client object,
On Tue, Apr 07, 2015 at 10:05:39AM +0200, Daniel Vetter wrote:
On Fri, Apr 03, 2015 at 10:43:29AM +0100, Chris Wilson wrote:
I resurrected my dual-channel evenly loaded gm45 and to my surprise
found it reporting a L-shaped memory layout.
Well my gm45 is also dual-channel and evenly loaded
On 07/04/2015 10:18, Maarten Lankhorst wrote:
Hey,
Op 20-03-15 om 18:48 schreef john.c.harri...@intel.com:
From: John Harrison john.c.harri...@intel.com
There is a construct in the linux kernel called 'struct fence' that is intended
to keep track of work that is executed on hardware. I.e. it
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6135
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1
Add a straightforward test that allocates a BO that is bigger than
(by 1 page currently) the mappable aperture, tests mmap access to it
by CPU directly and through GTT in sequence.
Currently it is expected for the GTT access to gracefully fail as
all objects are attempted to get pinned to GTT
According to Spec this is a reserved bit for Gen9+ and should not be set.
Change-Id: I0215fb7057b94139b7a2f90ecc7a0201c0c93ad4
Signed-off-by: Arun Siluvery arun.siluv...@linux.intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
On Thu, 02 Apr 2015, Darren Hart darren.h...@intel.com wrote:
Jesse Barnes jbarnes at virtuousgeek.org writes:
Looks like it was introduced in:
commit 650ad970a39f8b6164fe8613edc150f585315289
Author: Imre Deak imre.deak at intel.com
Date: Fri Apr 18 16:35:02 2014 +0300
drm/i915:
On Tue, Apr 07, 2015 at 11:32:02AM +0200, Maarten Lankhorst wrote:
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b13c5526a73b..7aaf8eddf19c 100644
---
On Tue, Apr 07, 2015 at 03:51:44PM +0200, Maarten Lankhorst wrote:
Op 07-04-15 om 15:37 schreef Daniel Vetter:
On Tue, Apr 07, 2015 at 11:32:02AM +0200, Maarten Lankhorst wrote:
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
diff --git
2015-04-06 23:09 GMT-03:00 Todd Previte tprev...@gmail.com:
The Displayport Link Layer Compliance Testing Specification 1.2 rev 1.1
specifies that repeated AUX transactions after a failure (no response /
invalid response) must have a minimum delay of 400us before the resend can
occur. Tests
Arun Siluvery arun.siluv...@linux.intel.com writes:
According to Spec this is a reserved bit for Gen9+ and should not be set.
Change-Id: I0215fb7057b94139b7a2f90ecc7a0201c0c93ad4
Signed-off-by: Arun Siluvery arun.siluv...@linux.intel.com
---
Reviewed-by: Mika Kuoppala
On Tue, Apr 07, 2015 at 12:29:25PM +0300, Mika Kahola wrote:
Definitely a good idea to check the audio part as well if there is
a doubt that by changing CD clock the audio would fail. I can check
this and I'll get back once I have the results.
We force a full modeset, which should result in an
On Tue, Apr 07, 2015 at 11:12:09AM +0100, Chris Wilson wrote:
On Tue, Apr 07, 2015 at 11:07:07AM +0200, Daniel Vetter wrote:
On Tue, Apr 07, 2015 at 09:36:37AM +0100, Chris Wilson wrote:
On Tue, Apr 07, 2015 at 10:10:25AM +0200, Daniel Vetter wrote:
On Thu, Apr 02, 2015 at 12:15:13AM
Op 07-04-15 om 15:37 schreef Daniel Vetter:
On Tue, Apr 07, 2015 at 11:32:02AM +0200, Maarten Lankhorst wrote:
Signed-off-by: Maarten Lankhorst maarten.lankho...@linux.intel.com
---
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index
On to, 2015-04-02 at 19:32 +0300, Ville Syrjälä wrote:
On Tue, Mar 17, 2015 at 11:39:56AM +0200, Imre Deak wrote:
From: Vandana Kannan vandana.kan...@intel.com
Add display clock/PHY initialization sequence as per BSpec.
Until GOP/VBIOS provides an upper limit value for CDCLK,
On Tue, Apr 07, 2015 at 03:23:08PM +0300, Joonas Lahtinen wrote:
static void
+test_huge_bo(int fd)
+{
+ uint32_t bo;
+ char *ptr_cpu;
+ char *ptr_gtt;
+ char *cpu_pattern;
+ uint64_t mappable_aperture_pages = gem_mappable_aperture_size() /
+
On Tue, Apr 07, 2015 at 05:46:19PM +0300, Mika Kuoppala wrote:
Chris Wilson ch...@chris-wilson.co.uk writes:
After we successfully allocate them, we will fill them with their
initial contents (either the chain of page tables, or a pointer to the
scratch page).
Regression from
commit
On Tue, 31 Mar 2015, jinwb ji...@sonoscape.net wrote:
My machine is intel gm45 chipset,i found a problem in ubuntu 10.04.
When i use xrandr to change output on VGA and TV, sometime is not
successd.I update ubuntu 10.04 to ubuntu 13.04,founding the bug has
solved, but my compony need the
2015-04-06 23:11 GMT-03:00 Todd Previte tprev...@gmail.com:
For test 4.2.2.5 to pass per the Link CTS Core 1.2 rev1.1 spec, the source
device must attempt at least 7 times to read the EDID when it receives an
I2C defer. The normal DRM code makes only 7 retries, regardless of whether
or not the
On Tue, Apr 07, 2015 at 11:29:43AM -0300, Paulo Zanoni wrote:
2015-04-06 23:11 GMT-03:00 Todd Previte tprev...@gmail.com:
For test 4.2.2.5 to pass per the Link CTS Core 1.2 rev1.1 spec, the source
device must attempt at least 7 times to read the EDID when it receives an
I2C defer. The
Chris Wilson ch...@chris-wilson.co.uk writes:
After we successfully allocate them, we will fill them with their
initial contents (either the chain of page tables, or a pointer to the
scratch page).
Regression from
commit 06fda602dbca9c59d87db7da71192e4b54c9f5ff
Author: Ben Widawsky
After we successfully allocate them, we will fill them with their
initial contents (either the chain of page tables, or a pointer to the
scratch page).
Regression from
commit 06fda602dbca9c59d87db7da71192e4b54c9f5ff
Author: Ben Widawsky benjamin.widaw...@intel.com
Date: Tue Feb 24 16:22:36 2015
We now have two implementations for vmapping a whole object, one for
dma-buf and one for the ringbuffer. If we couple the vmapping into the
obj-pages lifetime, then we can reuse an obj-vmapping for both and at
the same time couple it into the shrinker.
Signed-off-by: Chris Wilson
Since we use obj-active as a hint in many places throughout the code,
knowing its state in debugfs is extremely useful.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
1 file changed, 2
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_lrc.c| 56 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 +-
2 files changed, 31 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
Reuse the same reclocking strategy for Baytail as on its bigger brethren,
Sandybridge and Ivybridge. In particular, this makes the device quicker
to reclock (both up and down) though the tendency now is to downclock
more aggressively to compensate for the RPS boosts.
v2: Rebase
v3: Exclude
Since we will often pageflip to an active surface, we will often have to
wait for the surface to be written before issuing the flip. Also we are
likely to wait on that surface in plenty of time before the vblank.
Since we have a mechanism for boosting when a flip misses the expected
vblank,
vma are more frequently allocated than objects and so should equally
benefit from having a dedicated slab.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_dma.c | 4
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 7
This is mostly useful for execlists where the rings switch between
contexts (and so checking that the ring's start register matches the
context is important).
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
In a few cases, having a direct pointer to the drm_i915_private from the
request is useful.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 11 ---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
2 files changed, 5 insertions(+), 8 deletions(-)
diff
The hardware is documentated as treating the TAIL register update as
serialising, so we can relax the barriers when filling the rings.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_lrc.h| 6 +++---
drivers/gpu/drm/i915/intel_ringbuffer.h | 17
Synchronising to an object active on the same ring is a no-op, for the
benefit of execbuffer scheduler. However, for CS flips this means that
we can forgo checking whether the last write request of the object is
actually queued and more importantly whether the cache flush for the
write was
Fixes regression from
commit 48d823878d64f93163f5a949623346748bbce1b4
Author: Oscar Mateo oscar.ma...@intel.com
Date: Thu Jul 24 17:04:23 2014 +0100
drm/i915/bdw: Generic logical ring init and cleanup
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
We can use the simpler spinlock form to disable interrupts as we are
always outside of an irq/softirq handler.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_lrc.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git
Instead of querying the reset counter before every access to the ring,
query it the first time we touch the ring, and do a final compare when
submitting the request. For correctness, we need to then sanitize how
the reset_counter is incremented to prevent broken submission and
waiting across
When doing relocations, we have to obtain a mapping to the page
containing the target address. This is either a kmap or iomap depending
on GPU and its cache coherency. Neighbouring relocation entries are
typically within the same page and so we can cache our kmapping between
them and avoid those
The multiple levels of indirect do nothing but hinder the compiler and
the pointer chasing turns to be quite painful but painless to fix.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_drv.h | 4 +---
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
The issue is that by computing the last_adj value after applying the
clamping, we can end up with a bogus value for feeding into the next RPS
autotuning step.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Daniel Vetter daniel.vet...@ffwll.ch
Cc: Deepak S deepa...@linux.intel.com
12:58 jlahtine there're actually equally many i915_is_ggtt(vma-vm)
calls
12:58 jlahtine (one less)
12:59 jlahtine so while at it I'd make it vm-is_ggtt and
vma-is_ggtt
12:59 jlahtine then get rid of the whole helper, maybe
13:00 ickle you preempted my beautiful macro
13:03 ickle just don't
We already assign a unique identifier to every request: seqno. That
someone felt like adding a second one without even mentioning why and
tweaking ABI smells very fishy.
Fixes regression from
commit b3a38998f042b862f5ba4d7f2268f3a8dfb4883a
Author: Nick Hoath nicholas.ho...@intel.com
Date: Thu
If we hit a vblank and see that have a pageflip queue but not yet
processed, ensure that the GPU is running at maximum in order to clear
the backlog. Pageflips are only queued for the following vblank, if we
miss it, there will be a visible stutter. Boosting the GPU frequency
doesn't prevent us
With boosting for missed pageflips, we have a much stronger indication
of when we need to (temporarily) boost GPU frequency to ensure smooth
delivery of frames. So now only allow each client to perform one RPS boost
in each period of GPU activity due to stalling on results.
Signed-off-by: Chris
Lots of pickings here to improve both microbenchmarks and beyond across
several generations. Have fun!
-Chris
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Ring switches can occur many times per frame, and are often out of
control, causing frequent RPS boosting for no practical benefit. Treat
the sw semaphore synchronisation as a separate client and only allow it
to boost once per busy/idle cycle.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Now with the trimmed memcpy before the command parser, we try to
allocate many different sizes of batches, predominantly one or two
pages. We can therefore speed up searching for a good sized batch by
keeping the objects of buckets of roughly the same size.
v2: Add a comment about bucket sizes
In the next patch, I want to use the structure elsewhere and so require
it defined earlier. Rather than move the definition to an earlier location
where it feels very odd, place it in its own header file.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Tvrtko Ursulin
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6139
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -5
In i915, we have a big mutex around our device struct - every time before
we attempt to communicate with the GPU, we acquire the mutex. This makes
it a convenient juncture to place our GPU error handling - before we take
the mutex we first check whether the GPU is hung or whether we are in
the
Hello,
since late 4.0-rc4 / early4.0-rc5 drm-intel branch I'm experiencing lockups
every time I try to connect my lenovo t440p laptop to its docking station.
[ 143.896172] [ cut here ]
[ 143.896182] WARNING: CPU: 0 PID: 1102 at
In preparation for exporting very similar functionality through another
interface, gut the current remap_pfn_range(). The motivating factor here
is to reuse the PGB/PUD/PMD/PTE walker, but allow back progation of
errors rather than BUG_ON.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc:
On Tue, Apr 07, 2015 at 05:03:32PM +0300, Mika Kuoppala wrote:
Arun Siluvery arun.siluv...@linux.intel.com writes:
According to Spec this is a reserved bit for Gen9+ and should not be set.
Change-Id: I0215fb7057b94139b7a2f90ecc7a0201c0c93ad4
Signed-off-by: Arun Siluvery
Not only does it make for good documentation and debugging aide, but it
is also vital for when we want to unwind requests - such as when
throwing away an incomplete request.
v2: Rebase
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 13
This provides a nice boost to mesa in swap bound scenarios (as mesa
throttles itself to the previous frame and given the scenario that will
complete shortly). It will also provide a good boost to systems running
with semaphores disabled and so frequently waiting on the GPU as it
switches rings. In
Currently we emit semaphore synchronisation as if we were going to flip
using the target CS engine, but we then change our minds and do the flip
using the CPU. Consequently we write instructions to the ring but never
use them - even to the point of filling that ring up entirely and never
This trims a little overhead from the common case of not needing to
synchronize between rings.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git
At runtime, this helps ensure that the batch pools are kept trim and
fast. Then at suspend, this releases memory that we do not need to
restore. It also ties into the oom-notifier to ensure that we recover as
much kernel memory as possible during OOM.
Signed-off-by: Chris Wilson
If we have llc coherency, we can write directly into the ringbuffer
using ordinary cached writes rather than forcing WC access.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 60 +++--
1 file changed, 49
After the removal of DRI1, all access to the rings are through requests
and so we can always be sure that there is a request to wait upon to
free up available space. The fallback code only existed so that we could
quiesce the GPU following unmediated access by DRI1.
v2: Rebase
Signed-off-by:
When looking for viable candidates to shrink, we only want objects that
are not pinned. However to do so we performed a double iteration over
the vma in the objects, first looking for the pin-count, then looking
for allocations. We can do both at once and be slightly more explicit in
our validity
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