sorry if i am missing something, HSW and BDW requires display audio
controller to be updated with new values once CD clock is modified. how
is this accomplished here ?
regards,
Sivakumar
On 4/7/2015 11:57 AM, Sivakumar Thulasimani wrote:
On 3/31/2015 4:44 PM, Mika Kahola wrote:
Implement su
On Fri, Apr 03, 2015 at 10:43:29AM +0100, Chris Wilson wrote:
> On Thu, Nov 20, 2014 at 09:26:30AM +0100, Daniel Vetter wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c
> > b/drivers/gpu/drm/i915/i915_gem_tiling.c
> > index 749ab485569e..03c675a4476e 100644
> > --- a/drivers/gpu/drm/
On Thu, Apr 02, 2015 at 11:02:44AM +0530, Sonika Jindal wrote:
> We make use of HW tracking for Selective update region and enable frame sync
> on
> sink. We use hardware's hardcoded data values for frame sync and GTC.
>
> v2: Add 3200x2000 resolution restriction with PSR2, move psr2_support to
On Thu, Apr 02, 2015 at 08:59:33AM -0700, Matt Roper wrote:
> On Thu, Apr 02, 2015 at 10:24:02AM +0530, Jindal, Sonika wrote:
> > I am not sure how it will help. drm_plane_check_pixel_format should
> > be used to check the pixel format of the fb which we should be doing
> > in some -check functions
On Thu, Apr 02, 2015 at 02:50:09PM -0700, Jeff McGee wrote:
> On Wed, Apr 01, 2015 at 08:20:44AM +0200, Daniel Vetter wrote:
> > On Tue, Mar 31, 2015 at 09:59:22AM -0700, jeff.mc...@intel.com wrote:
> > > From: Jeff McGee
> > >
> > > BXT uses a subset of the SKL fuse registers, because it has at
On 4/7/2015 1:46 PM, Daniel Vetter wrote:
On Mon, Apr 06, 2015 at 10:50:51AM +0530, Jindal, Sonika wrote:
On 4/2/2015 9:18 PM, Matt Roper wrote:
On Thu, Apr 02, 2015 at 10:08:27AM +0530, Jindal, Sonika wrote:
On 4/1/2015 11:51 PM, Matt Roper wrote:
On Mon, Mar 30, 2015 at 02:04:56PM +05
On Mon, Apr 06, 2015 at 10:50:51AM +0530, Jindal, Sonika wrote:
>
>
> On 4/2/2015 9:18 PM, Matt Roper wrote:
> >On Thu, Apr 02, 2015 at 10:08:27AM +0530, Jindal, Sonika wrote:
> >>
> >>
> >>On 4/1/2015 11:51 PM, Matt Roper wrote:
> >>>On Mon, Mar 30, 2015 at 02:04:56PM +0530, Sonika Jindal wrote:
On 4/7/2015 1:43 PM, Daniel Vetter wrote:
On Thu, Apr 02, 2015 at 08:59:33AM -0700, Matt Roper wrote:
On Thu, Apr 02, 2015 at 10:24:02AM +0530, Jindal, Sonika wrote:
I am not sure how it will help. drm_plane_check_pixel_format should
be used to check the pixel format of the fb which we should
On Thu, Apr 02, 2015 at 06:49:38PM +0530, Deepak S wrote:
>
>
> On Monday 30 March 2015 09:13 PM, Daniel Vetter wrote:
> >On Mon, Mar 30, 2015 at 08:03:58PM +0530, deepa...@linux.intel.com wrote:
> >>From: Deepak S
> >>
> >>Cleanup idr table if any error happens after __create_hw_context() in
>
On Wed, Apr 01, 2015 at 06:41:32PM +0300, Ville Syrjälä wrote:
> On Tue, Mar 31, 2015 at 04:03:21PM -0700, Rodrigo Vivi wrote:
> > Program the default initial value of the L3SqcReg1 on BDW for performance
> >
> > v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.
> >
> > v3:
On Tue, Apr 07, 2015 at 11:57:23AM +0530, Sivakumar Thulasimani wrote:
>
>
> On 3/31/2015 4:44 PM, Mika Kahola wrote:
> > Implement support for changing the cdclk frequency during runtime on
> > HSW. VLV/CHV already have support for this, so we can follow their
> > example for the most part. Only
On Wed, Apr 01, 2015 at 01:43:46PM +0200, Daniel Vetter wrote:
> We stopped handling them in
>
> commit aaecdf611a05cac26a94713bad25297e60225c29
> Author: Daniel Vetter
> Date: Tue Nov 4 15:52:22 2014 +0100
>
> drm/i915: Stop gathering error states for CS error interrupts
>
> but just cle
On Tue, Apr 07, 2015 at 12:33:40PM +0530, Sivakumar Thulasimani wrote:
> sorry if i am missing something, HSW and BDW requires display audio
> controller to be updated with new values once CD clock is modified. how
> is this accomplished here ?
I'm hoping the audio driver will query the cdclk fr
On Tue, Apr 07, 2015 at 10:20:15AM +0200, Daniel Vetter wrote:
> On Thu, Apr 02, 2015 at 06:49:38PM +0530, Deepak S wrote:
> >
> >
> > On Monday 30 March 2015 09:13 PM, Daniel Vetter wrote:
> > >On Mon, Mar 30, 2015 at 08:03:58PM +0530, deepa...@linux.intel.com wrote:
> > >>From: Deepak S
> > >>
On Thu, Apr 02, 2015 at 12:15:13AM +0100, Chris Wilson wrote:
> On Wed, Apr 01, 2015 at 07:40:59PM -0300, Paulo Zanoni wrote:
> > +static void draw_rect_mmap_wc(int fd, struct buf_data *buf, struct rect
> > *rect,
> > + uint32_t color)
> > +{
> > + uint32_t *ptr;
> > +
On Wed, Apr 01, 2015 at 09:37:22PM +0300, Jani Nikula wrote:
> Hi all -
>
> I think having several overlapping register read/write/dump/etc. tools
> is just silly. I've been working on unsillifying the situation a bit on
> the background, in the idle moments ("while my kernel's compiling").
>
> H
v2: Moving creation of property in a function, checking for 90/270
rotation simultaneously (Chris)
Letting primary plane to be positioned
v3: Adding if/else for 90/270 and rest params programming, adding check for
pixel_format, some cleanup (review comments)
v4: Adding right pixel_formats, using sr
On Tue, Apr 07, 2015 at 10:10:25AM +0200, Daniel Vetter wrote:
> On Thu, Apr 02, 2015 at 12:15:13AM +0100, Chris Wilson wrote:
> > On Wed, Apr 01, 2015 at 07:40:59PM -0300, Paulo Zanoni wrote:
> > > +static void draw_rect_mmap_wc(int fd, struct buf_data *buf, struct rect
> > > *rect,
> > > +
Return the return value of the set_property ioctl and add check for
the failure.
Signed-off-by: Sonika Jindal
---
lib/igt_kms.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 6cb1f08..14abae8 100644
--- a/lib/igt_kms.c
+++ b/lib/
Adding 90/270 rotation testcase for primary and sprite planes.
v2: Added position test for sprite. Checking for gen > 9 for 90/270.
Some cleanup and rebase.
v3: Added test for unsupported tiling and unsupported pixel format for 90/270
Signed-off-by: Sonika Jindal
---
tests/kms_rotation_crc.c |
where can i check this (audio driver) ? since there was no need for them
to check CD clock value till now i don't think they will be doing it.
also this needs to be changed in Display Audio controller, so not sure
if audio driver has access to it in the first place. will be good to
confirm this
On Thu, Apr 02, 2015 at 04:03:22PM -0700, Matt Roper wrote:
> On Wed, Apr 01, 2015 at 07:59:35PM -0700, Chandra Konduru wrote:
> > This patch converts intel_plane_state->src rect from 16.16
> > values into regular ints.
> >
> > This approach aligns with sprite_plane_state->src rects
> > which are
On Thu, Apr 02, 2015 at 04:04:14PM +0100, Chris Wilson wrote:
> Once userptr becomes part of client API, it is almost a certainly that
> eventually someone will try to create a new object from a mapping of
> another client object, e.g.
>
> new = vaImport(vaMap(old, &size), size);
>
> (using a hyp
On Thu, Apr 02, 2015 at 06:28:07PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> ../drivers/gpu/drm/i915/intel_pm.c:3185:45: warning: Initializer entry
> defined twice
> ../drivers/gpu/drm/i915/intel_pm.c:3185:52: also defined here
>
> Signed-off-by: Ville Syrjälä
Qu
On Fri, Apr 03, 2015 at 06:01:12PM -0700, jeff.mc...@intel.com wrote:
> From: Jeff McGee
>
> Pre-Gen8 devices should be skipped early instead of failing
> when test resources are not found.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89822
> Signed-off-by: Jeff McGee
Applied, th
Please try v4.0-rc7.
BR,
Jani.
On Mon, 06 Apr 2015, "Winkler, Tomas" wrote:
> Ubuntu 14.04.2 LTS
> 00:02.0 VGA compatible controller: Intel Corporation Xeon E3-1200 v3/4th Gen
> Core Processor Integrated Graphics Controller (rev 06) (prog-if 00 [VGA
> controller])
> Subsystem: Gigabyt
On Mon, 06 Apr 2015, Chandra Konduru wrote:
> At end of intel_crtc_set_config, reset crtc_state's
> drm_state back pointer to null.
This does not tell me anything that reading the patch already
didn't. Please explain *why* this is needed in the commit message. What
breaks without it? If this fixe
On Tue, Apr 07, 2015 at 09:36:37AM +0100, Chris Wilson wrote:
> On Tue, Apr 07, 2015 at 10:10:25AM +0200, Daniel Vetter wrote:
> > On Thu, Apr 02, 2015 at 12:15:13AM +0100, Chris Wilson wrote:
> > > On Wed, Apr 01, 2015 at 07:40:59PM -0300, Paulo Zanoni wrote:
> > > > +static void draw_rect_mmap_wc
On Thu, Apr 02, 2015 at 02:47:56PM +0300, Ander Conselvan de Oliveira wrote:
> -static void valleyview_modeset_global_pipes(struct drm_device *dev,
> +static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
> unsigned *prepare_pipes)
> {
Hey,
Op 20-03-15 om 18:48 schreef john.c.harri...@intel.com:
> From: John Harrison
>
> There is a construct in the linux kernel called 'struct fence' that is
> intended
> to keep track of work that is executed on hardware. I.e. it solves the basic
> problem that the drivers 'struct drm_i915_gem_
On Thu, Apr 02, 2015 at 02:47:57PM +0300, Ander Conselvan de Oliveira wrote:
> Move towards atomic by using the atomic state instead.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/i915/intel_display.c | 15 +++
> 1 file changed, 11 insertions(+), 4 deletio
On Thu, Apr 02, 2015 at 02:47:59PM +0300, Ander Conselvan de Oliveira wrote:
> Reduce dependency on the staged config by using the atomic state
> instead.
>
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> drivers/gpu/drm/i915/intel_display.c | 22 ++
> 1 file changed,
On Thu, Apr 02, 2015 at 02:47:55PM +0300, Ander Conselvan de Oliveira wrote:
> These patches remove usage of the staged config from the modeset path
> that I overlooked in my previous patch series.
>
> Ander Conselvan de Oliveira (6):
> drm/i915: Don't use staged config for VLV cdclk calculation
Definitely a good idea to check the audio part as well if there is
a doubt that by changing CD clock the audio would fail. I can check
this and I'll get back once I have the results.
Cheers,
Mika
On Tue, Apr 07, 2015 at 02:06:50PM +0530, Sivakumar Thulasimani wrote:
> where can i check this (au
Signed-off-by: Maarten Lankhorst
---
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b13c5526a73b..7aaf8eddf19c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2146,14 +2146,14 @@ i915_gem_request_unreference(struct
drm_i
Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
into one function 'intel_modeset_global_pipes()'
v2:
- we don't modify 'disable_pipes', so passing this as a pointer
is removed (based on Ville's comment)
- introduced a new function 'intel_calc_cdclk()' that combines
routin
On Tue, Apr 07, 2015 at 11:07:07AM +0200, Daniel Vetter wrote:
> On Tue, Apr 07, 2015 at 09:36:37AM +0100, Chris Wilson wrote:
> > On Tue, Apr 07, 2015 at 10:10:25AM +0200, Daniel Vetter wrote:
> > > On Thu, Apr 02, 2015 at 12:15:13AM +0100, Chris Wilson wrote:
> > > > On Wed, Apr 01, 2015 at 07:40
On Tue, Apr 07, 2015 at 10:53:20AM +0200, Daniel Vetter wrote:
> On Thu, Apr 02, 2015 at 04:04:14PM +0100, Chris Wilson wrote:
> > Once userptr becomes part of client API, it is almost a certainly that
> > eventually someone will try to create a new object from a mapping of
> > another client objec
On Tue, Apr 07, 2015 at 10:05:39AM +0200, Daniel Vetter wrote:
> On Fri, Apr 03, 2015 at 10:43:29AM +0100, Chris Wilson wrote:
> > I resurrected my dual-channel evenly loaded gm45 and to my surprise
> > found it reporting a L-shaped memory layout.
>
> Well my gm45 is also dual-channel and evenly l
Signed-off-by: Nick Hoath
---
drivers/gpu/drm/i915/i915_reg.h | 8 +
drivers/gpu/drm/i915/intel_pm.c | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 53 +++--
3 files changed, 41 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/
On 07/04/2015 10:18, Maarten Lankhorst wrote:
Hey,
Op 20-03-15 om 18:48 schreef john.c.harri...@intel.com:
From: John Harrison
There is a construct in the linux kernel called 'struct fence' that is intended
to keep track of work that is executed on hardware. I.e. it solves the basic
problem t
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6135
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1
Hey,
Op 07-04-15 om 12:59 schreef John Harrison:
> On 07/04/2015 10:18, Maarten Lankhorst wrote:
>> Hey,
>>
>> Op 20-03-15 om 18:48 schreef john.c.harri...@intel.com:
>>> From: John Harrison
>>>
>>> There is a construct in the linux kernel called 'struct fence' that is
>>> intended
>>> to keep t
Add a straightforward test that allocates a BO that is bigger than
(by 1 page currently) the mappable aperture, tests mmap access to it
by CPU directly and through GTT in sequence.
Currently it is expected for the GTT access to gracefully fail as
all objects are attempted to get pinned to GTT comp
According to Spec this is a reserved bit for Gen9+ and should not be set.
Change-Id: I0215fb7057b94139b7a2f90ecc7a0201c0c93ad4
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
On Thu, 02 Apr 2015, Darren Hart wrote:
> Jesse Barnes virtuousgeek.org> writes:
>> Looks like it was introduced in:
>>
>> commit 650ad970a39f8b6164fe8613edc150f585315289
>> Author: Imre Deak intel.com>
>> Date: Fri Apr 18 16:35:02 2014 +0300
>>
>> drm/i915: vlv: factor out vlv_force_gfx
On Tue, Apr 07, 2015 at 11:32:02AM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
> ---
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b13c5526a73b..7aaf8eddf19c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i91
On Tue, Apr 07, 2015 at 11:12:09AM +0100, Chris Wilson wrote:
> On Tue, Apr 07, 2015 at 11:07:07AM +0200, Daniel Vetter wrote:
> > On Tue, Apr 07, 2015 at 09:36:37AM +0100, Chris Wilson wrote:
> > > On Tue, Apr 07, 2015 at 10:10:25AM +0200, Daniel Vetter wrote:
> > > > On Thu, Apr 02, 2015 at 12:15
On Tue, Apr 07, 2015 at 12:29:25PM +0300, Mika Kahola wrote:
> Definitely a good idea to check the audio part as well if there is
> a doubt that by changing CD clock the audio would fail. I can check
> this and I'll get back once I have the results.
We force a full modeset, which should result in
Op 07-04-15 om 15:37 schreef Daniel Vetter:
> On Tue, Apr 07, 2015 at 11:32:02AM +0200, Maarten Lankhorst wrote:
>> Signed-off-by: Maarten Lankhorst
>> ---
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index b13c5526a73b..7aaf8eddf19c 100644
>> --- a/driv
2015-04-06 23:09 GMT-03:00 Todd Previte :
> The Displayport Link Layer Compliance Testing Specification 1.2 rev 1.1
> specifies that repeated AUX transactions after a failure (no response /
> invalid response) must have a minimum delay of 400us before the resend can
> occur. Tests 4.2.1.1 and 4.2.1
On Tue, Apr 07, 2015 at 03:51:44PM +0200, Maarten Lankhorst wrote:
> Op 07-04-15 om 15:37 schreef Daniel Vetter:
> > On Tue, Apr 07, 2015 at 11:32:02AM +0200, Maarten Lankhorst wrote:
> >> Signed-off-by: Maarten Lankhorst
> >> ---
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> >> b/drivers/g
Arun Siluvery writes:
> According to Spec this is a reserved bit for Gen9+ and should not be set.
>
> Change-Id: I0215fb7057b94139b7a2f90ecc7a0201c0c93ad4
> Signed-off-by: Arun Siluvery
> ---
Reviewed-by: Mika Kuoppala
> drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
> 1 file changed, 2 insertion
On to, 2015-04-02 at 19:32 +0300, Ville Syrjälä wrote:
> On Tue, Mar 17, 2015 at 11:39:56AM +0200, Imre Deak wrote:
> > From: Vandana Kannan
> >
> > Add display clock/PHY initialization sequence as per BSpec.
> >
> > Until GOP/VBIOS provides an upper limit value for CDCLK, comparing clock
> > va
On Tue, Apr 07, 2015 at 03:23:08PM +0300, Joonas Lahtinen wrote:
> static void
> +test_huge_bo(int fd)
> +{
> + uint32_t bo;
> + char *ptr_cpu;
> + char *ptr_gtt;
> + char *cpu_pattern;
> + uint64_t mappable_aperture_pages = gem_mappable_aperture_size() /
> +
On Tue, 31 Mar 2015, jinwb wrote:
> My machine is intel gm45 chipset,i found a problem in ubuntu 10.04.
> When i use xrandr to change output on VGA and TV, sometime is not
> successd.I update ubuntu 10.04 to ubuntu 13.04,founding the bug has
> solved, but my compony need the machine use ubuntu
2015-04-06 23:11 GMT-03:00 Todd Previte :
> For test 4.2.2.5 to pass per the Link CTS Core 1.2 rev1.1 spec, the source
> device must attempt at least 7 times to read the EDID when it receives an
> I2C defer. The normal DRM code makes only 7 retries, regardless of whether
> or not the response is a
Chris Wilson writes:
> After we successfully allocate them, we will fill them with their
> initial contents (either the chain of page tables, or a pointer to the
> scratch page).
>
> Regression from
> commit 06fda602dbca9c59d87db7da71192e4b54c9f5ff
> Author: Ben Widawsky
> Date: Tue Feb 24 16:
On Tue, Apr 07, 2015 at 11:29:43AM -0300, Paulo Zanoni wrote:
> 2015-04-06 23:11 GMT-03:00 Todd Previte :
> > For test 4.2.2.5 to pass per the Link CTS Core 1.2 rev1.1 spec, the source
> > device must attempt at least 7 times to read the EDID when it receives an
> > I2C defer. The normal DRM code m
On Tue, Apr 07, 2015 at 05:46:19PM +0300, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > After we successfully allocate them, we will fill them with their
> > initial contents (either the chain of page tables, or a pointer to the
> > scratch page).
> >
> > Regression from
> > commit 06fda602db
On Tuesday 07 April 2015 02:02 PM, Chris Wilson wrote:
On Tue, Apr 07, 2015 at 10:20:15AM +0200, Daniel Vetter wrote:
On Thu, Apr 02, 2015 at 06:49:38PM +0530, Deepak S wrote:
On Monday 30 March 2015 09:13 PM, Daniel Vetter wrote:
On Mon, Mar 30, 2015 at 08:03:58PM +0530, deepa...@linux.int
If we hit a vblank and see that have a pageflip queue but not yet
processed, ensure that the GPU is running at maximum in order to clear
the backlog. Pageflips are only queued for the following vblank, if we
miss it, there will be a visible stutter. Boosting the GPU frequency
doesn't prevent us fro
With boosting for missed pageflips, we have a much stronger indication
of when we need to (temporarily) boost GPU frequency to ensure smooth
delivery of frames. So now only allow each client to perform one RPS boost
in each period of GPU activity due to stalling on results.
Signed-off-by: Chris Wi
Lots of pickings here to improve both microbenchmarks and beyond across
several generations. Have fun!
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
When doing relocations, we have to obtain a mapping to the page
containing the target address. This is either a kmap or iomap depending
on GPU and its cache coherency. Neighbouring relocation entries are
typically within the same page and so we can cache our kmapping between
them and avoid those pe
The multiple levels of indirect do nothing but hinder the compiler and
the pointer chasing turns to be quite painful but painless to fix.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 4 +---
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
drivers/gpu/drm/i915/i915_gem_gtt.h |
The issue is that by computing the last_adj value after applying the
clamping, we can end up with a bogus value for feeding into the next RPS
autotuning step.
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
Cc: Deepak S
Reviewed-by: Deepak S
---
drivers/gpu/drm/i915/i915_irq.c | 27
12:58 < jlahtine> there're actually equally many i915_is_ggtt(vma->vm)
calls
12:58 < jlahtine> (one less)
12:59 < jlahtine> so while at it I'd make it vm->is_ggtt and
vma->is_ggtt
12:59 < jlahtine> then get rid of the whole helper, maybe
13:00 < ickle> you preempted my beautiful macro
13:03 < ickle
We already assign a unique identifier to every request: seqno. That
someone felt like adding a second one without even mentioning why and
tweaking ABI smells very fishy.
Fixes regression from
commit b3a38998f042b862f5ba4d7f2268f3a8dfb4883a
Author: Nick Hoath
Date: Thu Feb 19 16:30:47 2015 +
Ring switches can occur many times per frame, and are often out of
control, causing frequent RPS boosting for no practical benefit. Treat
the sw semaphore synchronisation as a separate client and only allow it
to boost once per busy/idle cycle.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i91
Now with the trimmed memcpy before the command parser, we try to
allocate many different sizes of batches, predominantly one or two
pages. We can therefore speed up searching for a good sized batch by
keeping the objects of buckets of roughly the same size.
v2: Add a comment about bucket sizes
Si
In the next patch, I want to use the structure elsewhere and so require
it defined earlier. Rather than move the definition to an earlier location
where it feels very odd, place it in its own header file.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.
After we successfully allocate them, we will fill them with their
initial contents (either the chain of page tables, or a pointer to the
scratch page).
Regression from
commit 06fda602dbca9c59d87db7da71192e4b54c9f5ff
Author: Ben Widawsky
Date: Tue Feb 24 16:22:36 2015 +
drm/i915: Create
We now have two implementations for vmapping a whole object, one for
dma-buf and one for the ringbuffer. If we couple the vmapping into the
obj->pages lifetime, then we can reuse an obj->vmapping for both and at
the same time couple it into the shrinker.
Signed-off-by: Chris Wilson
---
drivers/g
Since we use obj->active as a hint in many places throughout the code,
knowing its state in debugfs is extremely useful.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c| 56 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 +-
2 files changed, 31 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
ind
Reuse the same reclocking strategy for Baytail as on its bigger brethren,
Sandybridge and Ivybridge. In particular, this makes the device quicker
to reclock (both up and down) though the tendency now is to downclock
more aggressively to compensate for the RPS boosts.
v2: Rebase
v3: Exclude Cherryt
Since we will often pageflip to an active surface, we will often have to
wait for the surface to be written before issuing the flip. Also we are
likely to wait on that surface in plenty of time before the vblank.
Since we have a mechanism for boosting when a flip misses the expected
vblank, curtain
vma are more frequently allocated than objects and so should equally
benefit from having a dedicated slab.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_dma.c | 4
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 7 ++-
drivers/gpu/drm/i91
This is mostly useful for execlists where the rings switch between
contexts (and so checking that the ring's start register matches the
context is important).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++
2 fi
In a few cases, having a direct pointer to the drm_i915_private from the
request is useful.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 11 ---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i9
The hardware is documentated as treating the TAIL register update as
serialising, so we can relax the barriers when filling the rings.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.h| 6 +++---
drivers/gpu/drm/i915/intel_ringbuffer.h | 17 -
2 files chan
Synchronising to an object active on the same ring is a no-op, for the
benefit of execbuffer scheduler. However, for CS flips this means that
we can forgo checking whether the last write request of the object is
actually queued and more importantly whether the cache flush for the
write was emitted.
Fixes regression from
commit 48d823878d64f93163f5a949623346748bbce1b4
Author: Oscar Mateo
Date: Thu Jul 24 17:04:23 2014 +0100
drm/i915/bdw: Generic logical ring init and cleanup
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c| 18 -
drivers/gpu/d
We can use the simpler spinlock form to disable interrupts as we are
always outside of an irq/softirq handler.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/driver
Instead of querying the reset counter before every access to the ring,
query it the first time we touch the ring, and do a final compare when
submitting the request. For correctness, we need to then sanitize how
the reset_counter is incremented to prevent broken submission and
waiting across resets
Not only does it make for good documentation and debugging aide, but it
is also vital for when we want to unwind requests - such as when
throwing away an incomplete request.
v2: Rebase
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 13
drivers/gpu/drm/i91
This provides a nice boost to mesa in swap bound scenarios (as mesa
throttles itself to the previous frame and given the scenario that will
complete shortly). It will also provide a good boost to systems running
with semaphores disabled and so frequently waiting on the GPU as it
switches rings. In
Currently we emit semaphore synchronisation as if we were going to flip
using the target CS engine, but we then change our minds and do the flip
using the CPU. Consequently we write instructions to the ring but never
use them - even to the point of filling that ring up entirely and never
submitting
This trims a little overhead from the common case of not needing to
synchronize between rings.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/dri
At runtime, this helps ensure that the batch pools are kept trim and
fast. Then at suspend, this releases memory that we do not need to
restore. It also ties into the oom-notifier to ensure that we recover as
much kernel memory as possible during OOM.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrt
If we have llc coherency, we can write directly into the ringbuffer
using ordinary cached writes rather than forcing WC access.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 60 +++--
1 file changed, 49 insertions(+), 11 deletions(-)
diff
After the removal of DRI1, all access to the rings are through requests
and so we can always be sure that there is a request to wait upon to
free up available space. The fallback code only existed so that we could
quiesce the GPU following unmediated access by DRI1.
v2: Rebase
Signed-off-by: Chri
The list handling during submission was quite confusing as the retired
requests were out of order - making it much harder in future to reduce
the extra lists. Simplify the submission mechanism to explicitly track
the actual requests current on each port and so trim the amount of work
required to tr
The biggest user of i915_gem_object_get_page() is the relocation
processing during execbuffer. Typically userspace passes in a set of
relocations in sorted order. Sadly, we alternate between relocations
increasing from the start of the buffers, and relocations decreasing
from the end. However the m
Since we blow the TLB caches by using kmap/kunmap, we may as well go the
whole hog and see if declaring our destination page as WC is faster than
keeping it as WB and using clflush. It should be!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 17 +
1 fil
This is just so that I don't have to read about the batch pool on
systems that are not using it! Rather than using a newline between the
kernel clients and userspace clients, just distinguish the internal
allocations with a '[k]'
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.
requests are even more frequently allocated than objects and equally
benefit from having a dedicated slab.
v2: Rebase
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_dma.c | 12 ++
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
drivers/gpu/drm/i915/i915_gem.c
Quite a few of our objects used for internal hardware programming do not
benefit from being swappable or from being zero initialised. As such
they do not benefit from using a shmemfs backing storage and since they
are internal and never directly exposed to the user, we do not need to
worry about pr
We can forgo an evict-everything here in favour of the simpler
i915_gpu_idle() as the shrinker operation itself will unbind any vma as
required. The simplicity allows us to ignore any errors whilst idling
and still force the request retirement to run.
Signed-off-by: Chris Wilson
---
drivers/gpu/
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