On Thu, Jun 25, 2015 at 11:47:22PM +0200, Daniel Vetter wrote:
We can't elide the fb tracking invalidate if the buffer is already in
the right domain since that would lead to missed screen updates. I'm
pretty sure I've written this already before but must have gotten lost
unfortunately :(
On Thu, Jun 25, 2015 at 01:57:16PM -0700, Yu Dai wrote:
On 06/25/2015 07:40 AM, Dave Gordon wrote:
GuC submission is basically execlist submission, but with the GuC
handling the actual writes to the ELSP and the resulting context
switch interrupts. So to prepare a context for submission via
On Thu, Jun 25, 2015 at 04:21:40PM +0100, Damien Lespiau wrote:
The master plan would be to get a bit more stats in it, at least the
standard deviation and confidence interval. Just need the average for
now.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
gtkdoc is missing for this.
On Thu, Jun 25, 2015 at 06:46:06PM +0100, Michel Thierry wrote:
On 6/25/2015 4:35 PM, Mika Kuoppala wrote:
We can have exactly 4GB sized ppgtt with 32bit system.
size_t is inadequate for this.
v2: Convert a lot more places (Daniel)
Looks good to me.
The only possible remaining size_t
We can't elide the fb tracking invalidate if the buffer is already in
the right domain since that would lead to missed screen updates. I'm
pretty sure I've written this already before but must have gotten lost
unfortunately :(
v2: Chris observed that all internal set_domain users already
On Thu, 25 Jun 2015, Shobhit Kumar ku...@shobhit.info wrote:
On Thu, Jun 25, 2015 at 2:18 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
On Mon, Jun 22, 2015 at 04:24:25PM +0530, Shobhit Kumar wrote:
Use the CRC PWM device in intel_panel.c and add new MIPI backlight
specififc
On Thu, Jun 11, 2015 at 09:05:38PM +0300, Mika Kuoppala wrote:
Michel Thierry michel.thie...@intel.com writes:
After Mika's ppgtt cleanup series, all the other free functions have
drm_device as the first parameter, except this one.
No functional changes.
Signed-off-by: Michel
This patch adds support for Skylake display pipe background color.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
Documentation/DocBook/drm.tmpl | 10 -
drivers/gpu/drm/i915/i915_reg.h | 10 +
drivers/gpu/drm/i915/intel_display.c | 73
This patch series allocates minimum dbuf blocks required for tile-y, tile-yf
buffers correctly as per bspec. Also in WM calculations, for 90/270,
swaps source width and height.
Chandra Konduru (2):
drm/i915: Allocate min dbuf blocks per bspec
drm/i915: In DBUF/WM calcs for 90/270, swap w h
Properly allocate min blocks per hw requirements.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
DRRS is a power saving feature, which will refresh the display
at the lowest supported refresh rate, based on the rate of change
of display content to be rendered.
This patch implements the Generic state machine for the Idleness DRRS.
Idleness DRRS is nothing but, when the content of the Display
EDP specific DRRS implementation is removed to implement a
generic DRRS stack extentable accross the supportable encoders.
Signed-off-by: Ramalingam C ramalinga...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 110 -
drivers/gpu/drm/i915/i915_drv.h | 22 --
VBT structure's block 42 is updated as per the current VBT v188
specification and additonal member drrs_min_vrefresh is added.
Corresponding logic for parsing drrs_min_vrefresh is added.
drrs_min_vrefresh is nothing but lowest vrefresh supported by the panel.
Signed-off-by: Ramalingam C
dsi_clk is calculated for the clock of passed drm_display_mode
and pclk is adjusted considering dual link and the burst mode.
This change is required to make the drrs to co-exist with dual link
and Burst mode.
Signed-off-by: Ramalingam C ramalinga...@intel.com
---
This patch Implements the generic DSI DRRS functions and registers
them with Generic DRRS state machine.
Platform specific DSI DRRS functions will be implemented and
registered with this generic DSI DRRS implementation. Hence
extending the DSI DRRS to new platform is made simple.
Signed-off-by:
On 06/24/2015 06:22 PM, Daniel Vetter wrote:
On Wed, Jun 24, 2015 at 04:10:24PM -0300, Danilo Cesar Lemes de Paula wrote:
Functions, Structs and Parameters definitions on kernel documentation
are pure cosmetic, it only highlights the element.
To ease the navigation in the documentation we
On 26/06/15 08:31, Chris Wilson wrote:
On Thu, Jun 25, 2015 at 01:57:16PM -0700, Yu Dai wrote:
On 06/25/2015 07:40 AM, Dave Gordon wrote:
GuC submission is basically execlist submission, but with the GuC
handling the actual writes to the ELSP and the resulting context
switch interrupts. So
On Fri, Jun 26, 2015 at 07:21:45PM +0530, Ramalingam C wrote:
EDP specific DRRS implementation is removed to implement a
generic DRRS stack extentable accross the supportable encoders.
Signed-off-by: Ramalingam C ramalinga...@intel.com
Nack. You don't make something generic by first throwing
On Fri, Jun 26, 2015 at 02:32:03PM +0530, Shobhit Kumar wrote:
Hi,
Next update of the series reviewed at
https://lkml.org/lkml/2015/6/22/155
Major changes are few review comments from Varka and Ville being addressed.
Also except
for intel-gfx patches, all patches reviesion history is
On Fri, Jun 26, 2015 at 05:45:08PM +0100, Dave Gordon wrote:
On 16/06/15 21:38, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:23PM +0100, Arun Siluvery wrote:
+ /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
+ if (IS_BROADWELL(ring-dev)) {
+ struct drm_i915_private
Changed size from u32 to u64 to support +4GB.
48-bit PPGTT test cases may need extra memory available.
v2: Use thousands separator (Chris)
v3: Moved igt_skip_on_simulation() to the start (Chris)
Include Chris' usage hint in the gtk-doc section (Daniel)
Cc: Daniel Vetter
On 16/06/2015 11:39, Abdiel Janulgue wrote:
GEN8 and above uses Execlists by default instead of the legacy
ringbuffer for batch execution. This patch enables the resource
streamer bits when required.
Patch is based on the initial work by Minu Mathai minu.mat...@intel.com
This version also adds
This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 32
1 file changed, 28 insertions(+), 4 deletions(-)
Resending with correct patches.
This patch series allocates minimum dbuf blocks required for tile-y, tile-yf
buffers correctly as per bspec. Also in WM calculations, for 90/270,
swaps source width and height.
Chandra Konduru (2):
drm/i915: Allocate min dbuf blocks per bspec
drm/i915: In
Properly allocate min blocks per hw requirements.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c
This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 32
1 file changed, 28 insertions(+), 4 deletions(-)
Display Refresh Rate Switching (DRRS) is a power conservation feature
which enables swtching between low and high refresh rates,
dynamically, based on the usage scenario to save power.
This feature is applicable for internal panels.
Indication that the panel supports DRRS is given by the panel
If DSI panel has the downclock mode supported, add that in the
connector's mode list.
This is needed by userspace apps to identify the range of vrefresh
rates supported by panel incase of the media playback DRRS.
Signed-off-by: Ramalingam C ramalinga...@intel.com
---
Based on the minimum requirement of the vrefresh to support a
content's playback, we can place a drrs request from userspace
to kernel. For example 24FPS video content can be played at
48 vrefresh without any quality degradation.
This patch implements required changes in generic DRRS state
DRRS capability on each connector is exposed to userspace through
drm connector property.
In this change one drm property is created and attached with each
connector. And when DRRS is successfully initialized for a connector,
drrs connector property is set with appropriate value.
Signed-off-by:
Michel Thierry michel.thie...@intel.com writes:
A safer way to update the PDPx registers is sending lri commands, added
in the ring before the batchbuffer start. Otherwise, the ctx must be idle
before trying to change anything (but the ring-tail) in the ctx image. An
example where the ctx
On 24/06/15 11:04, Chris Wilson wrote:
On Tue, Jun 23, 2015 at 07:45:42AM +0200, Sedat Dilek wrote:
I have seen this typo once and added an entry to codespell's dictionary.txt
file.
$ diff -uprN /usr/share/codespell/dictionary.txt.orig
/usr/share/codespell/dictionary.txt
---
Functions, Structs and Parameters definitions on kernel documentation
are pure cosmetic, it only highlights the element.
To ease the navigation in the documentation we should use links inside
those tags so readers can easily jump between methods directly.
This was discussed in 2014[1] and is
VLV related dsi drrs functions are implemented and registered
with generic dsi drrs.
This will provide the service to generic dsi drrs stack to calculate
the pll divider values and program the pll registers for DRRS
functionality.
Signed-off-by: Ramalingam C ramalinga...@intel.com
---
VLV related ePD drrs functions are implemented and registered
with generic eDP drrs module.
This will provide the platform specific services to generic ePD drrs
stack, like program the pll registers for DRRS functionality.
Signed-off-by: Ramalingam C ramalinga...@intel.com
---
For all the connectors drrs init is invoked. drrs_init will
initialize the drrs for those connectors that support DRRS.
Signed-off-by: Ramalingam C ramalinga...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |5 +
1 file changed, 5 insertions(+)
diff --git
If crtc is in clone mode, DRRS will be disabled. Because if the both
the displays are not sharing the same vrefresh, then userspace
activities based on vsync will go for toss.
Clone mode will be rechecked on every restarting Idleness DRRS events.
Signed-off-by: Ramalingam C
During the DRRS state transitions we are modifying the clock and
hence the vrefresh rate.
So we need to update the drm_crtc-mode and the adjusted
mode in intel_crtc. So that watermark calculations will be as per the
new modified clock.
Signed-off-by: Ramalingam C ramalinga...@intel.com
---
This patch Implements the generic eDP DRRS functions and registers
them with Generic DRRS state machine.
Platform specific eDP DRRS functions will be implemented and
registered with this generic eDP DRRS implementation. Hence
extending the eDP DRRS to new platform is made simple.
Signed-off-by:
If the platform supports the media playback DRRS, Userspace can provide
a request for Media playback DRRS. This is done by placing the modeset
request with the same mode and FB but with different vrefresh.
This change implements the algorithm to identify the Media playback
DRRS requests from the
Content based DRRS support is implemented in
DSI DRRS module also.
Signed-off-by: Ramalingam C ramalinga...@intel.com
---
drivers/gpu/drm/i915/intel_dsi_drrs.c | 60 +++--
1 file changed, 58 insertions(+), 2 deletions(-)
diff --git
Content based DRRS support is implemented in
eDP DRRS module also.
Signed-off-by: Ramalingam C ramalinga...@intel.com
---
drivers/gpu/drm/i915/intel_drv.h |3 +++
drivers/gpu/drm/i915/intel_edp_drrs.c | 29 +
2 files changed, 32 insertions(+)
diff --git
This will enable the called to decide the combination of divider
values that needs to be programmed.
First divider value will go into primary divider and the second divider
value will be taken for drrs divider register, if that is supported
on platform.
Signed-off-by: Ramalingam C
On 23/06/15 13:21, Michel Thierry wrote:
Gen8+ supports 48-bit virtual addresses, but some objects must always be
allocated inside the 32-bit address range.
In specific, any resource used with flat/heapless (0x-0xf000)
General State Heap (GSH) or Intruction State Heap (ISH) must
On Fri, Jun 26, 2015 at 06:28:39PM +0300, Ander Conselvan De Oliveira wrote:
Hi all,
I've been looking into creating custom fields in Bugzilla to help sort
our bugs in a more manageable way. I did some testing in a private
installation and came up with this proposal. In a nut shell, we would
On 22 June 2015 at 14:02, Daniel Vetter daniel.vet...@ffwll.ch wrote:
We should never nest these since in theory kms drivers should know
when a pipe is on/off and call the corresponding enable/disable
functions for the vblank helper code only once. But for historical
reasons (the
On Fri, Jun 26, 2015 at 07:08:40PM +0200, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:53PM +0530, Ramalingam C wrote:
If crtc is in clone mode, DRRS will be disabled. Because if the both
the displays are not sharing the same vrefresh, then userspace
activities based on vsync will go
On Fri, Jun 26, 2015 at 06:23:39PM +0100, Chris Wilson wrote:
On Fri, Jun 26, 2015 at 07:05:20PM +0200, Daniel Vetter wrote:
Maybe we need a bit more polish, but probably not worth it to spend too
much time on the exact feature list. If we spot serious gaps we can always
add more. And
We can't elide the fb tracking invalidate if the buffer is already in
the right domain since that would lead to missed screen updates. I'm
pretty sure I've written this already before but must have gotten lost
unfortunately :(
v2: Chris observed that all internal set_domain users already
On 25/06/15 18:51, Chris Wilson wrote:
On Thu, Jun 25, 2015 at 06:35:14PM +0300, Mika Kuoppala wrote:
During review of dynamic page tables series, I was able
to hit a lite restore bug with execlists. I assume that
due to incorrect pd, the batch run out of legit address space
and into the
On Fri, Jun 26, 2015 at 06:14:07PM +0100, Chris Wilson wrote:
On Fri, Jun 26, 2015 at 07:08:40PM +0200, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 07:21:53PM +0530, Ramalingam C wrote:
If crtc is in clone mode, DRRS will be disabled. Because if the both
the displays are not sharing the
On Fri, Jun 26, 2015 at 02:08:30PM -0300, Paulo Zanoni wrote:
2015-06-25 12:19 GMT-03:00 Damien Lespiau damien.lesp...@intel.com:
Currently, if an odd divider improves the deviation (minimizes it), we
take that divider. The recommendation is to prefer even dividers.
v2: Move the check at
On Fri, Jun 26, 2015 at 07:35:16PM +0200, Daniel Vetter wrote:
We can't elide the fb tracking invalidate if the buffer is already in
the right domain since that would lead to missed screen updates. I'm
pretty sure I've written this already before but must have gotten lost
unfortunately :(
On Fri, Jun 26, 2015 at 06:53:49AM -0700, Chandra Konduru wrote:
This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.
Signed-off-by: Chandra Konduru chandra.kond...@intel.com
Do we have an igt which provokes underruns and hence can
On Fri, Jun 26, 2015 at 06:34:29PM +0100, Damien Lespiau wrote:
We can't improve a 0 deviation, so when we find such a divider, skip the
remaining ones they won't be better.
This short-circuit the search for 34 of the 373 test frequencies in the
corresponding i-g-t test
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Turns out the VLV/CHV system agent doesn't understand memory
latencies, so trying to rely on the PND deadline mechanism is not
going to fly especially when DDR DVFS is enabled.
On 26/06/2015 14:34, Chris Wilson wrote:
On Fri, Jun 26, 2015 at 01:58:11PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The intended usage model for struct fence is that the signalled status should be
set on demand rather than polled. That is, there
On Fri, Jun 26, 2015 at 07:21:53PM +0530, Ramalingam C wrote:
If crtc is in clone mode, DRRS will be disabled. Because if the both
the displays are not sharing the same vrefresh, then userspace
activities based on vsync will go for toss.
Clone mode will be rechecked on every restarting
2015-06-25 12:15 GMT-03:00 Damien Lespiau damien.lesp...@intel.com:
The HW validation team came back from further testing with a slightly
changed constraint on the deviation between the DCO frequency and the
central frequency. Instead of +-4%, it's now +1%/-6%.
Unfortunately, the previous
On Fri, Jun 26, 2015 at 06:31:37PM +0200, Daniel Vetter wrote:
On Fri, Jun 26, 2015 at 02:32:03PM +0530, Shobhit Kumar wrote:
Hi,
Next update of the series reviewed at
https://lkml.org/lkml/2015/6/22/155
Major changes are few review comments from Varka and Ville being addressed.
Hi Shashank,
I have been working on support for colorspace handling for V4L2 (video capture),
basically the flip-side of the coin that you are working on.
While both the V4L2 and DRM/KMS APIs are completely different, the part that
does
the matrix calculations can be shared between the two. I
2015-06-25 12:19 GMT-03:00 Damien Lespiau damien.lesp...@intel.com:
Currently, if an odd divider improves the deviation (minimizes it), we
take that divider. The recommendation is to prefer even dividers.
v2: Move the check at the right place after having inverted the two for
loops in the
On Fri, Jun 26, 2015 at 07:21:54PM +0530, Ramalingam C wrote:
For all the connectors drrs init is invoked. drrs_init will
initialize the drrs for those connectors that support DRRS.
Signed-off-by: Ramalingam C ramalinga...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |5 +
1
On Fri, Jun 26, 2015 at 07:21:55PM +0530, Ramalingam C wrote:
During the DRRS state transitions we are modifying the clock and
hence the vrefresh rate.
So we need to update the drm_crtc-mode and the adjusted
mode in intel_crtc. So that watermark calculations will be as per the
new modified
On Fri, Jun 26, 2015 at 07:21:44PM +0530, Ramalingam C wrote:
Display Refresh Rate Switching (DRRS) is a power conservation feature
which enables swtching between low and high refresh rates,
dynamically, based on the usage scenario to save power.
This feature is applicable for internal
On Fri, Jun 26, 2015 at 06:00:03PM +0100, John Harrison wrote:
On 26/06/2015 14:34, Chris Wilson wrote:
On Fri, Jun 26, 2015 at 01:58:11PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
The intended usage model for struct fence is that the signalled
On Fri, Jun 26, 2015 at 02:18:39PM -0300, Paulo Zanoni wrote:
@@ -1311,13 +1320,15 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
unsigned int p = dividers[d].list[i];
uint64_t dco_freq = p * afe_clock;
-
On Fri, Jun 26, 2015 at 07:05:20PM +0200, Daniel Vetter wrote:
Maybe we need a bit more polish, but probably not worth it to spend too
much time on the exact feature list. If we spot serious gaps we can always
add more. And remove old ones which have gone out of favour (having that
script
On Fri, 2015-06-26 at 11:50 +0100, Kaskinen, Tanu wrote:
On Tue, 2015-06-23 at 10:51 +0300, Tanu Kaskinen wrote:
(Added pulseaudio-discuss to CC.)
On Mon, 2015-06-22 at 17:44 +0200, Takashi Iwai wrote:
At Mon, 22 Jun 2015 15:21:16 +,
Kaskinen, Tanu wrote:
On Mon,
2015-06-25 14:08 GMT-03:00 Damien Lespiau damien.lesp...@intel.com:
We can't improve a 0 deviation, so when we find such a divider, skip the
remaining ones they won't be better.
This short-circuit the search for 34 of the 373 test frequencies in the
corresponding i-g-t test
We can't improve a 0 deviation, so when we find such a divider, skip the
remaining ones they won't be better.
This short-circuit the search for 34 of the 373 test frequencies in the
corresponding i-g-t test (tools/skl_compute_wrpll)
v2: Place the short-circuiting code in skl_compute_wrpll()
On 25/06/15 19:38, Tomas Elf wrote:
On 24/06/2015 18:03, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
An earlier patch was added to reserve space in the ring buffer for the
commands issued during 'add_request()'. The initial version was
pessimistic in the
On Thu, Jun 25, 2015 at 12:17 PM, Ben Widawsky b...@bwidawsk.net wrote:
On Thu, Jun 25, 2015 at 07:11:21PM +0100, Chris Wilson wrote:
On Thu, Jun 25, 2015 at 11:01:44AM -0700, Ben Widawsky wrote:
On Wed, Jun 24, 2015 at 08:28:13AM +0100, Chris Wilson wrote:
On Tue, Jun 23, 2015 at
We cannot let IPS enabled with no plane on the pipe:
BSpec: IPS cannot be enabled until after at least one plane has
been enabled for at least one vertical blank. and IPS must be
disabled while there is still at least one plane enabled on the
same pipe as IPS. This restriction apply to HSW and
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Consider which planes are active and compute the FIFO split based on the
relative data rates. Since we only consider the pipe src width rather
than the plane width when computing
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Allow tweaking the VLV/CHV memory latencies thorugh sysfs, like we do
for ILK+.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c |
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
CxSR (or maxfifo on VLV/CHV) blocks somne changes to the plane control
register (enable bit at least, not quite sure about the rest). So in
order to have the plane enable/disable when
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
In order to get decnet memory self refresh residency on VLV, flip it
over to the new CHV way of doing things. VLV doesn't do PM5 or DDR DVFS
so it's a bit simpler.
I'm not sure the
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Enabling PM5/DDR DVFS with multiple active pipes isn't a validated
configuration. It does seem to work most of the time at least, but
there is clearly an additional risk of underruns,
On Mon, 2015-06-22 at 17:44 +0200, Takashi Iwai wrote:
At Mon, 22 Jun 2015 15:21:16 +,
Kaskinen, Tanu wrote:
PulseAudio (mostly) doesn't use the hw:X devices directly. Instead, it
uses logical names like front, hdmi, iec958, etc. Speaking of HDMI
specifically, PulseAudio uses devices
On Fri, Jun 26, 2015 at 03:05:29PM +0300, Mika Kuoppala wrote:
Daniel Vetter dan...@ffwll.ch writes:
On Thu, Jun 25, 2015 at 06:35:18PM +0300, Mika Kuoppala wrote:
+static int setup_scratch(struct i915_address_space *vm)
+{
+ struct i915_address_space *ggtt_vm =
On 16/06/15 21:38, Chris Wilson wrote:
On Tue, Jun 16, 2015 at 08:25:23PM +0100, Arun Siluvery wrote:
+/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
+if (IS_BROADWELL(ring-dev)) {
+struct drm_i915_private *dev_priv = ring-dev-dev_private;
dev_priv =
On Thu, Jun 25, 2015 at 6:00 PM, Dave Airlie airl...@linux.ie wrote:
This is the main drm pull request for v4.2.
It seems to work ok for me, but it causes quite a few new warnings on
my Sony VAIO Pro laptop. It's (once more) a regular i5-4200U CPU (aka
Haswell, aka 4th gen Intel Core i5)
Most
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
The hardware supposedly ignores the WM1 watermarks while the PND
deadline mode is enabled, but clear out the register just in case.
This is what the other OS does, and it does make
2015-06-26 14:35 GMT-03:00 Chris Wilson ch...@chris-wilson.co.uk:
On Fri, Jun 26, 2015 at 07:35:16PM +0200, Daniel Vetter wrote:
We can't elide the fb tracking invalidate if the buffer is already in
the right domain since that would lead to missed screen updates. I'm
pretty sure I've written
On Fri, Jun 26, 2015 at 10:56:33AM -0700, Clint Taylor wrote:
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Turns out the VLV/CHV system agent doesn't understand memory
latencies, so trying to rely on the PND deadline
On 06/26/2015 12:48 PM, Ville Syrjälä wrote:
On Fri, Jun 26, 2015 at 10:56:33AM -0700, Clint Taylor wrote:
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Turns out the VLV/CHV system agent doesn't understand memory
latencies, so
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Read out the current watermark settings from the hardware at driver init
time. This will allow us to compare the newly calculated values against
the currrent ones and potentially avoid
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Try to update the watermarks on the right side of the plane update. This
is just a temporary hack until we get the proper two part update into
place. However in the meantime this might
On 06/24/2015 12:00 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We want cxsr exit to happen ASAP, so toss in some POSTING_READ()s to
make sure things are really kicked off.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
On Fri, Jun 26, 2015 at 10:15:08AM +0200, Daniel Vetter wrote:
We can't elide the fb tracking invalidate if the buffer is already in
the right domain since that would lead to missed screen updates. I'm
pretty sure I've written this already before but must have gotten lost
unfortunately :(
On Fri, Jun 26, 2015 at 12:26:56AM +0100, Damien Lespiau wrote:
Sure, it'll be freed at exit(), but might as well be a bit pedantic.
s/pedantic/pedagological/
Tests also serve as examples and will undoubtably be copy-pasted at some
point.
-Chris
--
Chris Wilson, Intel Open Source Technology
On Thu, 2015-06-25 at 10:44 +0100, Liam Girdwood wrote:
On Wed, 2015-06-24 at 20:47 +, Kaskinen, Tanu wrote:
On Wed, 2015-06-24 at 14:06 +0100, Liam Girdwood wrote:
On Wed, 2015-06-24 at 12:41 +, Kaskinen, Tanu wrote:
On Tue, 2015-06-23 at 10:06 +0200, Takashi Iwai wrote:
At
Use the CRC PWM device in intel_panel.c and add new MIPI backlight
specififc callbacks
v2: Modify to use pwm_config callback
v3: Addressed Jani's comments
- Renamed all function as pwm_* instead of vlv_*
- Call intel_panel_actually_set_backlight in enable function
- Return -ENODEV in
On some BYT PLatform the PWM is controlled using CRC PMIC. Add a lookup
entry for the same to be used by the consumer (Intel GFX)
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
On Thu, Jun 25, 2015 at 06:35:17PM +0300, Mika Kuoppala wrote:
Scratch page is part of struct i915_address_space. Move other
scratch entities into the same struct. This is a preparatory patch
for having only one instance of each scratch_pt/pd.
v2: make commit msg more readable
Hi,
Next update of the series reviewed at
https://lkml.org/lkml/2015/6/22/155
Major changes are few review comments from Varka and Ville being addressed.
Also except
for intel-gfx patches, all patches reviesion history is moved out of commit
message.
Hope this series finally finds its mark.
Needed for PWM control suuported by the PMIC
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot gnu...@gmail.com
Cc: Thierry Reding thierry.red...@gmail.com
Acked-by: Lee Jones lee.jo...@linaro.org
Tested-by: Ville Syrjälä
In case we unload and load a driver module again that is registering a
lookup table, without this it will result in multiple entries. Provide
an option to remove the lookup table on driver unload
Cc: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre
On some Intel SoC platforms, the panel enable/disable signals are
controlled by CRC PMIC. Add those control as a new GPIO in a lookup
table for gpio-crystalcove chip during CRC driver load
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre Courbot
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