Re: [Intel-gfx] Request Linux Graphic Driver for Intel GMA 3150

OK, thank you for your help. Regards, David -Original Message- From: Vivi, Rodrigo [mailto:rodrigo.v...@intel.com] Sent: 04 September 2015 23:06 To: matts...@gmail.com; rodrigo.v...@gmail.com; hupernikao...@gmail.com Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] Request L

[Intel-gfx] [PATCH i-g-t 2/2] Adding kms_nv12 to test display NV12 feature

From: chandra konduru This patch adds kms_nv12 test case. It covers testing NV12 in linear/tile-X/tile-Y tiling formats in 0/90/180/270 orientations. For each tiling format, it tests several combinations of planes and its scaling. v2: -Added 90/270 tests (me) -took out crc test as it isn't addin

[Intel-gfx] [PATCH 11/15] drm/i915: Add NV12 to sprite plane programming.

This patch is adding NV12 support to skylake sprite plane programming. It is covering linear/X/Y/Yf tiling formats for 0 and 180 rotations. For 90/270 rotation, Y and UV subplanes should be treated as separate surfaces and GTT remapping for rotation should be done separately for each subplane. Onc

[Intel-gfx] [PATCH 13/15] drm/i915: skl nv12 wa - disable streamer fix

When the plane source pixel format is NV12, the CHICKEN_PIPESL register bit 22 must be set to 1 v2: -one wa per commit with comments, and function headers (Daniel) v3: -moved intel stepping helper functions to i915_drv.c (Daniel) Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/i915_drv

[Intel-gfx] [PATCH 14/15] drm/i915: skl nv12 wa - NV12 to RGB switch

Switching format from NV12 to RGB can result in display underrun and corruption. This workaround sets bits 15 & 19 to 1 in CLKGATE_DIS_PSL register to address transition underrun. Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/i915_reg.h |8 drivers/gpu/drm/i915/intel_

[Intel-gfx] [PATCH 10/15] drm/i915: Add NV12 to primary plane programming.

This patch is adding NV12 support to skylake primary plane programming. It is covering linear/X/Y/Yf tiling formats for 0 and 180 rotations. For 90/270 rotation, Y and UV subplanes should be treated as separate surfaces and GTT remapping for rotation should be done separately for each subplane. On

[Intel-gfx] [PATCH 07/15] drm/i915: Add NV12 as supported format for primary plane

This patch adds NV12 to list of supported formats for primary plane. v2: -Rebased (me) Signed-off-by: Chandra Konduru Testcase: igt/kms_nv12 --- drivers/gpu/drm/i915/intel_display.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i91

[Intel-gfx] [PATCH 05/15] drm/i915: Update format_is_yuv() to include NV12

This patch adds NV12 to format_is_yuv() function and made it available for both primary and sprite planes. v2: -Use intel_ prefix for format_is_yuv (Ville) Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/intel_drv.h|1 + drivers/gpu/drm/i915/intel_sprite.c |9 + 2 fi

[Intel-gfx] [PATCH 15/15] drm/i915: Add 90/270 rotation for NV12 format.

Adding NV12 90/270 rotation support for primary and sprite planes. v2: -For 90/270 adjust pixel boundary only in Y-direction (bspec) v3: -Rebased (me) Signed-off-by: Chandra Konduru Testcase: igt/kms_nv12 --- drivers/gpu/drm/i915/intel_display.c | 46 +++- drivers/gpu

[Intel-gfx] [PATCH 12/15] drm/i915: Set initial phase & trip for NV12 scaler

This patch sets default initial phase and trip to scale NV12 content. In future, if needed these can be set via properties or other means depending on incoming stream request. Until then defaults are fine. Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/intel_display.c |7 +++ dr

[Intel-gfx] [PATCH 04/15] drm/i915: Stage scaler request for NV12 as src format

This patch stages a scaler request when input format is NV12. The same scaler does both chroma-upsampling and resolution scaling as needed. v2: -Added helper function for need_scaling (Ville) v3: -Rebased to current kernel version 4.2.0.rc4 (me) v4: -minor updates (Ville) Signed-off-by: Chandra

[Intel-gfx] [PATCH 03/15] drm/i915: Set scaler mode for NV12

This patch sets appropriate scaler mode for NV12 format. In this mode, skylake scaler does either chroma-upsampling or chroma-upsampling and resolution scaling. v2: - new reg defines squashed into patches used them (Ville) Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/i915_reg.h |

[Intel-gfx] [PATCH 06/15] drm/i915: Upscale scaler max scale for NV12.

This patch updates max supported scaler limits for NV12. v2: -Rebased to current kernel version 4.2.0.rc4 (me) v3: -simplified max_scale calculation (Ville) Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/intel_display.c | 17 + drivers/gpu/drm/i915/intel_drv.h |

[Intel-gfx] [PATCH 02/15] drm/i915: In DBUF/WM calcs for 90/270, swap w & h

This patch swaps src width and height for dbuf/wm calculations when rotation is 90/270 as per hw requirements. v2: - minor/cosmetic changes, removed plane_state check kludge (Ville) Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/intel_pm.c | 28 1 file ch

[Intel-gfx] [PATCH 08/15] drm/i915: Add NV12 as supported format for sprite plane

This patch adds NV12 to list of supported formats for sprite plane. v2: - made supported format list const, fixed a leftover -1. (Ville) Signed-off-by: Chandra Konduru Testcase: igt/kms_nv12 --- drivers/gpu/drm/i915/intel_sprite.c | 25 ++--- 1 file changed, 22 insertions(

[Intel-gfx] [PATCH 09/15] drm/i915: Add NV12 support to intel_framebuffer_init

This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (me) v3: -cosmetic update, split checks into two (Ville) Signed-off-by: Chandra Konduru Testcase: igt/kms_nv12 --- drivers/gpu/drm/i915/intel_display.c | 33 +

[Intel-gfx] [PATCH 00/15] drm/i915: Adding NV12 for skylake display

This patch series is adding initial NV12 support for Skylake display after rebasing on latest drm-intel-nightly. Earlier I had two patch series one for 0/180 and another for 90/270. Some of the patches were already merged. This is combined series to support 0/90/180/270 and removing the ones that a

[Intel-gfx] [PATCH 01/15] drm/i915: Allocate min dbuf blocks per bspec

Properly allocate min blocks per hw requirements. v2: - changed helper functional param to bool, some code simplification (Ville) Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/intel_pm.c | 29 +++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git

Re: [Intel-gfx] [PATCH 14/15] drm/i915: skl nv12 workarounds

> > > On Thu, Aug 27, 2015 at 01:44:06AM +, Konduru, Chandra wrote: > > > > > > -static char intel_get_stepping(struct drm_device *dev) > > > > > > +char intel_get_stepping(struct drm_device *dev) > > > > > > > > > > I guess we should have a new home for this now that it's used outside > > > >

Re: [Intel-gfx] [PATCH 15/15] drm/i915: Add 90/270 rotation for NV12 format.

> > /* Adjust (macro)pixel boundary */ > > if (fb && intel_format_is_yuv(fb->pixel_format)) { > > - to_intel_plane_state(plane_state)->src.x1 &= ~0x1; > > - to_intel_plane_state(plane_state)->src.x2 &= ~0x1; > > + if (intel_rotation_90_or_270(plane_stat

Re: [Intel-gfx] [PATCH 14/15] drm/i915: skl nv12 workarounds

> > + > > + if (((IS_SKYLAKE(dev) && intel_get_stepping(dev) == 'C') || > > + (IS_BROXTON(dev) && intel_get_stepping(dev) == 'A')) && > > + fb->pixel_format == DRM_FORMAT_NV12) { > > + I915_WRITE(CHICKEN_PIPESL(pipe), > > + I915_READ

Re: [Intel-gfx] [PATCH 11/15] drm/i915: Add NV12 to primary plane programming.

> > + > > + if (fb->pixel_format == DRM_FORMAT_NV12) { > > + int height_in_mem = (fb->offsets[1]/fb->pitches[0]); > > + /* > > +* If UV starts from middle of a page, then UV start > should > > +* be programmed to

Re: [Intel-gfx] [PATCH v2 3/3] drm/i915: don't hard code vlv backlight frequency if unset

On 09/04/2015 06:55 AM, Jani Nikula wrote: Fall back to VBT based backlight modulation frequency if it's not set. Do not hard code. This could be a problem if there is no VBT. Cc: Clint Taylor Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_panel.c | 13 - 1 file chan

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: initialize backlight max from VBT

On 09/04/2015 06:55 AM, Jani Nikula wrote: Normally we determine the backlight PWM modulation frequency (which we also use as backlight max value) from the backlight registers at module load time, expecting the registers have been initialized by the BIOS. If this is not the case, we fail. The VB

Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: use pch backlight override on hsw too

On 09/04/2015 06:55 AM, Jani Nikula wrote: Currently the difference between backlight control on HSW vs. BDW/SKL is that on HSW we modify the duty cycle on the CPU register, and have the hardware pass the changes on to the PCH registers. We still drive the PCH PWM on both. While HSW and BDW use t

[Intel-gfx] [PATCH v1] drm/i915: Add GuC css header parser

From: Alex Dai By using information from GuC css header, we can eliminate some hard code w.r.t size of some components of firmware. v1: 1) guc_css_header is defined as __packed now 2) Add and correct GuC related topics in kernel/Doc Signed-off-by: Alex Dai --- Documentation/DocBook/drm.tm

Re: [Intel-gfx] [PATCH] scripts/kernel-doc: Improve Markdown results

On Fri, 4 Sep 2015 14:53:34 -0300 Danilo Cesar Lemes de Paula wrote: > In the last few days I sent three features: > Markdown support (patch series 1) > Cross-reference hyperlink support (patch series 1) > in-struct-body documentation (series 2) > > I assume you want a new patch series for the s

[Intel-gfx] [RFC] drm/i915: Render decompression support for Gen9 and above

This patch includes enabling render decompression after checking all the requirements (format, tiling, rotation etc.). Along with this, the WAs mentioned in BSpec Workaround page have been implemented. This patch has been implemented on top of Nabendu/Chandra's NV12 patches. TODO: 1. Disable ster

Re: [Intel-gfx] [PATCH 9/9] drm/i915: add bufferless execbuf ioctl

On 09/04/2015 10:37 AM, Chris Wilson wrote: > On Fri, Sep 04, 2015 at 09:59:03AM -0700, Jesse Barnes wrote: >> We just need to pass in an address to execute and some flags, since we >> don't have to worry about buffer relocation or any of the other usual >> stuff. Returns a fence to be used for sy

Re: [Intel-gfx] [RFC] Page table sharing and bufferless execbuf

On 09/04/2015 10:23 AM, Chris Wilson wrote: > On Fri, Sep 04, 2015 at 09:58:54AM -0700, Jesse Barnes wrote: >> A few things to think about: >> - how to signal GPU hangs with the new execbuf (a signal might be more >> natural as the execution appears more CPU-like? what state do we >> hav

[Intel-gfx] [PATCH 1/3] lib: update kmstest_get_pipe_from_crtc_id

This function uses an intel-specific ioctl to fetch a mapping between pipes and crtc ids, but this technique is outdated as the crtc id is now always equivalent to its index in the array of crtcs returned by the kernel. --- lib/igt_kms.c | 33 - 1 file changed, 24

[Intel-gfx] [PATCH 0/3] remove crtc<->pipe mapping code

This patchset removes the code that looks up a pipe number from a crtc ID. The pipe number is equivalent to the index of the crtc in the array of crtcs returned by the kernel for a drmModeGetResources() call. This may not have been the case when these lookups were written, but it is the de facto

[Intel-gfx] [PATCH 3/3] overlay: remove crtc<->pipe mapping code from kms-overlay

the crtc id is now always equivalent to its index in the array of crtcs returned by the kernel --- overlay/Makefile.am | 4 ++-- overlay/kms/kms-overlay.c | 7 ++- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/overlay/Makefile.am b/overlay/Makefile.am index c648875..c82

[Intel-gfx] [PATCH 2/3] tests/drm_read: remove manual crtc<->pipe mapping from drm_read test

the crtc id is now always equivalent to its index in the array of crtcs returned by the kernel --- tests/drm_read.c | 43 +-- 1 file changed, 13 insertions(+), 30 deletions(-) diff --git a/tests/drm_read.c b/tests/drm_read.c index b808bed..ab7e4ef 100644 -

Re: [Intel-gfx] [PATCH] scripts/kernel-doc: Improve Markdown results

On 09/02/2015 11:15 AM, Jonathan Corbet wrote: > On Tue, 1 Sep 2015 14:57:33 -0300 > Danilo Cesar Lemes de Paula wrote: > >> Did you find time to check this patch? As you mentioned that you applied >> the Markdown support for the linux-next tree, this patch might be needed >> (maybe "wanted" is a

Re: [Intel-gfx] [PATCH 9/9] drm/i915: add bufferless execbuf ioctl

On Fri, Sep 04, 2015 at 09:59:03AM -0700, Jesse Barnes wrote: > We just need to pass in an address to execute and some flags, since we > don't have to worry about buffer relocation or any of the other usual > stuff. Returns a fence to be used for synchronization. There is no need for a flush+fenc

Re: [Intel-gfx] [RFC] Page table sharing and bufferless execbuf

On Fri, Sep 04, 2015 at 09:58:54AM -0700, Jesse Barnes wrote: > A few things to think about: > - how to signal GPU hangs with the new execbuf (a signal might be more > natural as the execution appears more CPU-like? what state do we > have to worry about restoring for bufferless contexts

[Intel-gfx] [PATCH 2/9] signal: export force_sig_info

For signaling tasks from drivers. --- kernel/signal.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/signal.c b/kernel/signal.c index 0f6bbbe..9122aa2 100644 --- a/kernel/signal.c +++ b/kernel/signal.c @@ -1227,6 +1227,7 @@ force_sig_info(int sig, struct siginfo *info, struct task_str

[Intel-gfx] [PATCH 8/9] drm/i915: Android sync points for i915 v4 (obsolete)

Allow for sync point exposure in the i915 driver. This There are a couple of goals here: 1) allow applications and libraries to create fences without an associated buffer 2) re-use a common API so userspace doesn't have to impedance mismatch between different driver implementations

[Intel-gfx] [PATCH 4/9] android/sync: hack: enable fence signaling in Android Native Sync implementation

--- drivers/staging/android/sync.c | 29 + 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/staging/android/sync.c b/drivers/staging/android/sync.c index 7f0e919..858278d 100644 --- a/drivers/staging/android/sync.c +++ b/drivers/staging/android/sy

[Intel-gfx] [PATCH 6/9] drm/i915: driver based PASID handling

New file with VT-d SVM and PASID handling functions and page table management. This belongs in the IOMMU code (along with some extra bits for waiting for invalidations and page faults to complete, flushing the device IOTLB, etc.) FIXME: need work queue for re-submitting contexts TE bit handli

[Intel-gfx] [PATCH 3/9] android/sync: add sync_fence_create_dma

From: Maarten Lankhorst This allows users of dma fences to create a android fence. Cc: Daniel Vetter Cc: Jesse Barnes Signed-off-by: Maarten Lankhorst --- drivers/staging/android/sync.c | 13 + drivers/staging/android/sync.h | 3 ++- 2 files changed, 11 insertions(+), 5 deletion

[Intel-gfx] [PATCH 1/9] mm: move mmu_find_ops to mmu_notifier.c

For use by other modules. Signed-off-by: Jesse Barnes --- drivers/misc/sgi-gru/grutlbpurge.c | 19 --- include/linux/mmu_notifier.h | 8 mm/mmu_notifier.c | 19 +++ 3 files changed, 27 insertions(+), 19 deletions(-) diff --git a/d

[Intel-gfx] [PATCH 7/9] drm/i915: add fences to the request struct

This simplifies the sync code quite a bit. I don't think we'll be able to get away with using the core fence code's seqno support, since we'll be moving away from simple seqno comparisions with the scheduler and preemption, but the additional code is pretty minimal anyway, and lets us add addition

[Intel-gfx] [RFC] Page table sharing and bufferless execbuf

I've been carrying something looking rougly like this patchset around internally for a long time now, and with SKL out there now, I figured it's time to get it posted and start the process of integration. David is working on pulling over most of the "driver based PASID handling" and other code int

[Intel-gfx] [PATCH 9/9] drm/i915: add bufferless execbuf ioctl

We just need to pass in an address to execute and some flags, since we don't have to worry about buffer relocation or any of the other usual stuff. Returns a fence to be used for synchronization. --- drivers/gpu/drm/i915/i915_dma.c| 140 - drivers/gpu/drm/i

[Intel-gfx] [PATCH 5/9] drm/i915: add create_context2 ioctl

For passing flags (e.g. SVM) when creating a context. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_dma.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem_context.c | 63 +++-- include/uapi/drm/i915_drm.h

Re: [Intel-gfx] [PATCH 2/2] drm/i915/lrc: Prevent preemption when lite-restore is disabled

On 04/09/15 12:59, Michel Thierry wrote: When WaEnableForceRestoreInCtxtDescForVCS is required, it is only safe to send new contexts if the last reported event is "active to idle". Otherwise the same context can fully preempt itself because lite-restore is disabled. Testcase: igt/gem_concurrent_

Re: [Intel-gfx] Request Linux Graphic Driver for Intel GMA 3150

On Fri, 2015-09-04 at 21:41 +0700, David Ho wrote: > Hello Rodrigo/Matt, > > Running: > lspci -ns :00:02.0 | awk -F: '{ print $4 }' > > returns: > a001 (rev 02) Yes, it is supported. Definitely a Pineview. > > I’m not very familiar with “build”. SO it is probably not recommended option

[Intel-gfx] [PATCH i-g-t v2] tools: install the register definition files

Install the register definition files and use them by default in intel_reg. v2: remove redundant path check Suggested-by: Jani Nikula Signed-off-by: Thomas Wood --- configure.ac| 5 +++-- tools/Makefile.am | 2 +- tools/intel_reg.c | 4 ++-- tools/registers/

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Reduce frequency of unspecific HSW reg debugging

On Fri, Sep 04, 2015 at 06:16:19PM +0300, Ville Syrjälä wrote: > On Fri, Sep 04, 2015 at 04:53:28PM +0200, Daniel Vetter wrote: > > On Fri, Sep 04, 2015 at 03:18:14PM +0300, Mika Kuoppala wrote: > > > Mika Kuoppala writes: > > > > > > > Daniel Vetter writes: > > > > > > > >> On Fri, Sep 04, 2015

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Reduce frequency of unspecific HSW reg debugging

On Fri, Sep 04, 2015 at 06:16:19PM +0300, Ville Syrjälä wrote: > On Fri, Sep 04, 2015 at 04:53:28PM +0200, Daniel Vetter wrote: > > On Fri, Sep 04, 2015 at 03:18:14PM +0300, Mika Kuoppala wrote: > > > Mika Kuoppala writes: > > > > > > > Daniel Vetter writes: > > > > > > > >> On Fri, Sep 04, 2015

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Reduce frequency of unspecific HSW reg debugging

On Fri, Sep 04, 2015 at 04:53:28PM +0200, Daniel Vetter wrote: > On Fri, Sep 04, 2015 at 03:18:14PM +0300, Mika Kuoppala wrote: > > Mika Kuoppala writes: > > > > > Daniel Vetter writes: > > > > > >> On Fri, Sep 04, 2015 at 11:40:26AM +0300, Mika Kuoppala wrote: > > >>> Daniel Vetter writes: > >

Re: [Intel-gfx] [PATCH 11/15] drm/i915: Add NV12 to primary plane programming.

On Fri, Sep 04, 2015 at 02:09:41PM +0300, Ville Syrjälä wrote: > Really, someone should just finally fix the mess we have made with handling > different types of planes in totally different ways and unify things as > much as possible. Yeah I want universal planes for skl finally, and I'd like to h

Re: [Intel-gfx] [PATCH 04/15] drm/i915: Set scaler mode for NV12

On Fri, Sep 04, 2015 at 11:53:36AM +0300, Ville Syrjälä wrote: > On a further note, this function could use some cleaning to move > various variables into narrower scope. Now it's rather hard to see what > is valid per iteration and what is valid across the entire loop. It's also rather big, so mi

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Reduce frequency of unspecific HSW reg debugging

On Fri, Sep 04, 2015 at 03:18:14PM +0300, Mika Kuoppala wrote: > Mika Kuoppala writes: > > > Daniel Vetter writes: > > > >> On Fri, Sep 04, 2015 at 11:40:26AM +0300, Mika Kuoppala wrote: > >>> Daniel Vetter writes: > >>> > >>> > On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote: > >

Re: [Intel-gfx] [PATCH 4/6] drm/i915: drm/i915: Check live status before reading edid

On Fri, Sep 04, 2015 at 06:56:14PM +0530, Sonika Jindal wrote: > The Bspec is very clear that Live status must be checked about before > trying to read EDID over DDC channel. This patch makes sure that HDMI > EDID is read only when live status us up. > > The live status doesn't seem to perform ver

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Add HDMI probe function

On Fri, Sep 04, 2015 at 06:56:12PM +0530, Sonika Jindal wrote: > From: Shashank Sharma > > This patch adds a separate probe function for HDMI > EDID read over DDC channel. This function has been > registered as a .hot_plug handler for HDMI encoder. > > The current implementation of hdmi_detect()

Re: [Intel-gfx] [PATCH 5/6] drm/i915: drm/i915: Process hpd only for hdmi inside hotplug_work_func

On Fri, Sep 04, 2015 at 06:56:15PM +0530, Sonika Jindal wrote: > If the same port is enumerated as hdmi as well as DP, this will get > called for DP connector as well which is not required because > i915_hotplug_work_func is solely to handle hdmi HPD. > > Signed-off-by: Sonika Jindal > --- > dri

Re: [Intel-gfx] Request Linux Graphic Driver for Intel GMA 3150

Hello Rodrigo/Matt, Running: lspci -ns :00:02.0 | awk -F: '{ print $4 }' returns: a001 (rev 02) I’m not very familiar with “build”. and build your self following: https://01.org/linuxgraphics/documentation/build-guide-0 If I follow all steps in above link, will I get a de

[Intel-gfx] [PATCH i-g-t] tools: install the register definition files

Install the register definition files and use them by default in intel_reg. Suggested-by: Jani Nikula Signed-off-by: Thomas Wood --- configure.ac| 5 +++-- tools/Makefile.am | 2 +- tools/intel_reg.c | 4 +++- tools/registers/Makefile.am | 3 ++- 4 files chan

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Reduce frequency of unspecific HSW reg debugging

2015-09-04 10:57 GMT-03:00 Mika Kuoppala : > "Zanoni, Paulo R" writes: > >> Em Sex, 2015-09-04 às 11:40 +0300, Mika Kuoppala escreveu: >>> Daniel Vetter writes: >>> >>> > On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote: >>> > > From: Chris Wilson >>> > > >>> > > Delay the expensive

[Intel-gfx] [PATCH v5 2/2] drm/i915: On fb alloc failure, unref gem object where it gets refed

Currently when allocating a framebuffer fails, the gem object gets unrefed at the bottom of the call chain in __intel_framebuffer_create, not where it gets refed, which is in intel_framebuffer_create_for_mode (via i915_gem_alloc_object) and in intel_user_framebuffer_create (via drm_gem_object_looku

Re: [Intel-gfx] [PATCH v2 00/22] Enable gpu switching on the MacBook Pro

Hi Jani, On Mon, Aug 31, 2015 at 10:15:07PM +0300, Jani Nikula wrote: > On Sat, 29 Aug 2015, Lukas Wunner wrote: > > the patch set I've posted August 12 included 3 commits which fix bugs > > in i915. These bugs should be fixed independently of MacBook Pro GPU > > switching, please consider mergin

[Intel-gfx] [PATCH v5 1/2] drm/i915: Fix failure paths around initial fbdev allocation

From: Tvrtko Ursulin We had two failure modes here: 1. Deadlock in intelfb_alloc failure path where it calls drm_framebuffer_remove, which grabs the struct mutex and intelfb_create (caller of intelfb_alloc) was already holding it. 2. Deadlock in intelfb_create failure path where it calls drm_fr

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Reduce frequency of unspecific HSW reg debugging

"Zanoni, Paulo R" writes: > Em Sex, 2015-09-04 às 11:40 +0300, Mika Kuoppala escreveu: >> Daniel Vetter writes: >> >> > On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote: >> > > From: Chris Wilson >> > > >> > > Delay the expensive read on the FPGA_DBG register from once per >> > >

Re: [Intel-gfx] [PATCH 2/4] drm/i915: restrict unclaimed register checking

On Fri, Sep 04, 2015 at 01:38:07PM +, Zanoni, Paulo R wrote: > Em Sex, 2015-09-04 às 09:53 +0300, Mika Kuoppala escreveu: > > Paulo Zanoni writes: > > > > > The unclaimed register bit is only triggered when someone touches > > > the > > > specified register range. > > > > > > > I got the i

[Intel-gfx] [PATCH v2 1/3] drm/i915: use pch backlight override on hsw too

Currently the difference between backlight control on HSW vs. BDW/SKL is that on HSW we modify the duty cycle on the CPU register, and have the hardware pass the changes on to the PCH registers. We still drive the PCH PWM on both. While HSW and BDW use the same LPT PCH, BDW does not pass these mess

[Intel-gfx] [PATCH v2 3/3] drm/i915: don't hard code vlv backlight frequency if unset

Fall back to VBT based backlight modulation frequency if it's not set. Do not hard code. This could be a problem if there is no VBT. Cc: Clint Taylor Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_panel.c | 13 - 1 file changed, 13 deletions(-) diff --git a/drivers/gpu/

[Intel-gfx] [PATCH v2 2/3] drm/i915: initialize backlight max from VBT

Normally we determine the backlight PWM modulation frequency (which we also use as backlight max value) from the backlight registers at module load time, expecting the registers have been initialized by the BIOS. If this is not the case, we fail. The VBT contains the backlight modulation frequency

[Intel-gfx] [PATCH] drm/i915: Split alloc from init for lrc

Extend init/init_hw split to context init. - Move context initialisation in to i915_gem_init_hw - Move one off initialisation for render ring to i915_gem_validate_context - Move default context initialisation to logical_ring_init Rename intel_lr_context_deferred_create to intel_lr

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Reduce frequency of unspecific HSW reg debugging

Em Sex, 2015-09-04 às 11:40 +0300, Mika Kuoppala escreveu: > Daniel Vetter writes: > > > On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote: > > > From: Chris Wilson > > > > > > Delay the expensive read on the FPGA_DBG register from once per > > > mmio to > > > once per forcewake sec

[Intel-gfx] [PATCH 1/6] drm/i915: add attached connector to hdmi container

From: Shashank Sharma This patch adds the intel_connector initialized to intel_hdmi display, during the init phase, just like the other encoders do. This attachment is very useful when we need to extract the connector pointer during the hotplug handler function Signed-off-by: Shashank Sharma --

[Intel-gfx] [PATCH 5/6] drm/i915: drm/i915: Process hpd only for hdmi inside hotplug_work_func

If the same port is enumerated as hdmi as well as DP, this will get called for DP connector as well which is not required because i915_hotplug_work_func is solely to handle hdmi HPD. Signed-off-by: Sonika Jindal --- drivers/gpu/drm/i915/intel_hotplug.c |3 ++- 1 file changed, 2 insertions(+)

[Intel-gfx] [PATCH 4/6] drm/i915: drm/i915: Check live status before reading edid

The Bspec is very clear that Live status must be checked about before trying to read EDID over DDC channel. This patch makes sure that HDMI EDID is read only when live status us up. The live status doesn't seem to perform very consistent across various platforms when tested with different monitors

[Intel-gfx] [PATCH 2/6] drm/i915: Add HDMI probe function

From: Shashank Sharma This patch adds a separate probe function for HDMI EDID read over DDC channel. This function has been registered as a .hot_plug handler for HDMI encoder. The current implementation of hdmi_detect() function re-sets the cached HDMI edid (in connector->detect_edid) in every d

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Reduce frequency of unspecific HSW reg debugging

Em Sex, 2015-09-04 às 10:02 +0300, Mika Kuoppala escreveu: > Paulo Zanoni writes: > > > From: Chris Wilson > > > > Delay the expensive read on the FPGA_DBG register from once per > > mmio to > > once per forcewake section when we are doing the general wellbeing > > check rather than the target

Re: [Intel-gfx] [PATCH 2/4] drm/i915: restrict unclaimed register checking

Em Sex, 2015-09-04 às 09:53 +0300, Mika Kuoppala escreveu: > Paulo Zanoni writes: > > > The unclaimed register bit is only triggered when someone touches > > the > > specified register range. > > > > I got the impression that we get the unclaimed access also > for other ranges, if they are pow

[Intel-gfx] [PATCH 6/6] drm/i915/bxt: Fix irq_port for eDP

From: Durgadoss R Currently, HDMI hotplug with eDP as local panel is failing because the HDMI hpd is detected as a long hpd for eDP; and is thus rightfully ignored. But, it should really be handled as an interrupt on port B for HDMI (due to BXT A1 platform having HPD pins A and B swapped). This p

[Intel-gfx] [PATCH 0/6] HDMI optimization series

This series adds changes in HDMI detection methods and also afew optimization. The overview of changes are: 1. HDMI EDID is read only at the hot-plug time. 2. EDID is cached in connectoer on hotplug,and released from cache only on the hot-unplug. 3. In between, for all detetct calls, only cached

[Intel-gfx] [PATCH 3/6] drm/i915: Make intel_digital_port_connected global

This is to allow live status check for HDMI as well. Also, using intel_encoder->hpd_pin to check the live status for bxt because of BXT A0/A1 WA for HPD pins. Signed-off-by: Sonika Jindal --- drivers/gpu/drm/i915/intel_dp.c | 11 +++ drivers/gpu/drm/i915/intel_drv.h |2 ++ 2 files

Re: [Intel-gfx] [PATCH 2/2] drm/i915: initialize backlight max from VBT

On Fri, 04 Sep 2015, Jani Nikula wrote: > On Thu, 27 Aug 2015, Clint Taylor wrote: >> On 08/26/2015 12:58 AM, Jani Nikula wrote: >>> Normally we determine the backlight PWM modulation frequency (which we >>> also use as backlight max value) from the backlight registers at module >>> load time, ex

Re: [Intel-gfx] [PATCH 2/2] drm/i915: initialize backlight max from VBT

On Thu, 27 Aug 2015, Clint Taylor wrote: > On 08/26/2015 12:58 AM, Jani Nikula wrote: >> Normally we determine the backlight PWM modulation frequency (which we >> also use as backlight max value) from the backlight registers at module >> load time, expecting the registers have been initialized by

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Reduce frequency of unspecific HSW reg debugging

Mika Kuoppala writes: > Daniel Vetter writes: > >> On Fri, Sep 04, 2015 at 11:40:26AM +0300, Mika Kuoppala wrote: >>> Daniel Vetter writes: >>> >>> > On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote: >>> >> From: Chris Wilson >>> >> >>> >> Delay the expensive read on the FPGA_DBG

[Intel-gfx] [PATCH 2/2] drm/i915/lrc: Prevent preemption when lite-restore is disabled

When WaEnableForceRestoreInCtxtDescForVCS is required, it is only safe to send new contexts if the last reported event is "active to idle". Otherwise the same context can fully preempt itself because lite-restore is disabled. Testcase: igt/gem_concurrent_blit Reported-by: Daniele Ceraolo Spurio S

[Intel-gfx] [PATCH 1/2] drm/i915: WaEnableForceRestoreInCtxtDescForVCS is for video engines only

Also check for correct revision id in each Gen9 platform (SKL until B0 and BXT until A0). Cc: Nick Hoath Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/intel_lrc.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/

Re: [Intel-gfx] [PATCH i-g-t] tools: remove quick_dump

On Fri, 04 Sep 2015, Ville Syrjälä wrote: > On Fri, Sep 04, 2015 at 11:22:28AM +0100, Thomas Wood wrote: >> Remove quick_dump as it has been replaced by the intel_reg tool and move >> the register definition files to tools/registers. >> >> Signed-off-by: Thomas Wood > > NAK > > It's the only too

Re: [Intel-gfx] [PATCH i-g-t] tools: remove quick_dump

On Fri, 04 Sep 2015, Thomas Wood wrote: > Remove quick_dump as it has been replaced by the intel_reg tool and move > the register definition files to tools/registers. > > Signed-off-by: Thomas Wood Acked-by: Jani Nikula As a follow-up, I'd like it if Someone(tm) would add rules to install the

Re: [Intel-gfx] [PATCH i-g-t] tools: remove quick_dump

On Fri, Sep 04, 2015 at 02:38:41PM +0300, Ville Syrjälä wrote: > On Fri, Sep 04, 2015 at 11:22:28AM +0100, Thomas Wood wrote: > > Remove quick_dump as it has been replaced by the intel_reg tool and move > > the register definition files to tools/registers. > > > > Signed-off-by: Thomas Wood > >

Re: [Intel-gfx] [PATCH 3/4] drm/i915: remove intel_uncore_check_errors()

Paulo Zanoni writes: > I added this code on 8664281b64c457705db72fc60143d03827e75ca9, on > April 12 2013. Back then, we only had support for detecting unclaimed > registers on I915_WRITE operations, and we didn't have the > i915.mmio_debug infrastructure. > > I tried to remember exactly why I add

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Reduce frequency of unspecific HSW reg debugging

Daniel Vetter writes: > On Fri, Sep 04, 2015 at 11:40:26AM +0300, Mika Kuoppala wrote: >> Daniel Vetter writes: >> >> > On Thu, Sep 03, 2015 at 04:51:45PM -0300, Paulo Zanoni wrote: >> >> From: Chris Wilson >> >> >> >> Delay the expensive read on the FPGA_DBG register from once per mmio to >>

Re: [Intel-gfx] [PATCH i-g-t] tools: remove quick_dump

On Fri, Sep 04, 2015 at 11:22:28AM +0100, Thomas Wood wrote: > Remove quick_dump as it has been replaced by the intel_reg tool and move > the register definition files to tools/registers. > > Signed-off-by: Thomas Wood NAK It's the only tool that works on VLV/CHV reasonably. > --- > README

Re: [Intel-gfx] [PATCH 15/15] drm/i915: Add 90/270 rotation for NV12 format.

On Wed, Aug 19, 2015 at 06:02:36PM -0700, Chandra Konduru wrote: > Adding NV12 90/270 rotation support for primary and sprite planes. > > v2: > -For 90/270 adjust pixel boundary only in Y-direction (bspec) > > v3: > -Rebased (me) > > Signed-off-by: Chandra Konduru > Testcase: igt/kms_nv12 > ---

Re: [Intel-gfx] [PATCH 14/15] drm/i915: skl nv12 workarounds

On Wed, Aug 19, 2015 at 06:02:35PM -0700, Chandra Konduru wrote: > Adding driver workarounds for nv12. > > Signed-off-by: Chandra Konduru > --- > drivers/gpu/drm/i915/i915_reg.h | 20 > drivers/gpu/drm/i915/intel_csr.c |2 +- > drivers/gpu/drm/i915/intel_displ

Re: [Intel-gfx] [PATCH 13/15] drm/i915: Set initial phase & trip for NV12 scaler

On Wed, Aug 19, 2015 at 06:02:34PM -0700, Chandra Konduru wrote: > This patch sets default initial phase and trip to scale NV12 > content. In future, if needed these can be set via properties > or other means depending on incoming stream request. Until then > defaults are fine. We should set it ac

Re: [Intel-gfx] [PATCH 11/15] drm/i915: Add NV12 to primary plane programming.

On Wed, Aug 19, 2015 at 06:02:32PM -0700, Chandra Konduru wrote: > This patch is adding NV12 support to skylake primary plane > programming. It is covering linear/X/Y/Yf tiling formats > for 0 and 180 rotations. > > For 90/270 rotation, Y and UV subplanes should be treated > as separate surfaces a

Re: [Intel-gfx] [PATCH] drm/i915: Improve kernel-doc for i915_audio_component struct

On Fri, 04 Sep 2015 12:33:45 +0200, David Henningsson wrote: > > > > On 2015-09-04 10:03, Daniel Vetter wrote: > > Also please use the new inline style for struct members. > > I tried that, but I couldn't get it to work. This was with Takashi's > for-next tree, do I need to apply some docbook

Re: [Intel-gfx] [PATCH 10/15] drm/i915: Add NV12 support to intel_framebuffer_init

On Wed, Aug 19, 2015 at 06:02:31PM -0700, Chandra Konduru wrote: > This patch adds NV12 as supported format to > intel_framebuffer_init and performs various checks. > > v2: > -Fix an issue in checks added (me) > > Signed-off-by: Chandra Konduru > Testcase: igt/kms_nv12 > --- > drivers/gpu/drm/i

Re: [Intel-gfx] [PATCH] drm/i915: Improve kernel-doc for i915_audio_component struct

On 2015-09-04 10:03, Daniel Vetter wrote: Also please use the new inline style for struct members. I tried that, but I couldn't get it to work. This was with Takashi's for-next tree, do I need to apply some docbook special patches on top of that to get the new functionality? -- David Henn

[Intel-gfx] [PATCH i-g-t] tools: remove quick_dump

Remove quick_dump as it has been replaced by the intel_reg tool and move the register definition files to tools/registers. Signed-off-by: Thomas Wood --- README | 13 --- configure.ac | 27 + man/intel_reg.rs

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