On Thu, 2017-03-16 at 05:59 -0700, Robert Bragg wrote:
> On Thu, Mar 16, 2017 at 6:14 AM, wrote:
> > From: Sourab Gupta
> >
> > This series adds framework for collection of OA reports associated with the
> > render command stream, which are collected around batchbuffer boundaries.
> >
> > Refloa
> > > Since intel_gvt_init() is called at early initialization stage and
> > > require the status notifier head has been initiated, I initiate it in
> > > intel_engine_setup().
> > >
> > > v2: remove a redundant newline. (chris)
> > >
> > > Signed-off-by: Changbin Du
> > > Reviewed-by: Chris Wil
On Thu, Mar 16, 2017 at 04:40:01PM +0200, Jani Nikula wrote:
> On Thu, 16 Mar 2017, Greg KH wrote:
> > And again, you all are the only ones that have this issue. You might
> > find a handfull of patches for stable that come in twice in the rest of
> > the kernel, but your "little" driver dwarfs t
== Series Details ==
Series: series starting with [1/2] drm: Mark up accesses of vblank->enabled
outside of its spinlock
URL : https://patchwork.freedesktop.org/series/21410/
State : failure
== Summary ==
Series 21410v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/ser
Order the update to vblank->enabled after the timestamp is primed so
that a concurrent unlocked reader will only see the vblank->enabled with
the current timestamp.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Cc: Daniel Vetter
---
drivers/gpu/drm/drm_irq.c | 30 ++
Bypass all the spinlocks and return the last timestamp and counter from
the last vblank if the driver delcares that it is accurate (and stable
across on/off), and the vblank is currently enabled.
This is dependent upon the both the hardware and driver to provide the
proper barriers to facilitate r
== Series Details ==
Series: Adding driver-private objects to atomic state (rev4)
URL : https://patchwork.freedesktop.org/series/19355/
State : failure
== Summary ==
Series 19355v4 Adding driver-private objects to atomic state
https://patchwork.freedesktop.org/api/1.0/series/19355/revisions/4/
From: "Pandiyan, Dhinakaran"
Having an ->atomic_release callback is useful to release shared resources
that get allocated in compute_config(). This function is expected to be
called in the atomic_check() phase before new resources are acquired.
v4: Document that the function is conditionally cal
On Thu, Mar 16, 2017 at 11:58:23PM +0530, Sagar Arun Kamble wrote:
> @@ -862,6 +904,10 @@ void intel_slpc_init(struct drm_i915_private *dev_priv)
>
> dev_priv->guc.slpc.active = false;
>
> + mutex_lock(&dev_priv->rps.hw_lock);
> + gen6_init_rps_frequencies(dev_priv);
> + mutex
On Thu, Mar 16, 2017 at 11:58:27PM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke
>
> This patch makes SLPC enabled by default on
> platforms with hardware/firmware support.
Still requires justification here.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
On Thu, Mar 16, 2017 at 11:58:10PM +0530, Sagar Arun Kamble wrote:
> On platforms with SLPC support: call intel_slpc_*() functions from
> intel_*_gt_powersave() functions and GuC setup functions and do not
> use rps functions. intel_slpc_enable is tied to GuC setup.
> With SLPC, intel_enable_gt_pow
== Series Details ==
Series: drm/i915: Avoid use-after-free of ctx in request tracepoints
URL : https://patchwork.freedesktop.org/series/21398/
State : success
== Summary ==
Series 21398v1 drm/i915: Avoid use-after-free of ctx in request tracepoints
https://patchwork.freedesktop.org/api/1.0/se
On Thu, Mar 16, 2017 at 11:58:09PM +0530, Sagar Arun Kamble wrote:
> From: Tom O'Rourke
>
> The SLPC interface is dependent on GuC version.
> Only GuC versions known to be compatible are supported here.
>
> SLPC with GuC firmware v9 is supported with this series.
> Other platforms and correspond
On Thu, Mar 16, 2017 at 07:23:47PM +0200, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > This should be impossible, but let's assert that we do not pin a context
> > 4 billion times before retiring!
> >
> > v2: Fix the assertion -- the patch had just one job to do!
> >
> > Signed-off-by: Chris
trace_i915_gem_request_out may be used after the request is completed,
and so the request may have been retired on another thread, invalidating
the rq->ctx. Avoid dereferencing rq->ctx in the tracepoint by switching
to the fence context id instead, updating all tracepoints to match.
Signed-off-by:
On Thu, Mar 16, 2017 at 5:09 PM, Maarten Lankhorst
wrote:
> Op 16-03-17 om 16:52 schreef Daniel Vetter:
>> The vblank code really wants to look at crtc->state without having to
>> take a ww_mutex. One option might be to take one of the vblank locks
>> right when assigning crtc->state, which would
On Thu, Mar 16, 2017 at 05:07:26PM +0530, Praveen Paneri wrote:
> Hi Ville,
>
> On Wednesday 15 March 2017 03:53 PM, Ville Syrjälä wrote:
> > On Wed, Mar 15, 2017 at 12:29:35PM +0530, Praveen Paneri wrote:
> >> FBC is only enabled for X-tiled framebuffers but there are
> >> quite a few cases where
Em Qui, 2017-03-16 às 17:38 +0530, Praveen Paneri escreveu:
> When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
> surfaces on gen9, the cfb stride must be programmed by SW as
>
> cfb_stride = ceiling[(at least plane width in pixels)/
> (32 * compression limit factor)]
Em Ter, 2017-02-28 às 17:01 +0530, Mahesh Kumar escreveu:
> This patch make changes to calculate adjusted plane pixel rate &
> plane downscale amount using fixed_point functions available. This
> also
> adds few fixed point function to facilitate calculation.
Before we go into the full review I ne
== Series Details ==
Series: Add support for GuC-based SLPC (rev8)
URL : https://patchwork.freedesktop.org/series/2691/
State : success
== Summary ==
Series 2691v8 Add support for GuC-based SLPC
https://patchwork.freedesktop.org/api/1.0/series/2691/revisions/8/mbox/
Test gem_exec_fence:
From: Tom O'Rourke
Adds debugfs hooks for enabling/disabling each SLPC task.
The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.
Each of these can take the values:
"default", "enabled", or "disabled"
v1: update for SLPC v2015.2.4
dfps and turbo mer
From: Tom O'Rourke
i915_slpc_info shows the contents of SLPC shared data
parsed into text format.
v1: Reformat slpc info (Radek)
squashed query task state info
in slpc info, kunmap before seq_print (Paulo)
return void instead of ignored return value (Paulo)
Avoid magic numbers an
SLPC shared data is used to pass information to/from GuC SLPC.
This has details of SKU type, Slice count, IA Perf MSR values,
state etc.
v1: Update for SLPC interface version 2015.2.4
intel_slpc_active() returns 1 if slpc initialized (Paulo)
change default host_os to "Windows"
Spelling
SLPC behavior can be changed through set of parameters.
These parameters can be updated and queried from i915 though
Host to GuC SLPC events. This patch add parameter values and
events for setting/unsetting parameters.
v1: Use host2guc_slpc
update slcp_param_id enum values for SLPC 2015.2.4
Input string parsing used in CRC control parameter parsing is generic
and can be reused for other debugfs interfaces. Hence name it as
buffer_tokenize instead of tieing to display_crc. Also fix the function
desciption for CRC control parsing that was misplaced at tokenize function.
Cc: Tomeu Vizos
Communication with SLPC is via Host to GuC interrupt.
This patch defines the data structure to be passed as input
and received as output from SLPC. This patch also defines the
events to be sent as input and status values output by GuC
on processing SLPC events.
v1: fix whitespace (Sagar)
v2-v3: R
v1: Updated tasks and frequency post reset.
Added DFPS param update for MAX_FPS and FPS Stall.
v2-v3: Rebase.
v4: Updated with GuC firmware v9.
v5: Rebase. Replaced H2G interrupts for parameter override with memory
setup with required parameters.
v6: Moved task override to intel_slpc_in
From: Tom O'Rourke
This patch makes SLPC enabled by default on
platforms with hardware/firmware support.
v1: Removing warning "enable_slpc < 0" as it is
set to -1 with this patch now. This was caught by CI BAT.
v2-v4: Rebase.
v5: Sanitizing SLPC option based on capabilities earlier in
driver l
From: Tom O'Rourke
This patch adds has_slpc to skylake info.
The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.
On Skylake, GuC firmware v6 is supported. Other
platforms and versions can be added here later.
v1: Move slpc_
Send host2guc SLPC reset event to GuC post GuC load.
Post this, i915 can ascertain if SLPC has started running successfully
through shared data. This check is done during intel_init_gt_powersave.
This allows to get initial configuration setup by SLPC and if needed
move to Host RPS if SLPC runs into
This patch adds two debugfs interfaces:
1. i915_slpc_paramlist: List of all parameters that Host can configure.
Currently listing id and names.
2. i915_slpc_param_ctl: This allows to change the parameters. Syntax is:
echo "write " > i915_slpc_param_ctl.
echo "read " > i915_slpc_param_ctl;
From: Tom O'Rourke
Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.
v1: Return void instead of ignored error code (Paulo)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
Added SLPC
Adds has_slpc to kabylake info and adds kabylake firmware version check
to sanitize_slpc_option.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_slpc.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/d
From: Tom O'Rourke
The SLPC interface is dependent on GuC version.
Only GuC versions known to be compatible are supported here.
SLPC with GuC firmware v9 is supported with this series.
Other platforms and corresponding checks added later in the series.
v1: Updated with modified sanitize_slpc_op
From: Tom O'Rourke
Adds has_slpc to broxton info and adds broxton firmware version check
to sanitize_slpc_option.
v1: Adjusted slpc version check for major version 8.
Added message if version mismatch happens for easier debug. (Sagar)
v2-v3: Rebase.
v4: Commit message update.
v5: Rebase.
On platforms with SLPC support: call intel_slpc_*() functions from
intel_*_gt_powersave() functions and GuC setup functions and do not
use rps functions. intel_slpc_enable is tied to GuC setup.
With SLPC, intel_enable_gt_powersave will only handle RC6 and ring
frequencies. intel_init_gt_powersave w
When SLPC is controlling frequency requests, RPS state related to
autotuning is no longer valid. Make user aware through banner
upfront. Value read from register RPNSWREQ likely has the frequency
requested last by GuC SLPC.
v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
Avoid magic number
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
v2-v4: Rebase.
v5: Removed typecasting the frequency values to u32. (Chris)
Changed
With GuC based SLPC, frequency control will be moved to GuC and Host will
continue to control RC6 and Ring frequency setup. SLPC can be enabled in
the GuC setup path and can happen in parallel in GuC with other i915 setup.
Hence we can do away with deferred RPS enabling. This needs separate
handlin
SLPC (Single Loop Power Controller) is a replacement for some host-based
power management features. The SLPC implementation runs in firmware on GuC.
This series has been tested with SKL/APL/KBL GuC firmware v9.
The graphics power management features in SLPC in this version are called
GTPERF, BALAN
From: Tom O'Rourke
When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.
Host-based turbo operations are already avoided when
SLPC is used. This change covers other frequency
requests such as from sysfs or debugfs interfa
From: Tom O'Rourke
Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC). SLPC is
a replacement for some host-based power management
features.
v1: fix whitespace (Sagar)
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Aru
From: Tom O'Rourke
If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.
v1: Use intel_slpc_enabled() (Paulo)
v2-v4: Rebase.
v5: Changed intel_slpc_enabled() to i915.enable_slpc. (Sagar)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers
From: Tom O'Rourke
i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.
slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_chec
Apologies for this erroneous patch.
My .config did not have CONFIG_DRM_I915_WERROR set so did not catch.
Should have let this through trybot for this change.
On 3/16/2017 10:53 PM, Patchwork wrote:
== Series Details ==
Series: Add support for GuC-based SLPC (rev7)
URL : https://patchwork.fr
== Series Details ==
Series: drm/i915: Assert that the context pin_counts do not overflow (rev2)
URL : https://patchwork.freedesktop.org/series/21390/
State : success
== Summary ==
Series 21390v2 drm/i915: Assert that the context pin_counts do not overflow
https://patchwork.freedesktop.org/api
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Split I915_RESET_IN_PROGRESS
into two flags
URL : https://patchwork.freedesktop.org/series/21393/
State : failure
== Summary ==
Series 21393v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/2139
Chris Wilson writes:
> This should be impossible, but let's assert that we do not pin a context
> 4 billion times before retiring!
>
> v2: Fix the assertion -- the patch had just one job to do!
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> Cc: Joonas Lahtinen
> Cc: Mika Kuoppala
Rev
== Series Details ==
Series: Add support for GuC-based SLPC (rev7)
URL : https://patchwork.freedesktop.org/series/2691/
State : failure
== Summary ==
CC [M] drivers/gpu/drm/i915/gvt/gvt.o
CC [M] drivers/gpu/drm/i915/gvt/trace_points.o
CC [M] drivers/gpu/drm/i915/gvt/vgpu.o
LD d
This should be impossible, but let's assert that we do not pin a context
4 billion times before retiring!
v2: Fix the assertion -- the patch had just one job to do!
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c
Provide some serialisation between user operations by waiting for the
reset initiated by setting i915_wedged to complete.
The automatic wait here makes
echo 1 > i915_wedged; cat i915_error_state
do the right thing, and not risk reporting "No error collected".
Signed-off-by: Chris Wilson
It turns out that we may want to restore the original
engine->submit_request (and engine->schedule) callbacks from more than
just the guc <-> execlists transition. Move this to a vfunc so we can
have a common interface.
v2: Move initial selection to intel_engines_init_common(), repaint vfunc
with
When we wedge the device, we override engine->submit_request with a nop
to ensure that all in-flight requests are marked in error. However, igt
would like to unwedge the device to test -EIO handling. This requires us
to flush those in-flight requests and restore the original
engine->submit_request.
I915_RESET_IN_PROGRESS is being used for both signaling the requirement
to i915_mutex_lock_interruptible() to avoid taking the struct_mutex and
to instruct a waiter (already holding the struct_mutex) to perform the
reset. To allow for a little more coordination, split these two meaning
into a coupl
Mika Kuoppala writes:
> Chris Wilson writes:
>
>> Provide some serialisation between user operations by waiting for the
>> reset initiated by setting i915_wedged to complete.
>>
>> Signed-off-by: Chris Wilson
>> Cc: Tvrtko Ursulin
>> Cc: Mika Kuoppala
>> ---
>> drivers/gpu/drm/i915/i915_debu
On Thu, Mar 16, 2017 at 06:38:09PM +0200, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > Provide some serialisation between user operations by waiting for the
> > reset initiated by setting i915_wedged to complete.
The automatic wait here makes
echo 1 > i915_wedged; cat i915_error_sta
Chris Wilson writes:
> I915_RESET_IN_PROGRESS is being used for both signaling the requirement
> to i915_mutex_lock_interruptible() to avoid taking the struct_mutex and
> to instruct a waiter (already holding the struct_mutex) to perform the
> reset. To allow for a little more coordination, split
== Series Details ==
Series: drm/i915: Assert that the context pin_counts do not overflow
URL : https://patchwork.freedesktop.org/series/21390/
State : failure
== Summary ==
Series 21390v1 drm/i915: Assert that the context pin_counts do not overflow
https://patchwork.freedesktop.org/api/1.0/se
Chris Wilson writes:
> Provide some serialisation between user operations by waiting for the
> reset initiated by setting i915_wedged to complete.
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 4
> 1 file changed, 4
From: Tom O'Rourke
Adds debugfs hooks for enabling/disabling each SLPC task.
The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.
Each of these can take the values:
"default", "enabled", or "disabled"
v1: update for SLPC v2015.2.4
dfps and turbo mer
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
v2-v4: Rebase.
v5: Removed typecasting the frequency values to u32. (Chris)
Changed
From: Tom O'Rourke
This patch adds has_slpc to skylake info.
The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.
On Skylake, GuC firmware v6 is supported. Other
platforms and versions can be added here later.
v1: Move slpc_
When SLPC is controlling frequency requests, RPS state related to
autotuning is no longer valid. Make user aware through banner
upfront. Value read from register RPNSWREQ likely has the frequency
requested last by GuC SLPC.
v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
Avoid magic number
From: Tom O'Rourke
Adds has_slpc to broxton info and adds broxton firmware version check
to sanitize_slpc_option.
v1: Adjusted slpc version check for major version 8.
Added message if version mismatch happens for easier debug. (Sagar)
v2-v3: Rebase.
v4: Commit message update.
v5: Rebase.
Adds has_slpc to kabylake info and adds kabylake firmware version check
to sanitize_slpc_option.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_slpc.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/d
From: Tom O'Rourke
i915_slpc_info shows the contents of SLPC shared data
parsed into text format.
v1: Reformat slpc info (Radek)
squashed query task state info
in slpc info, kunmap before seq_print (Paulo)
return void instead of ignored return value (Paulo)
Avoid magic numbers an
v1: Updated tasks and frequency post reset.
Added DFPS param update for MAX_FPS and FPS Stall.
v2-v3: Rebase.
v4: Updated with GuC firmware v9.
v5: Rebase. Replaced H2G interrupts for parameter override with memory
setup with required parameters.
v6: Moved task override to intel_slpc_in
Send host2guc SLPC reset event to GuC post GuC load.
Post this, i915 can ascertain if SLPC has started running successfully
through shared data. This check is done during intel_init_gt_powersave.
This allows to get initial configuration setup by SLPC and if needed
move to Host RPS if SLPC runs into
SLPC shared data is used to pass information to/from GuC SLPC.
This has details of SKU type, Slice count, IA Perf MSR values,
state etc.
v1: Update for SLPC interface version 2015.2.4
intel_slpc_active() returns 1 if slpc initialized (Paulo)
change default host_os to "Windows"
Spelling
From: Tom O'Rourke
This patch makes SLPC enabled by default on
platforms with hardware/firmware support.
v1: Removing warning "enable_slpc < 0" as it is
set to -1 with this patch now. This was caught by CI BAT.
v2-v4: Rebase.
v5: Sanitizing SLPC option based on capabilities earlier in
driver l
This patch adds two debugfs interfaces:
1. i915_slpc_paramlist: List of all parameters that Host can configure.
Currently listing id and names.
2. i915_slpc_param_ctl: This allows to change the parameters. Syntax is:
echo "write " > i915_slpc_param_ctl.
echo "read " > i915_slpc_param_ctl;
Communication with SLPC is via Host to GuC interrupt.
This patch defines the data structure to be passed as input
and received as output from SLPC. This patch also defines the
events to be sent as input and status values output by GuC
on processing SLPC events.
v1: fix whitespace (Sagar)
v2-v3: R
SLPC behavior can be changed through set of parameters.
These parameters can be updated and queried from i915 though
Host to GuC SLPC events. This patch add parameter values and
events for setting/unsetting parameters.
v1: Use host2guc_slpc
update slcp_param_id enum values for SLPC 2015.2.4
From: Tom O'Rourke
Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.
v1: Return void instead of ignored error code (Paulo)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
Added SLPC
On Thu, Mar 16, 2017 at 06:27:16PM +0200, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > This should be impossible, but let's assert that we do not pin a context
> > 4 billion times before retiring!
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > Cc: Joonas Lahtinen
> > ---
>
From: Tom O'Rourke
The SLPC interface is dependent on GuC version.
Only GuC versions known to be compatible are supported here.
SLPC with GuC firmware v9 is supported with this series.
Other platforms and corresponding checks added later in the series.
v1: Updated with modified sanitize_slpc_op
From: Tom O'Rourke
When frequency requests are made by SLPC, host driver
should not attempt to make frequency requests due to
potential conflicts.
Host-based turbo operations are already avoided when
SLPC is used. This change covers other frequency
requests such as from sysfs or debugfs interfa
From: Tom O'Rourke
i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.
slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_chec
SLPC (Single Loop Power Controller) is a replacement for some host-based
power management features. The SLPC implementation runs in firmware on GuC.
This series has been tested with SKL/APL/KBL GuC firmware v9.
The graphics power management features in SLPC in this version are called
GTPERF, BALAN
With GuC based SLPC, frequency control will be moved to GuC and Host will
continue to control RC6 and Ring frequency setup. SLPC can be enabled in
the GuC setup path and can happen in parallel in GuC with other i915 setup.
Hence we can do away with deferred RPS enabling. This needs separate
handlin
Input string parsing used in CRC control parameter parsing is generic
and can be reused for other debugfs interfaces. Hence name it as
buffer_tokenize instead of tieing to display_crc. Also fix the function
desciption for CRC control parsing that was misplaced at tokenize function.
Cc: Tomeu Vizos
From: Tom O'Rourke
If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.
v1: Use intel_slpc_enabled() (Paulo)
v2-v4: Rebase.
v5: Changed intel_slpc_enabled() to i915.enable_slpc. (Sagar)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers
On platforms with SLPC support: call intel_slpc_*() functions from
intel_*_gt_powersave() functions and GuC setup functions and do not
use rps functions. intel_slpc_enable is tied to GuC setup.
With SLPC, intel_enable_gt_powersave will only handle RC6 and ring
frequencies. intel_init_gt_powersave w
From: Tom O'Rourke
Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC). SLPC is
a replacement for some host-based power management
features.
v1: fix whitespace (Sagar)
Reviewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Aru
On Mon, Mar 13, 2017 at 12:03:30PM +0800, Zhenyu Wang wrote:
> On 2017.03.13 10:47:11 +0800, changbin...@intel.com wrote:
> > From: Changbin Du
> >
> > GVTg has introduced the context status notifier to schedule the GVTg
> > workload. At that time, the notifier is bound to GVTg context only,
> >
Chris Wilson writes:
> This should be impossible, but let's assert that we do not pin a context
> 4 billion times before retiring!
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/intel_lrc.c| 1 +
> drivers/gpu/drm/i915/intel_rin
== Series Details ==
Series: drm/atomic: protect crtc|connector->state with rcu
URL : https://patchwork.freedesktop.org/series/21389/
State : warning
== Summary ==
Series 21389v1 drm/atomic: protect crtc|connector->state with rcu
https://patchwork.freedesktop.org/api/1.0/series/21389/revisions
Chris Wilson writes:
> I915_RESET_IN_PROGRESS is being used for both signaling the requirement
> to i915_mutex_lock_interruptible() to avoid taking the struct_mutex and
> to instruct a waiter (already holding the struct_mutex) to perform the
> reset. To allow for a little more coordination, split
Op 16-03-17 om 16:52 schreef Daniel Vetter:
> The vblank code really wants to look at crtc->state without having to
> take a ww_mutex. One option might be to take one of the vblank locks
> right when assigning crtc->state, which would ensure that the vblank
> code doesn't race and access freed memo
Depending on what version of drm_i915.h you have, you may not have
this #define but it's required in order to properly dump aubs from
newer versions of mesa.
---
tools/aubdump.c | 8
1 file changed, 8 insertions(+)
diff --git a/tools/aubdump.c b/tools/aubdump.c
index 08cee55..8a89b8c 100
On Thu, Mar 16, 2017 at 3:51 AM, Petri Latvala
wrote:
> On Wed, Mar 15, 2017 at 09:09:31AM -0700, Jason Ekstrand wrote:
> > +#ifndef DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
> > +#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WRDRM_IOWR(DRM_COMMAND_BASE
> + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_e
This should be impossible, but let's assert that we do not pin a context
4 billion times before retiring!
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_lrc.c| 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
2 files changed, 2 inse
The vblank code really wants to look at crtc->state without having to
take a ww_mutex. One option might be to take one of the vblank locks
right when assigning crtc->state, which would ensure that the vblank
code doesn't race and access freed memory.
But userspace tends to poke the vblank_ioctl to
On Thu, Mar 16, 2017 at 04:27:42PM +0100, Maarten Lankhorst wrote:
> Op 16-03-17 om 15:56 schreef Daniel Vetter:
> > On Thu, Mar 16, 2017 at 01:05:06PM +0100, Maarten Lankhorst wrote:
> >> Op 16-03-17 om 11:48 schreef Daniel Vetter:
> >>> On Wed, Mar 15, 2017 at 11:08:56AM +0100, Maarten Lankhorst
Op 16-03-17 om 15:56 schreef Daniel Vetter:
> On Thu, Mar 16, 2017 at 01:05:06PM +0100, Maarten Lankhorst wrote:
>> Op 16-03-17 om 11:48 schreef Daniel Vetter:
>>> On Wed, Mar 15, 2017 at 11:08:56AM +0100, Maarten Lankhorst wrote:
As a proof of concept, first try to convert intel_tv, which is
== Series Details ==
Series: drm/i915: Skip execlists_dequeue() early if the list is empty
URL : https://patchwork.freedesktop.org/series/21382/
State : failure
== Summary ==
Series 21382v1 drm/i915: Skip execlists_dequeue() early if the list is empty
https://patchwork.freedesktop.org/api/1.0/
On Thu, Mar 16, 2017 at 01:05:06PM +0100, Maarten Lankhorst wrote:
> Op 16-03-17 om 11:48 schreef Daniel Vetter:
> > On Wed, Mar 15, 2017 at 11:08:56AM +0100, Maarten Lankhorst wrote:
> >> As a proof of concept, first try to convert intel_tv, which is a rarely
> >> used connector. It has 5 properti
Do an early read of the execlists' queue before we take the spinlock and
start checking. This is safe as the first writer to the execlists queue
will cause the tasklet to be run again after a memory barrier.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Michał Winiarski
On Thu, 16 Mar 2017, Greg KH wrote:
> And again, you all are the only ones that have this issue. You might
> find a handfull of patches for stable that come in twice in the rest of
> the kernel, but your "little" driver dwarfs that by an order of
> magnitude. I really think you are doing it wron
On Thu, Mar 16, 2017 at 04:15:35PM +0200, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > When manually overwriting the HWS, rather than assume irq_seqno_barrier
> > does the right thing, we can explicitly flush the cacheline instead.
> > This avoids us calling the engine->irq_seqno_barrier() f
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