Re: [Intel-gfx] [PATCH 66/67] drm/i915/cnl: LSPCON support is gen9+

Reviewed-by: Shashank Sharma Regards Shashank -Original Message- From: Vivi, Rodrigo Sent: Thursday, April 6, 2017 10:16 PM To: intel-gfx@lists.freedesktop.org Cc: Vivi, Rodrigo ; Sharma, Shashank Subject:

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/cnl: Wa to ignore VBT alternate pin on B-stepping.

== Series Details == Series: drm/i915/cnl: Wa to ignore VBT alternate pin on B-stepping. URL : https://patchwork.freedesktop.org/series/22626/ State : failure == Summary == CC [M] drivers/gpu/drm/i915/gvt/cmd_parser.o CC [M] drivers/gpu/drm/i915/gvt/render.o CC [M]

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev3)

== Series Details == Series: series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev3) URL : https://patchwork.freedesktop.org/series/22607/ State : warning == Summary == Series 22607v3 Series without cover letter

[Intel-gfx] [PATCH] drm/i915/cnp: add CNP gmbus support

On CNP PCH based platforms the gmbus is on the south display that is on PCH. The existing implementation for previous platforms already covers the need for CNP expect for the pin pair configuration that follows similar definitions that we had on BXT. v2: Don't drop "_BXT" as the indicator of the

[Intel-gfx] [PATCH] drm/i915/cnl: Wa to ignore VBT alternate pin on B-stepping.

Current VBT available for pre-production machines tells that we need to use alternate pin. But if we use it we end up needing to define a different table. However if we respect the spec, ignore the VBT for now we get a more reliable HDMI. Cc: Clint Taylor

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: write wopcm related register once during uc init

== Series Details == Series: drm/i915/guc: write wopcm related register once during uc init URL : https://patchwork.freedesktop.org/series/22625/ State : success == Summary == Series 22625v1 drm/i915/guc: write wopcm related register once during uc init

[Intel-gfx] [PATCH] drm/i915/guc: write wopcm related register once during uc init

The wopcm registers are write-once, so any write after the first one will just be ignored. The registers survive a GPU reset but not always a suspend/resume cycle, so to keep things simple keep the writes in the intel_uc_init_hw function instead of moving it earlier to make sure we attempt them

[Intel-gfx] [PATCH 0/5] Re: [BUG][REGRESSION] i915 gpu hangs under load

I'm also getting kernel hangs every couple of days. For me it's still not fixed here in 4.11-rc5. It's hard to reproduce, the best reproducer is to build lineageos 14.1 on host while running LTP in a guest to stress the guest VM. Initially I thought it was related to the fact I upgraded the xf86

[Intel-gfx] [PATCH 1/5] i915: avoid kernel hang caused by synchronize rcu struct_mutex deadlock

synchronize_rcu/synchronize_sched/synchronize_rcu_expedited() will hang until its own workqueues are run. The i915 gem workqueues will wait on the struct_mutex to be released. So we cannot wait for a quiescent state using those rcu primitives while holding the struct_mutex or it creates a circular

[Intel-gfx] [PATCH 5/5] i915: fence workqueue optimization

Insist to run llist_del_all() until the free_list is found empty, this may avoid having to schedule more workqueues. Signed-off-by: Andrea Arcangeli --- drivers/gpu/drm/i915/intel_display.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] [PATCH 2/5] i915: flush gem obj freeing workqueues to add accuracy to the i915 shrinker

Waiting a RCU grace period only guarantees the work gets queued, but until after the queued workqueue returns, there's no guarantee the memory was actually freed. So flush the work to provide better guarantees to the reclaim code in addition of waiting a RCU grace period to pass. Signed-off-by:

[Intel-gfx] [PATCH 4/5] i915: schedule while freeing the lists of gem objects

Add cond_resched(). Signed-off-by: Andrea Arcangeli --- drivers/gpu/drm/i915/i915_gem.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 612fde3..c81baeb 100644 ---

[Intel-gfx] [PATCH 3/5] i915: initialize the free_list of the fencing atomic_helper

Just in case the llist model changes and NULL isn't valid initialization. Signed-off-by: Andrea Arcangeli --- drivers/gpu/drm/i915/intel_display.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] ✓ Fi.CI.BAT: success for Classify the engines in class + instance (rev4)

== Series Details == Series: Classify the engines in class + instance (rev4) URL : https://patchwork.freedesktop.org/series/22535/ State : success == Summary == Series 22535v4 Classify the engines in class + instance https://patchwork.freedesktop.org/api/1.0/series/22535/revisions/4/mbox/

[Intel-gfx] [PATCH 0/5] Classify the engines in class + instance (v3)

This refactoring helps simplify a few things here and there. Daniele Ceraolo Spurio (2): drm/i915: Classify the engines in class + instance drm/i915: Use the engine class to get the context size Oscar Mateo (3): drm/i915: Use the same vfunc for BSD2 ring init drm/i915: Generate the

[Intel-gfx] [PATCH 1/5] drm/i915: Classify the engines in class + instance

From: Daniele Ceraolo Spurio In such a way that vcs and vcs2 are just two different instances (0 and 1) of the same engine class (VIDEO_DECODE_CLASS). v2: Align the instance types (Tvrtko) Cc: Paulo Zanoni Cc: Rodrigo Vivi

[Intel-gfx] [PATCH 3/5] drm/i915: Generate the engine name based on the instance number

Not really needed, but makes the next change a little bit more compact. v2: - Use zero-based numbering for engine names: xcs0, xcs1.. xcsN (Tvrtko, Chris) - Make sure the mock engine name is null-terminated (Tvrtko, Chris) v3: Because I'm stupid (Chris) Cc: Tvrtko Ursulin

[Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

There are some properties that logically belong to the engine class, and some that belong to the engine instance. Make it explicit. v2: Commit message (Tvrtko) v3: - Rebased - Exec/uabi id should be per instance (Chris) Cc: Tvrtko Ursulin Cc: Paulo Zanoni

[Intel-gfx] [PATCH 5/5] drm/i915: Use the engine class to get the context size

From: Daniele Ceraolo Spurio Technically speaking, the context size is per engine class, not per instance. v2: Add MISSING_CASE (Tvrtko) Cc: Paulo Zanoni Cc: Rodrigo Vivi Cc: Chris Wilson

[Intel-gfx] [PATCH 2/5] drm/i915: Use the same vfunc for BSD2 ring init

If we needed to do something different for the init functions, we could always look at the engine instance to make the distinction. But, in any case, the two functions are virtually identical already (please notice that BSD2_RING is only used from gen8 onwards). With this, the init functions

Re: [Intel-gfx] [PATCH 21/67] drm/i915/cnl: Update the context size

On 17-04-06 14:53:50, Ceraolo Spurio, Daniele wrote: On 06/04/17 12:15, Rodrigo Vivi wrote: From: Ben Widawsky The docs are not yet correct, so I cannot provide a reference to it. In the current docs, the size is actually smaller than SKL. This seems unlikely

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: rest of refactoring, link rate fallback (rev3)

== Series Details == Series: drm/i915/dp: rest of refactoring, link rate fallback (rev3) URL : https://patchwork.freedesktop.org/series/22586/ State : success == Summary == Series 22586v3 drm/i915/dp: rest of refactoring, link rate fallback

Re: [Intel-gfx] [PATCH 21/67] drm/i915/cnl: Update the context size

On 06/04/17 12:15, Rodrigo Vivi wrote: From: Ben Widawsky The docs are not yet correct, so I cannot provide a reference to it. In the current docs, the size is actually smaller than SKL. This seems unlikely given that in another part of the docs there are clearly

Re: [Intel-gfx] [PATCH v4] drm: Add DPCD definitions for DP 1.4 DSC feature

Hi Ander, Could you take a look at this? Manasi On Mon, Apr 03, 2017 at 03:51:10PM -0700, Manasi Navare wrote: > From: "Navare, Manasi D" > > Display stream compression is supported on DP 1.4 DP > devices. This patch adds the corersponding DPCD > register

Re: [Intel-gfx] [PATCH 0/4] drm/atomic: Cleanups for adding connector atomic check function.

On Thu, Apr 06, 2017 at 08:48:36AM -0400, Sean Paul wrote: > On Thu, Apr 06, 2017 at 01:18:59PM +0200, Maarten Lankhorst wrote: > > Some small cleanups I came across to make drm_atomic_helper_check_modeset > > more readable. > > > > This makes it a lot more clear what atomic_check does and why

[Intel-gfx] [PATCH v6] drm/i915/dp: Validate cached link rate and lane count before retraining

Currently intel_dp_check_link_status() tries to retrain the link if Clock recovery or Channel EQ for any of the lanes indicated by intel_dp->lane_count is not set. However these values cached in intel_dp structure can be stale if link training has failed for these values during previous modeset.

Re: [Intel-gfx] [PATCH] drm: Take mode_config.mutex in setcrtc ioctl

On Thu, Apr 06, 2017 at 03:09:04PM -0400, Alex Deucher wrote: > On Thu, Apr 6, 2017 at 3:06 PM, Daniel Vetter wrote: > > Legacy drivers insist that we really take all the locks in this path, > > and the harm in doing so is minimal. > > > > v2: Like git add, it exists :( >

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp: rest of refactoring, link rate fallback (rev2)

== Series Details == Series: drm/i915/dp: rest of refactoring, link rate fallback (rev2) URL : https://patchwork.freedesktop.org/series/22586/ State : failure == Summary == CC [M] drivers/gpu/drm/i915/gvt/display.o CC [M] drivers/gpu/drm/i915/gvt/edid.o LD drivers/rtc/built-in.o

[Intel-gfx] ✗ Fi.CI.BAT: failure for Classify the engines in class + instance (rev3)

== Series Details == Series: Classify the engines in class + instance (rev3) URL : https://patchwork.freedesktop.org/series/22535/ State : failure == Summary == CC [M] drivers/gpu/drm/i915/intel_lpe_audio.o LD drivers/usb/storage/usb-storage.o LD

[Intel-gfx] [PATCH v5] drm/i915/dp: Validate cached link rate and lane count before retraining

Currently intel_dp_check_link_status() tries to retrain the link if Clock recovery or Channel EQ for any of the lanes indicated by intel_dp->lane_count is not set. However these values cached in intel_dp structure can be stale if link training has failed for these values during previous modeset.

[Intel-gfx] [PATCH v3] drm/i915: Generate the engine name based on the instance number

Not really needed, but makes the next change a little bit more compact. v2: - Use zero-based numbering for engine names: xcs0, xcs1.. xcsN (Tvrtko, Chris) - Make sure the mock engine name is null-terminated (Tvrtko, Chris) v3: Because I'm stupid (Chris) Cc: Tvrtko Ursulin

[Intel-gfx] ✓ Fi.CI.BAT: success for Classify the engines in class + instance (rev2)

== Series Details == Series: Classify the engines in class + instance (rev2) URL : https://patchwork.freedesktop.org/series/22535/ State : success == Summary == Series 22535v2 Classify the engines in class + instance https://patchwork.freedesktop.org/api/1.0/series/22535/revisions/2/mbox/

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

On 04/06/2017 01:12 PM, Chris Wilson wrote: On Thu, Apr 06, 2017 at 05:55:43AM -0700, Oscar Mateo wrote: There are some properties that logically belong to the engine class, and some that belong to the engine instance. Make it explicit. v2: Commit message (Tvrtko) Cc: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Generate the engine name based on the instance number

On 04/06/2017 01:10 PM, Chris Wilson wrote: On Thu, Apr 06, 2017 at 05:55:42AM -0700, Oscar Mateo wrote: Not really needed, but makes the next change a little bit more compact. v2: - Use zero-based numbering for engine names: xcs0, xcs1.. xcsN (Tvrtko, Chris) - Make sure the mock

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

On Thu, Apr 06, 2017 at 05:55:43AM -0700, Oscar Mateo wrote: > There are some properties that logically belong to the engine class, and some > that belong to the engine instance. Make it explicit. > > v2: Commit message (Tvrtko) > > Cc: Tvrtko Ursulin > Cc: Paulo

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev2)

== Series Details == Series: series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev2) URL : https://patchwork.freedesktop.org/series/22607/ State : warning == Summary == Series 22607v2 Series without cover letter

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Generate the engine name based on the instance number

On Thu, Apr 06, 2017 at 05:55:42AM -0700, Oscar Mateo wrote: > Not really needed, but makes the next change a little bit more compact. > > v2: > - Use zero-based numbering for engine names: xcs0, xcs1.. xcsN (Tvrtko, > Chris) > - Make sure the mock engine name is null-terminated (Tvrtko,

[Intel-gfx] [PATCH 5/5] drm/i915: Use the engine class to get the context size

From: Daniele Ceraolo Spurio Technically speaking, the context size is per engine class, not per instance. v2: Add MISSING_CASE (Tvrtko) Cc: Paulo Zanoni Cc: Rodrigo Vivi Cc: Chris Wilson

[Intel-gfx] [PATCH 3/5] drm/i915: Generate the engine name based on the instance number

Not really needed, but makes the next change a little bit more compact. v2: - Use zero-based numbering for engine names: xcs0, xcs1.. xcsN (Tvrtko, Chris) - Make sure the mock engine name is null-terminated (Tvrtko, Chris) Cc: Tvrtko Ursulin Cc: Paulo Zanoni

[Intel-gfx] [PATCH 4/5] drm/i915: Split the engine info table in two levels, using class + instance

There are some properties that logically belong to the engine class, and some that belong to the engine instance. Make it explicit. v2: Commit message (Tvrtko) Cc: Tvrtko Ursulin Cc: Paulo Zanoni Cc: Rodrigo Vivi Cc:

[Intel-gfx] [PATCH 1/5] drm/i915: Classify the engines in class + instance

From: Daniele Ceraolo Spurio In such a way that vcs and vcs2 are just two different instances (0 and 1) of the same engine class (VIDEO_DECODE_CLASS). v2: Align the instance types (Tvrtko) Cc: Paulo Zanoni Cc: Rodrigo Vivi

[Intel-gfx] [PATCH 0/5] Classify the engines in class + instance (v2)

This refactoring helps simplify a few things here and there. Daniele Ceraolo Spurio (2): drm/i915: Classify the engines in class + instance drm/i915: Use the engine class to get the context size Oscar Mateo (3): drm/i915: Use the same vfunc for BSD2 ring init drm/i915: Generate the

[Intel-gfx] [PATCH 2/5] drm/i915: Use the same vfunc for BSD2 ring init

If we needed to do something different for the init functions, we could always look at the engine instance to make the distinction. But, in any case, the two functions are virtually identical already (please notice that BSD2_RING is only used from gen8 onwards). With this, the init functions

Re: [Intel-gfx] [PATCH 21/67] drm/i915/cnl: Update the context size

On Thu, Apr 06, 2017 at 12:15:17PM -0700, Rodrigo Vivi wrote: > From: Ben Widawsky > > The docs are not yet correct, so I cannot provide a reference to it. In the > current docs, the size is actually smaller than SKL. This seems unlikely given > that in another part

[Intel-gfx] [PATCH] x86/gpu: CNL uses the same GMS values as SKL

From: Paulo Zanoni So don't forget to reserve its stolen memory bits. v2: Adding right Cc. Cc: Ingo Molnar Cc: H. Peter Anvin Cc: Ander Conselvan de Oliveira Cc: x...@kernel.org Signed-off-by:

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm: Take mode_config.mutex in setcrtc ioctl (rev2)

== Series Details == Series: drm: Take mode_config.mutex in setcrtc ioctl (rev2) URL : https://patchwork.freedesktop.org/series/22605/ State : failure == Summary == Series 22605v2 drm: Take mode_config.mutex in setcrtc ioctl

[Intel-gfx] [PATCH i-g-t v1] igt_kms: Allow pipes with no cursor plane

A cursor plane may not always be available. Since there already exist variables that signal the existance or non-existance of cursor planes like pipe->plane_cursor and display->has_cursor_plane, allow the pipes that have no cursor plane. Signed-off-by: Robert Foss ---

[Intel-gfx] [PATCH 63/67] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

WC is apparently not an option for CNL+ on GTT here. Trying to use it we get hard hangs. Credits-to: Ben Widawsky Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[Intel-gfx] [PATCH 54/67] drm/i915/gen10: fix WM latency printing

From: Paulo Zanoni Gen 10 is just like Gen 9, so let's consider that all the future platforms are going to be like gen 9 instead of being like gen8-. Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi ---

[Intel-gfx] [PATCH 59/67] drm/i915/cnl: Fix Cannonlake scaler mode programing.

As Geminilake scalers Cannonlake also don't need and don't have the "high quality" mode programming. Cc: Ander Conselvan de Oliveira Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_atomic.c | 2 +- 1 file changed, 1

[Intel-gfx] [PATCH 36/67] drm/i915: Add MMIO helper for 6 ports with different offsets.

Also new registers can have different mmio offsets per different lane per port. v2: Use _PICK as PORT3 instead of creating a new macro with if per port. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 4 1 file changed, 4 insertions(+) diff

[Intel-gfx] [PATCH 39/67] drm/i915/cnl: Implement voltage swing sequence.

This is an important part of the DDI initalization as well as for changing the voltage during DisplayPort link training. This new sequence for Cannonlake is more like Broxton style but still with different registers, different table and different steps. v2: Do not write to DW4_GRP to avoid

[Intel-gfx] [PATCH 64/67] drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)

Wa for B-stepping only. A for a hang issue that requires throttling EU performace to 12.5% to avoid back pressure to thread dispatch Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h| 1 + drivers/gpu/drm/i915/intel_engine_cs.c | 4 2 files

[Intel-gfx] [PATCH 41/67] drm/i915/cnl: Add slice and subslice information to debugfs.

A missing part that maybe it is better to squash to commit "drm/i915/cnl: Configure EU slice power gating." later but before upstreaming it. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[Intel-gfx] [PATCH 47/67] drm/i915/cnl: Dump the right pll registers when dumping pipe config.

Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 8e669b6..7a2f1be 100644 ---

[Intel-gfx] [PATCH 50/67] drm/i915/gen10+: use the SKL code for reading WM latencies

From: Paulo Zanoni Gen 10 should use the exact same code as Gen 9, so change the check to take this into consideration, and also assume that future platforms will run this code. Also add a MISSING_CASE(), just in case we do something wrong, instead of silently failing.

[Intel-gfx] [PATCH 52/67] drm/i915/gen10: fix the gen 10 SAGV block time

From: Paulo Zanoni A previous commit added CNL to intel_has_sagv(), but forgot to adjust the SAGV block time to gen 10 platforms. Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi ---

[Intel-gfx] [PATCH 53/67] drm/i915/cnl: don't apply the GEN9/CNL:A WM WAs to CNL:B+

From: Paulo Zanoni TODO: Right now we only have 2 of the 4 WAs implemented. There's one missing for render decompression and another for transition watermarks. When we upstream this patch, let's check if those missing WAs are also implemented. We may also consider not

[Intel-gfx] [PATCH 37/67] drm/i915/cnl: Add registers related to voltage swing sequences.

This are the registers and bits needed for the voltage swing sequence on Cannonlake. v2: Remove CL_DW5 that was wrongly defined. v3: Use (1 << 1) instead of (1<<1) as Paulo suggested Change DW2 swing sel upper and lower macros to do the bit selection instead of definint a table that

[Intel-gfx] [PATCH 67/67] drm/i915/cnl: Adjust min pixel rate.

Cannonlake also needs to adjust the minimal pixel rate as gen9 platforms. Specially for the Azalia audio case. Cc: Dhinakaran Pandiyan Cc: Sanyog Kale Signed-off-by: Rodrigo Vivi ---

[Intel-gfx] [PATCH 33/67] drm/i915: Configure DPLL's for Cannonlake

From: "Kahola, Mika" DPLL's are defined in DPCLKA_CFGCR0 register (0x6C200). Let's use these definitions when computing dpll's for ddi ports. v2: (Rodrigo) Remove register that was defined in another patch with fixed name and more bits. Signed-off-by: Kahola, Mika

[Intel-gfx] [PATCH 48/67] drm/i915/cnl: Get DDI clock based on PLLs.

PLLs are the source clocks for the DDIs so in order to determine the ddi clock we need to check the PLL configuration. v2: Mika pointed out that 24 was hardcoded while it should consider ref clock that can be either 24KHz or 19.2KHz on CNL. Reviewed-by: Mika Kahola

[Intel-gfx] [PATCH 56/67] drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake.

Otherwise it reuses the ilk that has a completely different wm. Cc: Paulo Zanoni Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 45/67] drm/i915/cnl: Add max allowed Cannonlake DC.

This is a follow-up after enabling DC states with commit: "drm/i915/DMC/CNL: Load DMC on CNL". Cc: Anusha Srivatsa Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[Intel-gfx] [PATCH 15/67] drm/i915/cnl: Apply large line width optimization

From: Ben Widawsky This bit enables hardware that will change the approximation used for distances calculations for AA wide lines so that they are rendered more accurately. The default value for this bit leaves the legacy behavior. There is no good reason to not enable the

[Intel-gfx] [PATCH 02/67] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH

From: Dhinakaran Pandiyan The first two bytes of PCI ID for CNP_LP PCH are the same as that of SPT_LP. We should really be looking at the first 9 bits instead of the first 8 to identify platforms, although this seems to have not caused any problems on earlier

[Intel-gfx] [PATCH 22/67] drm/i915/cnl: Add RT cache flush pipe control w/a

From: Ben Widawsky Signed-off-by: Ben Widawsky Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_lrc.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git

[Intel-gfx] [PATCH 62/67] drm/i915/cnl: Add support slice/subslice/eu configs

From: Ben Widawsky Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_drv.h | 5 +++- drivers/gpu/drm/i915/i915_reg.h | 21 +++ drivers/gpu/drm/i915/intel_device_info.c | 45 +++- 3 files

[Intel-gfx] [PATCH 21/67] drm/i915/cnl: Update the context size

From: Ben Widawsky The docs are not yet correct, so I cannot provide a reference to it. In the current docs, the size is actually smaller than SKL. This seems unlikely given that in another part of the docs there are clearly more engines stored within the context

[Intel-gfx] [PATCH 42/67] drm/i915/DMC/CNL: Load DMC on CNL

From: Anusha Srivatsa This patch loads the DMC on CNL.The firmware version is 1.04. v2: (Rodrigo) Remove MODULE_FIRMWARE. Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa Signed-off-by: Rodrigo Vivi

[Intel-gfx] [PATCH 40/67] drm/i915/cnl: Enable loadgen_select bit for vswing sequence

From: Clint Taylor vswing programming sequence step 2 requires the Loadgen_select bit to be set in PORT_TX_DW4 lane reigsters per table defined by Bit rate and lane width. Implemented the change that was marked as FIXME in the driver. v2: (Rodrigo) checkpatch fixes.

[Intel-gfx] [PATCH 60/67] drm/i915/cnl: Enable fifo underrun for Cannonlake.

Also in a way that reuse bdw+ for all next platforms. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c

[Intel-gfx] [PATCH 29/67] drm/i915/cnl: Implement .set_cdclk() for CNL

From: Ville Syrjälä Add support for changing the cdclk frequency on CNL. Again, quite similar to BXT, but there are some annoying differences which means trying to share more code might not be feasible: * PLL ratio now lives in the PLL enable register * pcode came

[Intel-gfx] [PATCH 26/67] drm/i915/cnl: Add power wells for CNL

From: Ville Syrjälä CNL power wells are very similar to SKL, with the exception that the misc IO well has been split into separate AUX IO wells. Not sure if DMC is supposed to manage the AUX wells for us or not. Let's assume so for now. v2: DDI A power well wants

[Intel-gfx] [PATCH 12/67] drm/i915/cnl: Introduce initial Cannonlake Workarounds.

Let's inherit workarounds from previous platforms that according to wa_database and BSpec are still valid for Cannonlake. v2: Add missed workarounds. v3: Rebase Cc: Mika Kuoppala Signed-off-by: Rodrigo Vivi ---

[Intel-gfx] [PATCH 55/67] drm/i915/gen10: implement gen 10 watermarks calculations

From: Paulo Zanoni They're slightly different than the gen 9 calculations. TODO: before upstraming this, check if the spec is still the same. Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi ---

[Intel-gfx] [PATCH 46/67] drm/i915/cnl: Add allowed DP rates for Cannonlake.

One warning is that in order to get DPLL Link rates 3240 and 4050 that allows 648000 and 81 is that: "Some SKUs may require elevated I/O voltage to support this." v2: Rebase on top of source_rates changes. Signed-off-by: Rodrigo Vivi ---

[Intel-gfx] [PATCH 38/67] drm/i915/cnl: Add DDI Buffer translation tables for Cannonlake.

These tables are used on voltage wswing sequence initialization on Cannonlake. It is a complete new format now in use by the voltage swing team, not following any other standard in use by any other platform. Also the registers are different as well. So let's redefine the translation table for

[Intel-gfx] [PATCH 66/67] drm/i915/cnl: LSPCON support is gen9+

There is no platform specific change needed for LSPCON support on Cannonlake. So let's make it gen9+. Cc: Shashank Sharma Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[Intel-gfx] [PATCH 49/67] drm/i915/cnl: Avoid old DDI translation functions on Cannonlake.

Cannonlake uses a different swing voltage initalization sequence scheme that doesn't require these old functions. All other DDI, voltage swing and PLLs initialialization and configuration are already in place for Cannonlake. This patch only removes unecessary steps probably saving us from some

[Intel-gfx] [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL

All the low level cdclk bits are present, so let's add the required hooks to reconfigure cdclk on the fly. v2: Rebase due to cnl_sanitize_cdclk() v3: Rebased by Rodrigo on top of Ville's cdclk rework. v4: Rebase moving cnl_calc_cdclk up to follow same order as previous platforms.

[Intel-gfx] [PATCH 35/67] drm/i915/cnl: Enable wrpll computation for CNL

From: "Kahola, Mika" Enable wrpll computation for Cannonlake platform to support pll's required for HDMI output. The patch contains the following features - compute Cannonlake port clock programming dividers P, Q, and K. - compute PLL parameters for Cannonlake. These

[Intel-gfx] [PATCH 51/67] drm/i915/cnl: Enable SAGV for Cannonlake.

For now inherit from previous platforms. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a2b2509..20a0701 100644

[Intel-gfx] [PATCH 09/67] drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.

Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is also the new Spec style what makes the review much more easy and straightforward. v2: Really include the PCI IDs to the

[Intel-gfx] [PATCH 57/67] x86/gpu: CNL uses the same GMS values as SKL

From: Paulo Zanoni So don't forget to reserve its stolen memory bits. TODO: Cc the appropriate maintainers outside Intel before submitting the patch to the public mailing lists. Acked-by: Rodrigo Vivi Signed-off-by: Paulo Zanoni

[Intel-gfx] [PATCH 65/67] drm/i915/cnl: Enable Audio Pin Buffer.

Starting on CNL, we need to enable Audio Pin Buffer. By the spec it seems that this is part of audio programming, so let's give them the hability to set/unset this as needed. v2: With a hook so audio driver can control it. v3: Put back reg definition lost on v2. Cc: Jani Nikula

[Intel-gfx] [PATCH 34/67] drm/i915/cnl: Initialize PLLs

Although CNL follows PLL initialization more like Skylake than Broxton we have a completely different initialization sequence and registers used. One big difference from SKL is that CDCLK PLL is now exclusive (ADPLL) and for DDIs and MIPI we need to use DFGPLLs 0, 1 or 2. v2: Accept all Ander's

[Intel-gfx] [PATCH 58/67] drm/i915/cnl: Cannonlake color init.

Cannonlake has same color setup as Geminilake. Legacy color load luts doesn't work anymore on Cannonlake+. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/intel_color.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 4

[Intel-gfx] [PATCH 25/67] drm/i915/cnl: Inherit RPS stuff from previous platforms.

Apparently no change on RPS stuff from previous platforms. v2: Merging to rps related patches in one and also adding missed cases. Cc: David Weinehall Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_debugfs.c | 20

[Intel-gfx] [PATCH 16/67] drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipe

From: James Irwin Issue: VIZ-4525 Reviewed-by: Damien Lespiau Signed-off-by: James Irwin Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_device_info.c | 2 +- 1 file changed, 1

[Intel-gfx] [PATCH 06/67] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

As for BXT, PP_DIVISOR was removed from CNP PCH and power cycle delay has been moved to PP_CONTROL. Cc: Jani Nikula Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_dp.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-)

[Intel-gfx] [PATCH 19/67] drm/i915/cnl: Configure EU slice power gating.

Cannonlake also supports slice power gating on devices with more than one slice as SKL. Let's assume that this is the same for SKL+ and exclude BXT only. v2: Also remove KBL. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_device_info.c | 7 +++ 1 file

[Intel-gfx] [PATCH 18/67] drm/i915/cnl: Add initial gen10 golden states.

XXX: based on gen9 render commands at this point. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_gem_render_state.c | 2 + drivers/gpu/drm/i915/intel_renderstate.h | 1 +

[Intel-gfx] [PATCH 14/67] drm/i915/cnl: WaDisableEnhancedSBEVertexCaching

WA forTDS handle reallocation getting dropped by SDE, which may result in PS attribute corruption. Disable enhanced SBE vertex caching in COMMON_SLICE_CHICKEN2 offset. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_engine_cs.c | 4 1 file changed, 4

[Intel-gfx] [PATCH 20/67] drm/i915/cnl: Cannonlake has same MOCS table than Skylake.

All registers and default configuration are the same for Skylake and Cannonlake. v2: Don't apply Wa for platforms without MOCS. (Paulo) Cc: Paulo Zanoni Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_mocs.c | 6 +++--- 1 file

[Intel-gfx] [PATCH 61/67] drm/i915/cnl: Setup PAT Index.

Different from previous platforms, on CNL+ there's separated registers for separated indexes. v2: Remove comments regarding uncertainty around the table. v3: Remove extra line (by Ben) Cc: Clint Taylor Cc: Daniele Ceraolo Spurio

[Intel-gfx] [PATCH 10/67] drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.

By the Spec all CNL Y skus are 2+2, i.e. GT2. v2: Really include the PCI IDs to the picidlist[]; Reviewed-by: Anusha Srivatsa Signed-off-by: Rodrigo Vivi --- include/drm/i915_pciids.h | 12 +++- 1 file changed, 11 insertions(+), 1

[Intel-gfx] [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

From: Ville Syrjälä Add support for reading out the cdclk frequency from the hardware on CNL. Very similar to BXT, with a few new twists and turns: * the PLL is now called CDCLK PLL, not DE PLL * reference clock can be 24 MHz in addition to the 19.2 MHz BXT had *

[Intel-gfx] [PATCH 43/67] drm/i915: Use HAS_CSR instead of gen number on DMC load.

Since we have HAS_CSR tied to the platform definition let's use this instead of checking per platform. One less thing to worry when adding support to new platforms. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_csr.c | 2 +- 1 file changed, 1 insertion(+),

[Intel-gfx] [PATCH 11/67] drm/i915/cnl: add IS_CNL_REVID macro

From: Paulo Zanoni We're going to use it in the next commits. Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.h | 6 ++ 1 file changed, 6 insertions(+) diff --git

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