On Tue, May 16, 2017 at 05:13:58PM -0700, Michel Thierry wrote:
> On 16/05/17 00:54, Chris Wilson wrote:
> >On Mon, May 15, 2017 at 03:25:27PM -0700, Michel Thierry wrote:
> >>On 5/15/2017 2:47 PM, Chris Wilson wrote:
> >>>On Mon, May 15, 2017 at 10:31:58PM +0100, Chris Wilson wrote:
> On Mon,
== Series Details ==
Series: Enhancement to intel_dp_aux_backlight driver (rev7)
URL : https://patchwork.freedesktop.org/series/21086/
State : success
== Summary ==
Series 21086v7 Enhancement to intel_dp_aux_backlight driver
https://patchwork.freedesktop.org/api/1.0/series/21086/revisions/7/mb
Hi,
I'm using 4.12.0-rc1 from https://github.com/jwrdegoede/linux-sunxi and got
the following weird trace yesterday. Previously I've been getting output
similar to https://www.spinics.net/lists/intel-gfx/msg127638.html, some boots
on 4.12.0-rc1 I don't get any trace at all.
[ 2383.844192] per
On Tue, May 16, 2017 at 10:43:39PM +0200, Hans de Goede wrote:
> Hi,
>
> On 05/16/2017 09:55 PM, FKr wrote:
> > Hi,
> > I'm using 4.12.0-rc1 from https://github.com/jwrdegoede/linux-sunxi and got
> > the following weird trace yesterday. Previously I've been getting output
> > similar to https://ww
The patch does what it says.
Tested-by: Mika Kahola
Reviewed-by: Mika Kahola
On Thu, 2016-12-15 at 19:47 +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The scanline counter is bonkers on VLV/CHV DSI. The scanline counter
> increment is not lined up with the start of vbl
== Series Details ==
Series: drm/i915: Disable decoupled mmio for GEN9LP (rev2)
URL : https://patchwork.freedesktop.org/series/24470/
State : success
== Summary ==
Series 24470v2 drm/i915: Disable decoupled mmio for GEN9LP
https://patchwork.freedesktop.org/api/1.0/series/24470/revisions/2/mbox
On Tue, May 16, 2017 at 02:31:24PM -0700, Ben Widawsky wrote:
> This is the plumbing for supporting fb modifiers on planes. Modifiers
> have already been introduced to some extent, but this series will extend
> this to allow querying modifiers per plane. Based on this, the client to
> enable optima
On 17/05/2017 02:07, kai.c...@intel.com wrote:
From: Kai Chen
The decoupled mmio feature doesn't work as intended by HW team. Enabling
it with forcewake will only make debugging efforts more difficult, so
let's just simply remove it.
v2:
- Remove dead code related to GEN9LP decoupled mmio.
-
== Series Details ==
Series: Enhancement to intel_dp_aux_backlight driver (rev7)
URL : https://patchwork.freedesktop.org/series/21086/
State : success
== Summary ==
Series 21086v7 Enhancement to intel_dp_aux_backlight driver
https://patchwork.freedesktop.org/api/1.0/series/21086/revisions/7/mb
On Mon, May 15, 2017 at 05:06:09PM +, Michal Wajdeczko wrote:
> Usefulness of these stats was over-advertised.
>
> v2: remove duplicated engine stats (Chris)
>
> Suggested-by: Chris Wilson
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
> Cc: Daniele Ceraolo Spurio
I'm not hearing a
== Series Details ==
Series: drm/i915/guc: capture GuC logs if FW fails to load (rev5)
URL : https://patchwork.freedesktop.org/series/23982/
State : success
== Summary ==
Series 23982v5 drm/i915/guc: capture GuC logs if FW fails to load
https://patchwork.freedesktop.org/api/1.0/series/23982/re
On 15/05/2017 18:06, Michal Wajdeczko wrote:
Usefulness of these stats was over-advertised.
v2: remove duplicated engine stats (Chris)
Suggested-by: Chris Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_debugfs.c| 19
Hi,
Here are the changes from v12 :
* At Chris' recommendation, record sseu configuration per context &
engine (patch 3)
* In patch 8, request rpcs update on all engines (not just RCS)
* Drop previous device GET_PARAM ioctls. Those were confusing from
the userspace point of view,
From: Chris Wilson
We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, which is initially set
to the device default upon creation.
v2: record sseu configuration pe
From: Chris Wilson
When we query the available eu on each subslice, we currently only
report the max. It would also be useful to report the minimum found as
well.
When we set RPCS (power gating over the EU), we can also specify both
the min and max number of eu to configure on each slice; curren
From: Chris Wilson
Currently we only configure the power gating for Skylake and above, but
the configuration should equally apply to Broadwell and Braswell. Even
though, there is not as much variation as for later generations, we want
to expose control over the configuration to userspace and may
When monitoring a particular context, we also want to select what
engine we interested in monitoring as different engine can have
different sseu configurations. This is required because the reports
produced by the OA unit have to be interpreted using the
slice/subslice configuration.
Signed-off-by
From: Robert Bragg
An oa_exponent_to_ns() utility and per-gen timebase constants where
recently removed when updating the tail pointer race condition WA, and
this restores those so we can update the _PROP_OA_EXPONENT validation
done in read_properties_unlocked() to not assume we have a 12.5MHz
ti
Enables userspace to determine the number of slices & subslices
enabled and also know what specific slices & subslices are enabled.
This information is required, for example, to be able to analyse some
OA counter reports where the counter configuration depends on the HW
slice configuration.
Signed
From: Robert Bragg
Enables access to OA unit metrics for BDW, CHV, SKL and BXT which all
share (more-or-less) the same OA unit design.
Of particular note in comparison to Haswell: some OA unit HW config
state has become per-context state and as a consequence it is somewhat
more complicated to ma
Gen8+ might have mux configurations per slices/subslices. Depending on
whether slices/subslices have been fused off, only part of the
configuration needs to be applied. This change reworks the mux
configurations query mechanism to allow more than one set of registers
to be programmed.
Signed-off-b
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7b9fd9d0f5b8..1d9c75caa26a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i
From: Robert Bragg
Adds a static OA unit, MUX, B Counter + Flex EU configurations for basic
render metrics on Broadwell, Cherryview, Skylake and Broxton. These are
auto generated from an XML description of metric sets, currently
maintained in gputop, ref:
https://github.com/rib/gputop
> gputop
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile |3 +-
drivers/gpu/drm/i915/i915_oa_glk.c | 2600
drivers/gpu/drm/i915/i915_oa_glk.h | 38 +
drivers/gpu/drm/i915/i915_perf.c | 15 +-
4 files changed, 2654 insertions(+), 2 dele
From: Robert Bragg
In earlier iterations of the i915-perf driver we had a number of
callbacks/hooks from other parts of the i915 driver to e.g. notify us
when a legacy context was pinned and these could run asynchronously with
respect to the stream file operations and might also run in atomic
con
Chris Wilson writes:
> On Mon, May 15, 2017 at 11:52:55AM +0100, Chris Wilson wrote:
>> A long time ago, I wrote some selftests for the struct kfence idea. Now
>> that we have infrastructure in i915/igt for running kselftests, include
>> some for i915_sw_fence.
>>
>> Signed-off-by: Chris Wilson
Chris Wilson writes:
> A long time ago, I wrote some selftests for the struct kfence idea. Now
> that we have infrastructure in i915/igt for running kselftests, include
> some for i915_sw_fence.
>
> Signed-off-by: Chris Wilson
Only minor thing that caught my eye was that I would
have preferred:
Chris Wilson writes:
> Ville found a reference to WaMediaResetBeforeFullReset which we presume
> means that we should simply do the media reset first.
Yesterday I reordered the resets but I recall it didnt help.
I will retry but regardless yeah resetting media first makes
sense.
>
> References:
Chris Wilson writes:
> Repeat the reset a couple of times if at first we do not succeed.
>
> Signed-off-by: Chris Wilson
> Link:
> http://patchwork.freedesktop.org/patch/msgid/20170513083726.502-1-ch...@chris-wilson.co.uk
Seems that this is already merged but FWIW.
Reviewed-by: Mika Kuoppala
On Wed, 17 May 2017, Tvrtko Ursulin wrote:
> On 17/05/2017 02:07, kai.c...@intel.com wrote:
>> From: Kai Chen
>>
>> The decoupled mmio feature doesn't work as intended by HW team. Enabling
>> it with forcewake will only make debugging efforts more difficult, so
>> let's just simply remove it.
>>
On Tue, May 16, 2017 at 02:19:12PM -0700, Ben Widawsky wrote:
> On 17-05-03 17:08:27, Daniel Vetter wrote:
> > On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
> > > +struct drm_format_modifier_blob {
> > > +#define FORMAT_BLOB_CURRENT 1
> > > + /* Version of this blob format */
> > >
Arkadiusz Hiler writes:
> This basically reverts commit 465418c6064c
> ("drm/i915/gen9: Remove WaEnableYV12BugFixInHalfSliceChicken7")
> with small addition - marking it as affecting KBL as well.
>
> It was incorrectly considered fixed in production steppings.
>
> References: HSD#2126385, HSD#213
On Tue, May 16, 2017 at 04:38:01PM +0300, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > Ville found a reference to WaMediaResetBeforeFullReset which we presume
> > means that we should simply do the media reset first.
>
> Yesterday I reordered the resets but I recall it didnt help.
> I will
Ville Syrjälä writes:
> On Tue, May 16, 2017 at 04:38:01PM +0300, Mika Kuoppala wrote:
>> Chris Wilson writes:
>>
>> > Ville found a reference to WaMediaResetBeforeFullReset which we presume
>> > means that we should simply do the media reset first.
>>
>> Yesterday I reordered the resets but I
On Wed, May 17, 2017 at 12:36:35PM +0300, Ville Syrjälä wrote:
> On Tue, May 16, 2017 at 10:43:39PM +0200, Hans de Goede wrote:
> > Hi,
> >
> > On 05/16/2017 09:55 PM, FKr wrote:
> > > Hi,
> > > I'm using 4.12.0-rc1 from https://github.com/jwrdegoede/linux-sunxi and
> > > got
> > > the following
On Tue, May 16, 2017 at 04:55:29PM +0300, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > Repeat the reset a couple of times if at first we do not succeed.
> >
> > Signed-off-by: Chris Wilson
> > Link:
> > http://patchwork.freedesktop.org/patch/msgid/20170513083726.502-1-ch...@chris-wilson.co.
This series implements new DDB allocation algorithm to solve the cases,
where we have sufficient DDB available to enable multiple planes, But
due to the current algorithm not dividing it properly among planes, we
end-up failing the flip.
It also takes care of enabling same watermark level for each
From: "Kumar, Mahesh"
fixed_16_16_div_round_up(_u64), wrapper for fixed_16_16 division
operation don't really round_up the result. Wrapper round_up only the
fraction part of the result to make it 16-bit.
This patch eliminates round_up keyword from the wrapper.
Later patch will introduce the new
From: "Kumar, Mahesh"
This patch adds few wrapper to perform fixed_point_16_16 operations
mul_round_up_u32_fixed16 : Multiplies u32 and fixed_16_16_t variables
& returns u32 result with rounding-up.
mul_fixed16 : Multiplies two fixed_16_16_t variable & returns fixed_16_
From: "Kumar, Mahesh"
This patch make changes to calculate adjusted plane pixel rate &
plane downscale amount using fixed_point functions available.
This patch will give uniformity in code, & will help to avoid mixing of
32bit uint32_t variable for fixed-16.16 with fixed_16_16_t variables in
late
From: "Kumar, Mahesh"
Don't use fixed_16_16 structure members directly, instead use wrapper to
perform fixed_16_16 division operation.
Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions
From: "Kumar, Mahesh"
We are already doing memset of ddb structure at the begining of
skl_allocate_pipe_ddb
function, No need to again do a memset.
Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 4 +---
1 file changed
From: "Kumar, Mahesh"
Fail the flip if no FB is present but plane_state is set as visible.
Above is not a valid combination so instead of continue fail the flip.
Signed-off-by: Mahesh Kumar
Reviewed-by: Matt Roper
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_pm.c | 3 ++-
1
From: "Kumar, Mahesh"
DDB minimum requirement of crtc configuration (cumulative of all the
enabled planes in crtc) may exceed the allocated DDB for crtc/pipe.
This patch make changes to fail the flip/ioctl if minimum requirement
for pipe exceeds the total ddb allocated to the pipe.
Previously it
From: "Kumar, Mahesh"
Instead of iterating over planes & wm levels in a single function use
skl_compute_wm_level function to interate over WM levels.
Change name of function to skl_compute_wm_levels (Matt).
These changes are to clean-up WM code & will help in making only new
ddb algorithm relate
From: "Kumar, Mahesh"
This patch cleanup/reorganises the watermark calculation functions.
This patch make use of already available macro
"drm_atomic_crtc_state_for_each_plane_state" to walk through
plane_state list instead of calculating plane_state in function itself.
This restructuring will he
From: "Kumar, Mahesh"
This patch make changes to use linetime latency if allocated
DDB size during plane watermark calculation is not available.
linetime is the time, display engine takes to fetch one line worth of
pixels with given pixel clock rate.
This is required to implement new DDB allocati
From: "Kumar, Mahesh"
This patch implements new DDB allocation algorithm as per HW team
recommendation. This algo takecare of scenario where we allocate less DDB
for the planes with lower relative pixel rate, but they require more DDB
to work.
It also takes care of enabling same watermark level f
From: "Kumar, Mahesh"
A display resolution is only supported if it meets all the restrictions
below for Maximum Pipe Pixel Rate.
The display resolution must fit within the maximum pixel rate output
from the pipe. Make sure that the display pipe is able to feed pixels at
a rate required to suppor
On Tue, May 16, 2017 at 04:38:01PM +0300, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > Ville found a reference to WaMediaResetBeforeFullReset which we presume
> > means that we should simply do the media reset first.
>
> Yesterday I reordered the resets but I recall it didnt help.
> I will
My original intention was for i915_sw_fence to be the base class and
provide the reference count for the container. This was from starting
with a design to handle async_work. In practice, for i915 we embed
fences into structs which have their own independent reference counting,
making the i915_sw_f
If we *know* that the engine is idle, i.e. we have not more contexts in
flight, we can skip any spurious CSB idle interrupts. These spurious
interrupts seem to arrive long after we assert that the engines are
completely idle, triggering later assertions:
[ 178.896646] intel_engine_is_idle(bcs): i
A long time ago, I wrote some selftests for the struct kfence idea. Now
that we have infrastructure in i915/igt for running kselftests, include
some for i915_sw_fence.
v2: INIT_WORK_ONSTACK/destroy_work_on_stack (Mika)
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/
Rebrand the current (pointer | bits) pack/unpack utility macros as
explicit bit twiddling for PAGE_SIZE so that we can use the more
flexible underlying macros for different bits.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +-
drivers
add/remove: 1/1 grow/shrink: 5/4 up/down: 391/-578 (-187)
function old new delta
execlists_submit_ports 262 471+209
port_assign.isra - 136+136
capture 63
ptr_unpack_bits() is a function-like macro, as such it is meant to be
replaceable by a function. In this case, we should be passing in the
out-param as a pointer.
Bizarrely this does affect code generation:
function old new delta
i915_gem_object_pin_map
The i915_priolist are allocated within an atomic context on a path where
we wish to minimise latency. If we use a dedicated kmem_cache, we have
the advantage of a local freelist from which to service new requests
that should keep the latency impact of an allocation small. Though
currently we expect
Explicitly assign the default priority, and give it a name. After much
discussion, we have chosen to call it I915_PRIORITY_NORMAL!
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_context.c | 1 +
drivers/gpu/drm/i915/i915_gem_request.h | 1 +
2 files cha
All the requests at the same priority are executed in FIFO order. They
do not need to be stored in the rbtree themselves, as they are a simple
list within a level. If we move the requests at one priority into a list,
we can then reduce the rbtree to the set of priorities. This should keep
the heigh
If we do not require to perform priority bumping, and we haven't yet
submitted the request, we can update its priority in situ and skip
acquiring the engine locks -- thus avoiding any contention between us
and submit/execute.
v2: Remove the stack element from the list if we can do the early
assign
As the handler is now quite complex, involving a few atomics, the cost
of the function preamble is negligible in comparison and so we should
leave the function out-of-line for better I$.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
1 file ch
Since we coordinate with the execlists tasklet using a locked schedule
operation that ensures that after we set the engine->irq_posted we
always have an invocation of the tasklet, we do not need to use a locked
operation to set the engine->irq_posted itself.
Signed-off-by: Chris Wilson
Reviewed-b
The dma_buf_vmap in itself warns on error and then downgrades
the return value from error ptr to NULL. Don't try to decode error
value from the return in our test.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/selftests/i915_gem_dmabuf.c | 6 +++---
1 file changed, 3 in
On Wed, May 17, 2017 at 03:41:49PM +0300, Mika Kuoppala wrote:
> The dma_buf_vmap in itself warns on error and then downgrades
> the return value from error ptr to NULL. Don't try to decode error
> value from the return in our test.
>
Actually dma_buf_vmap shouldn't be WARNing here, so go fix tha
== Series Details ==
Series: Implement DDB algorithm and WM cleanup (rev8)
URL : https://patchwork.freedesktop.org/series/20376/
State : success
== Summary ==
Series 20376v8 Implement DDB algorithm and WM cleanup
https://patchwork.freedesktop.org/api/1.0/series/20376/revisions/8/mbox/
Test ge
Older gen use a physical address for the hardware status page, for which
we use cache-coherent writes. As the writes are into the cpu cache, we use
a normal WB mapped page to read the HWS, used for our seqno tracking.
Anecdotally, I observed lost breadcrumbs writes into the HWS on i965gm,
which so
This reverts commit bc5ca47c0af4f949ba889e666b7da65569e36093.
Gabriel put this back into generic code with
commit 75f6dfe3e652e1adef8cc1b073c89f3e22103a8f
Author: Gabriel Krisman Bertazi
Date: Wed Dec 28 12:32:11 2016 -0200
drm: Deduplicate driver initialization message
but somehow he mi
On Wed, May 17, 2017 at 03:15:57PM +0200, Daniel Vetter wrote:
> This reverts commit bc5ca47c0af4f949ba889e666b7da65569e36093.
>
> Gabriel put this back into generic code with
>
> commit 75f6dfe3e652e1adef8cc1b073c89f3e22103a8f
> Author: Gabriel Krisman Bertazi
> Date: Wed Dec 28 12:32:11 2016
== Series Details ==
Series: series starting with [CI,01/12] drm/i915: Remove kref from i915_sw_fence
URL : https://patchwork.freedesktop.org/series/24560/
State : success
== Summary ==
Series 24560v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/24560/revisions/
== Series Details ==
Series: drm/i915/selftest: Fix dma_buf_vmap error handling
URL : https://patchwork.freedesktop.org/series/24561/
State : success
== Summary ==
Series 24561v1 drm/i915/selftest: Fix dma_buf_vmap error handling
https://patchwork.freedesktop.org/api/1.0/series/24561/revisions
On Wed, May 17, 2017 at 01:38:07PM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,01/12] drm/i915: Remove kref from
> i915_sw_fence
> URL : https://patchwork.freedesktop.org/series/24560/
> State : success
>
> == Summary ==
>
> Series 24560v1 Series withou
Daniel Vetter writes:
> This reverts commit bc5ca47c0af4f949ba889e666b7da65569e36093.
>
> Gabriel put this back into generic code with
>
> commit 75f6dfe3e652e1adef8cc1b073c89f3e22103a8f
> Author: Gabriel Krisman Bertazi
> Date: Wed Dec 28 12:32:11 2016 -0200
>
> drm: Deduplicate driver in
New version of [1] with DPCD OUI etc. reading moved from i915 to DP
helpers, and the quirks based on that. Helps improve the documentation
that Daniel longed for.
BR,
Jani.
[1] 20170511095721.7392-1-jani.nikula@intel.com">http://mid.mail-archive.com/20170511095721.7392-1-jani.nikula@intel.com
Face the fact, there are Display Port sink and branch devices out there
in the wild that don't follow the Display Port specifications, or they
have bugs, or just otherwise require special treatment. Start a common
quirk database the drivers can query based on the DP device
identification. At least
Switch to using the common DP helpers instead of using our own.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 37 -
drivers/gpu/drm/i915/intel_drv.h| 5 +
drivers/gpu/drm/i915/intel_lspcon.c | 2 +-
3 files changed, 6 insertion
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 35 +++
include/drm/drm_dp_helper.h | 19 +++
2 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 3e5f52110ea1..
The Analogix 7737 DP to HDMI converter requires reduced M and N values
when to operate correctly at HBR2. Detect this IC by its OUI value of
0x0022B9 via the DPCD quirk list.
v2 by Jani: Rebased on the DP quirk database
v3 by Jani: Rebased on the reworked DP quirk database
Fixes: 9a86cda07af2 ("
Chris Wilson writes:
> On Wed, May 17, 2017 at 03:41:49PM +0300, Mika Kuoppala wrote:
>> The dma_buf_vmap in itself warns on error and then downgrades
>> the return value from error ptr to NULL. Don't try to decode error
>> value from the return in our test.
>>
>
> Actually dma_buf_vmap shouldn'
== Series Details ==
Series: Revert "drm/i915: Restore lost "Initialized i915" welcome message"
URL : https://patchwork.freedesktop.org/series/24563/
State : success
== Summary ==
Series 24563v1 Revert "drm/i915: Restore lost "Initialized i915" welcome
message"
https://patchwork.freedesktop.o
Currently, we only mark the CPU cache as dirty if we skip a clflush.
This leads to some confusion where we have to ask if the object is in
the write domain or missed a clflush. If we always mark the cache as
dirty, this becomes a much simply question to answer.
The goal remains to do as few clflus
== Series Details ==
Series: drm/dp: device identification and quirks
URL : https://patchwork.freedesktop.org/series/24566/
State : success
== Summary ==
Series 24566v1 drm/dp: device identification and quirks
https://patchwork.freedesktop.org/api/1.0/series/24566/revisions/1/mbox/
Test gem_e
On Wed, May 17, 2017 at 1:31 PM, Daniel Vetter wrote:
> On Tue, May 16, 2017 at 02:19:12PM -0700, Ben Widawsky wrote:
>> On 17-05-03 17:08:27, Daniel Vetter wrote:
>> > On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
>> > > +struct drm_format_modifier_blob {
>> > > +#define FORMAT_BL
== Series Details ==
Series: drm/i915: Mark CPU cache as dirty on every transition for CPU writes
URL : https://patchwork.freedesktop.org/series/24569/
State : success
== Summary ==
Series 24569v1 drm/i915: Mark CPU cache as dirty on every transition for CPU
writes
https://patchwork.freedeskt
From: Tvrtko Ursulin
Building on top of the previous patch which exported the concept
of engine classes and instances, we can also use this instead of
the current awkward engine selection uAPI.
This is primarily interesting for the VCS engine selection which
is a) currently done via disjoint set
On Wed, May 17, 2017 at 04:40:57PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Building on top of the previous patch which exported the concept
> of engine classes and instances, we can also use this instead of
> the current awkward engine selection uAPI.
>
> This is primarily intere
Chris,
This patch works now as we unconditionally set cache_dirty
in set_cache_level function.
Tested-by: Dongwon Kim
On Wed, May 17, 2017 at 04:05:24PM +0100, Chris Wilson wrote:
> Currently, we only mark the CPU cache as dirty if we skip a clflush.
> This leads to some confusion where we hav
On Tue, 2017-05-16 at 17:39 -0700, Puthikorn Voravootivat wrote:
>
>
> On Tue, May 16, 2017 at 2:21 PM, Pandiyan, Dhinakaran
> wrote:
> On Tue, 2017-05-16 at 13:56 -0700, Puthikorn Voravootivat
> wrote:
> >
> >
> > On Tue, May 16, 2017 at 1:29 PM, Pandiyan
On Tue, May 16, 2017 at 06:52:17PM -0700, Manasi Navare wrote:
> On Tue, May 16, 2017 at 10:27:33PM -0300, Gabriel Krisman Bertazi wrote:
> > Manasi Navare writes:
> >
> > Hi Manasi,
> >
> > > So the purpose of this patch is to avoid overwriting the no_fbc_reason
> > > field during atomic_check
On Thu, Apr 06, 2017 at 12:15:32PM -0700, Rodrigo Vivi wrote:
> Also new registers can have different mmio offsets
> per different lane per port.
>
> v2: Use _PICK as PORT3 instead of creating a new
> macro with if per port.
>
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_
On Tue, 2017-05-16 at 17:34 -0700, Puthikorn Voravootivat wrote:
> Read desired PWM frequency from panel vbt and calculate the
> value for divider in DPCD address 0x724 and 0x728 to have
> as many bits as possible for PWM duty cyle for granularity of
> brightness adjustment while the frequency divi
From: Puthikorn Voravootivat [put...@google.com] on behalf of Puthikorn
Voravootivat [put...@chromium.org]
Sent: Tuesday, May 16, 2017 5:33 PM
To: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
Cc: dri-de...@lists.freedesktop.org; Jani Nikula; Navar
Set the class on our mock pci device to GFX. This should be useful for
utilities like intel-iommu that special case gfx devices.
References: https://bugs.freedesktop.org/show_bug.cgi?id=101080
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 1 +
1 file changed,
On Tue, 2017-05-16 at 17:34 -0700, Puthikorn Voravootivat wrote:
> This patch adds option to enable dynamic backlight for eDP
> panel that supports this feature via DPCD register and
> set minimum / maximum brightness to 0% and 100% of the
> normal brightness.
>
> Signed-off-by: Puthikorn Voravoot
Similar code was duplicated in ringbuffer.c and lrc.c
Lets share the code and move it to engine_cs.c
While around, move execlist enabling into separate inline
function, as this will make future patches simpler.
Suggested-by: Chris Wilson
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
Cc: Osca
== Series Details ==
Series: drm/i915/selftests: Pretend to be a gfx pci device
URL : https://patchwork.freedesktop.org/series/24580/
State : failure
== Summary ==
Series 24580v1 drm/i915/selftests: Pretend to be a gfx pci device
https://patchwork.freedesktop.org/api/1.0/series/24580/revisions
Before reseting an engine, check if there is an active request, and if
the _hung_ request has completed. In these two cases, the seqno has moved
after hang declaration and we can skip the reset.
Also store the active request so that we only search for it once, this
applies for reset-engine and ful
I like the approach.
BR,
Anusha
>-Original Message-
>From: Mateo Lozano, Oscar
>Sent: Friday, May 5, 2017 6:23 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Mateo Lozano, Oscar ; Srivatsa, Anusha
>; Ceraolo Spurio, Daniele
>; Chris Wilson
>Subject: [PATCH 1/2] drm/i915/guc: Get rid of the
On Wed, May 17, 2017 at 01:41:34PM -0700, Michel Thierry wrote:
> @@ -2827,21 +2829,35 @@ int i915_gem_reset_prepare_engine(struct
> intel_engine_cs *engine)
>
> if (engine_stalled(engine)) {
> request = i915_gem_find_active_request(engine);
> - if (request && req
== Series Details ==
Series: drm/i915: Move engine HWS setup into one shared function
URL : https://patchwork.freedesktop.org/series/24581/
State : success
== Summary ==
Series 24581v1 drm/i915: Move engine HWS setup into one shared function
https://patchwork.freedesktop.org/api/1.0/series/245
On Wed, May 17, 2017 at 1:09 PM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:
>
>
> From: Puthikorn Voravootivat [put...@google.com] on behalf of Puthikorn
> Voravootivat [put...@chromium.org]
> Sent: Tuesday, May 16, 2017 5:33 PM
> To: inte
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