[Intel-gfx] igt/kms_rotation_crc: Add horizontal flip subtest.

Test that horizontal flip works with supported rotations. Includes a fix for the unrotated fb which was not being positioned correctly with portrait and landscape rectangles. Signed-off-by: Joseph Garvey --- lib/igt_kms.c| 2 +- lib/igt_kms.h|

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for GuC Fixes, Minor restructuring changes and v9+ logging change

Test kms_flip: Subgroup modeset-vs-vblank-race: pass -> FAIL (shard-hsw) https://bugs.freedesktop.org/show_bug.cgi?id=102917 -Original Message- From: Patchwork [mailto:patchw...@emeril.freedesktop.org] Sent: Thursday, September 21, 2017 2:25 AM To:

[Intel-gfx] ✗ Fi.CI.BAT: warning for igt/kms_psr_sink_crc: Fix regression in psr_drrs subtest

== Series Details == Series: igt/kms_psr_sink_crc: Fix regression in psr_drrs subtest URL : https://patchwork.freedesktop.org/series/30683/ State : warning == Summary == IGT patchset tested on top of latest successful build 6e2622564dc85875ee9e2f22874f9607cf0cdd9c meson: share the

[Intel-gfx] [igt] igt/kms_psr_sink_crc: Fix regression in psr_drrs subtest

The substring to be matched is modified to reflect kernel code. Fixes: 33355210a43e (igt/kms_psr_sink_crc: Add psr_drrs subtest) Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Signed-off-by: Radhakrishna Sripada

[Intel-gfx] ✓ Fi.CI.IGT: success for scripts/run-tests.sh: Look for test-lists.txt in 'build' as well

== Series Details == Series: scripts/run-tests.sh: Look for test-lists.txt in 'build' as well URL : https://patchwork.freedesktop.org/series/30665/ State : success == Summary == Test kms_setmode: Subgroup basic: fail -> PASS (shard-hsw) fdo#99912 Test

Re: [Intel-gfx] [PATCH 4/5] drm/i915/dp: Clean up intel_dp_check_mst_status

On Wed, Sep 20, 2017 at 3:47 PM, Pandiyan, Dhinakaran wrote: > On Wed, 2017-09-20 at 13:02 -0700, Ausmus, James wrote: >> On Wed, Sep 20, 2017 at 12:55 PM, Pandiyan, Dhinakaran >> wrote: >> > On Wed, 2017-09-20 at 12:11 -0700, Ausmus,

Re: [Intel-gfx] [PATCH][drm-next] drm/i915/gvt: ensure -ve return value is handled correctly

On 2017.09.19 19:35:23 -0700, Joe Perches wrote: > On Wed, 2017-09-20 at 05:46 +0800, Zhenyu Wang wrote: > > On 2017.09.19 16:55:34 +0100, Colin King wrote: > > > From: Colin Ian King > > > > > > An earlier fix changed the return type from find_bb_size however the > > >

Re: [Intel-gfx] [PATCH 4/5] drm/i915/dp: Clean up intel_dp_check_mst_status

On Wed, 2017-09-20 at 13:02 -0700, Ausmus, James wrote: > On Wed, Sep 20, 2017 at 12:55 PM, Pandiyan, Dhinakaran > wrote: > > On Wed, 2017-09-20 at 12:11 -0700, Ausmus, James wrote: > >> On Mon, Sep 18, 2017 at 3:21 PM, Dhinakaran Pandiyan > >>

Re: [Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink

On Wed, Sep 20, 2017 at 02:32:34PM +, vathsala nagaraju wrote: > Add defines for dpcd register 2009 (synchronization latency > in sink). > > Cc: Rodrigo Vivi > CC: Puthikorn Voravootivat > Signed-off-by: Vathsala Nagaraju

Re: [Intel-gfx] [PATCH v4 6/9] drm/i915/guc: Fix GuC cleanup in unload path

On Wed, 20 Sep 2017 19:38:21 +0200, Sagar Arun Kamble wrote: We ensure that GuC is completely suspended and client is destroyed in i915_gem_suspend during i915_driver_unload. So now intel_uc_fini_hw should just take care of cleanup, hence

Re: [Intel-gfx] [PATCH v4 5/9] drm/i915/guc: Disable GuC submission and suspend it prior to i915 reset

On Wed, 20 Sep 2017 19:38:20 +0200, Sagar Arun Kamble wrote: Before i915 reset we need to disable GuC submission and suspend GuC operarions as it is recreated during intel_uc_init_hw. We can't reuse the ^^ intel_uc_suspend functionality as reset path

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs

== Series Details == Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs URL : https://patchwork.freedesktop.org/series/30669/ State : failure == Summary == Test kms_flip: Subgroup modeset-vs-vblank-race: pass -> FAIL

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/kbl: Change a KBL pci id to GT2 from GT1.5

On Wed, Sep 20, 2017 at 2:34 PM, Rodrigo Vivi wrote: > On Wed, Sep 20, 2017 at 08:31:26PM +, Anuj Phogat wrote: >> See Mesa commit 9c588ff >> >> Cc: Matt Turner >> Cc: Rodrigo Vivi >> Signed-off-by: Anuj Phogat

Re: [Intel-gfx] [PATCH libdrm V2 2/2] intel: Change a KBL pci id to GT2 from GT1.5

On Wed, Sep 20, 2017 at 07:11:03PM +, Anuj Phogat wrote: > See Mesa commit 9c588ff > > Cc: Matt Turner > Cc: Rodrigo Vivi > Signed-off-by: Anuj Phogat Reviewed-by: Rodrigo Vivi > --- >

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/kbl: Change a KBL pci id to GT2 from GT1.5

On Wed, Sep 20, 2017 at 08:31:26PM +, Anuj Phogat wrote: > See Mesa commit 9c588ff > > Cc: Matt Turner > Cc: Rodrigo Vivi > Signed-off-by: Anuj Phogat Reviewed-by: Rodrigo Vivi > --- >

Re: [Intel-gfx] [PATCH v4 3/9] drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication across RPM suspend/resume

On Wed, 20 Sep 2017 19:38:18 +0200, Sagar Arun Kamble wrote: Apart from configuring interrupts, we need to update the ggtt invalidate interface and GuC communication on suspend. This functionality can be reused for other suspend and reset paths. Prepared GuC

Re: [Intel-gfx] [PATCH v4 2/9] drm/i915/guc: Update prototype/name of GuC suspend/resume fns and move to intel_uc.c

On Wed, 20 Sep 2017 19:38:17 +0200, Sagar Arun Kamble wrote: Renamed intel_guc_suspend to intel_guc_enter_sleep and intel_guc_resume to intel_guc_exit_sleep to match GuC nomenclature compatibility. We plan to use intel_guc_suspend and intel_guc_resume through

Re: [Intel-gfx] [PATCH v4 7/9] drm/i915/guc: Remove i915_guc_log_unregister

On Wed, 20 Sep 2017 19:38:22 +0200, Sagar Arun Kamble wrote: Functionality needed to disable GuC interrupts and cleanup the runtime/relay data structures is already covered in the unload path via intel_guc_fini_hw and intel_guc_cleanup hence remove

[Intel-gfx] ✗ Fi.CI.IGT: failure for GuC Fixes, Minor restructuring changes and v9+ logging change

== Series Details == Series: GuC Fixes, Minor restructuring changes and v9+ logging change URL : https://patchwork.freedesktop.org/series/30666/ State : failure == Summary == Test kms_flip: Subgroup modeset-vs-vblank-race: pass -> FAIL (shard-hsw) Test

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/kbl: Remove unused Kabylake pci ids (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/kbl: Remove unused Kabylake pci ids (rev2) URL : https://patchwork.freedesktop.org/series/30151/ State : failure == Summary == CHK include/config/kernel.release CHK include/generated/uapi/linux/version.h CHK

[Intel-gfx] [PATCH v2 2/2] drm/i915/kbl: Change a KBL pci id to GT2 from GT1.5

See Mesa commit 9c588ff Cc: Matt Turner Cc: Rodrigo Vivi Signed-off-by: Anuj Phogat --- include/drm/i915_pciids.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drm/i915_pciids.h

Re: [Intel-gfx] [PATCH libdrm 2/2] intel: Change a KBL pci id to GT2 from GT1.5

On Wed, Sep 20, 2017 at 12:13 PM, Anuj Phogat wrote: > Any comments on this one. Sent out v2 after dropping > [PATCH 1/2] drm/i915/kbl: Remove unused Kabylake pci ids Correction. Dropped patch for libdrm is: [PATCH libdrm 1/2] intel: Remove unused Kabylake pci ids > > On

Re: [Intel-gfx] [PATCH libdrm 1/2] intel: Remove unused Kabylake pci ids

Dropping this patch. On Mon, Sep 11, 2017 at 9:22 AM, Anuj Phogat wrote: > These PCI IDs are not used in any Kabylake SKUs. > See Mesa commits: ebc5ccf and b2dae9f > > Cc: Matt Turner > Cc: Rodrigo Vivi > Signed-off-by: Anuj

Re: [Intel-gfx] [RFC 04/10] drm/i915: Expose a PMU interface for perf queries

Hi Peter, could you, please, comment on below? -Original Message- From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of Rogozhkin, Dmitry V Sent: Wednesday, September 13, 2017 4:06 PM To: pet...@infradead.org Cc: Intel-gfx@lists.freedesktop.org Subject: Re:

[Intel-gfx] ✓ Fi.CI.BAT: success for scripts/run-tests.sh: Look for test-lists.txt in 'build' as well

== Series Details == Series: scripts/run-tests.sh: Look for test-lists.txt in 'build' as well URL : https://patchwork.freedesktop.org/series/30665/ State : success == Summary == IGT patchset tested on top of latest successful build 6e2622564dc85875ee9e2f22874f9607cf0cdd9c meson: share the

Re: [Intel-gfx] [PATCH 4/5] drm/i915/dp: Clean up intel_dp_check_mst_status

On Wed, Sep 20, 2017 at 12:55 PM, Pandiyan, Dhinakaran wrote: > On Wed, 2017-09-20 at 12:11 -0700, Ausmus, James wrote: >> On Mon, Sep 18, 2017 at 3:21 PM, Dhinakaran Pandiyan >> wrote: >> > Rewriting this code without the goto, I

Re: [Intel-gfx] [PATCH 4/5] drm/i915/dp: Clean up intel_dp_check_mst_status

On Wed, 2017-09-20 at 12:11 -0700, Ausmus, James wrote: > On Mon, Sep 18, 2017 at 3:21 PM, Dhinakaran Pandiyan > wrote: > > Rewriting this code without the goto, I believe, makes it more readable. > > One functional change that has been included is the handling of

Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

On 09/20/2017 11:35 AM, Rodrigo Vivi wrote: CNL adds an extra register for slice/subslice information. Although no SKU is planed with an extra slice let's already handle this extra piece of information so we don't have the risk in future of getting a part that might have chosen this part of

[Intel-gfx] ✗ Fi.CI.BAT: failure for tests/kms_cursor_legacy: Use gem_mmap__gtt() rather than gem_mmap__wc()

== Series Details == Series: tests/kms_cursor_legacy: Use gem_mmap__gtt() rather than gem_mmap__wc() URL : https://patchwork.freedesktop.org/series/30664/ State : failure == Summary == IGT patchset tested on top of latest successful build 6e2622564dc85875ee9e2f22874f9607cf0cdd9c meson: share

Re: [Intel-gfx] [PATCH libdrm 2/2] intel: Change a KBL pci id to GT2 from GT1.5

Any comments on this one. Sent out v2 after dropping [PATCH 1/2] drm/i915/kbl: Remove unused Kabylake pci ids On Mon, Sep 11, 2017 at 9:22 AM, Anuj Phogat wrote: > See Mesa commit 9c588ff > > Cc: Matt Turner > Cc: Rodrigo Vivi

Re: [Intel-gfx] [PATCH 4/5] drm/i915/dp: Clean up intel_dp_check_mst_status

On Mon, Sep 18, 2017 at 3:21 PM, Dhinakaran Pandiyan wrote: > Rewriting this code without the goto, I believe, makes it more readable. > One functional change that has been included is the handling of failed ESI > register reads. Instead of disabling MST only for

[Intel-gfx] [PATCH libdrm V2 2/2] intel: Change a KBL pci id to GT2 from GT1.5

See Mesa commit 9c588ff Cc: Matt Turner Cc: Rodrigo Vivi Signed-off-by: Anuj Phogat --- intel/intel_chipset.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/intel/intel_chipset.h

Re: [Intel-gfx] force yuv 4:2:0 output

I've tried v4.14-rc1. Now I do not have 4k@60 anymore. dmesg with drm.debug: http://sprunge.us/TKbO Best Regards, Wolfgang Jani Nikula schrieb am Di., 19. Sep. 2017 um 12:08 Uhr: > On Mon, 18 Sep 2017, Wolfgang Haupt wrote: > > Hello

Re: [Intel-gfx] [PATCH 1/2] drm/i915/kbl: Remove unused Kabylake pci ids

Dropping this patch. On Tue, Sep 12, 2017 at 5:31 PM, Rodrigo Vivi wrote: > On Tue, Sep 12, 2017 at 08:30:47PM +, Paulo Zanoni wrote: >> Em Seg, 2017-09-11 às 10:10 -0700, Rodrigo Vivi escreveu: >> > On Mon, Sep 11, 2017 at 04:11:33PM +, Anuj Phogat wrote: >> > >

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs

== Series Details == Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs URL : https://patchwork.freedesktop.org/series/30669/ State : success == Summary == Series 30669v1 series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Intel-gfx] ✓ Fi.CI.BAT: success for GuC Fixes, Minor restructuring changes and v9+ logging change

== Series Details == Series: GuC Fixes, Minor restructuring changes and v9+ logging change URL : https://patchwork.freedesktop.org/series/30666/ State : success == Summary == Series 30666v1 GuC Fixes, Minor restructuring changes and v9+ logging change

Re: [Intel-gfx] [PULL] drm-misc-next

On Wed, Sep 20, 2017 at 07:33:35PM +0200, Daniel Vetter wrote: > include/uapi/drm/drm_mode.h| 4 +- In case you wonder why Daniel didn't say anything about uapi changes: It's a comment/documentation fix :-) -Daniel -- Daniel Vetter Software Engineer, Intel Corporation

[Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

CNL adds an extra register for slice/subslice information. Although no SKU is planed with an extra slice let's already handle this extra piece of information so we don't have the risk in future of getting a part that might have chosen this part of the die instead of other slices or anything like

[Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

From: Ben Widawsky Cannonlake Slice and Subslice information has changed. This patch initially provided by Ben adds the proper sseu initialization. v2: This v2 done by Rodrigo includes: - Fix on Total slices count by avoiding [1][2] and [2][2]. - Inclusion of EU Per

Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

On 09/19/2017 03:06 PM, Rodrigo Vivi wrote: CNL adds an extra register for slice/subslice information. Although no SKU is planed with an extra slice let's already handle this extra piece of information so we don't have the risk in future of getting a part that might have chosen this part of

Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

On 09/19/2017 03:06 PM, Rodrigo Vivi wrote: From: Ben Widawsky Cannonlake Slice and Subslice information has changed. This patch initially provided by Ben adds the proper sseu initialization. v2: This v2 done by Rodrigo includes: - Fix on Total slices count by

[Intel-gfx] [PATCH v4 4/9] drm/i915/guc: Update suspend functionality in intel_uc_suspend path

With this patch we disable GuC submission in i915_drm_suspend. This will destroy the client which will be setup back again. We also reuse the complete sanitization done via intel_uc_runtime_suspend in this path. Post drm resume this state is recreated by intel_uc_init_hw hence we need not have

[Intel-gfx] [PATCH v4 6/9] drm/i915/guc: Fix GuC cleanup in unload path

We ensure that GuC is completely suspended and client is destroyed in i915_gem_suspend during i915_driver_unload. So now intel_uc_fini_hw should just take care of cleanup, hence s/intel_uc_fini_hw/intel_uc_cleanup. Correspondingly we also updated as

[Intel-gfx] [PATCH v4 9/9] drm/i915: Reorganize HuC authentication

Prepared intel_auth_huc to separate HuC specific functionality from GuC send action. Created new header intel_huc.h to group HuC specific declarations. v2: Changed argument preparation for AUTHENTICATE_HUC. s/intel_auth_huc/intel_huc_auth. Deferred creation of intel_huc.h to later patch. v3:

[Intel-gfx] [PATCH v4 0/9] GuC Fixes, Minor restructuring changes and v9+ logging change

This series is based on reviews from https://patchwork.freedesktop.org/series/30351/. Due to changing priority and complexity of restructuring, this patch series has gone through >5 revisions but would want to maintain the series w.r.t above base series. W.r.t above series this is rev4. Older

[Intel-gfx] [PATCH v4 7/9] drm/i915/guc: Remove i915_guc_log_unregister

Functionality needed to disable GuC interrupts and cleanup the runtime/relay data structures is already covered in the unload path via intel_guc_fini_hw and intel_guc_cleanup hence remove i915_guc_log_unregister v2: Removed the function i915_guc_log_unregister. v3: Rebase as intel_guc.h is

[Intel-gfx] [PATCH v4 3/9] drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication across RPM suspend/resume

Apart from configuring interrupts, we need to update the ggtt invalidate interface and GuC communication on suspend. This functionality can be reused for other suspend and reset paths. Prepared GuC specific helpers to handle these suspend/resume tasks namely - intel_guc_runtime_suspend,

[Intel-gfx] [PATCH v4 8/9] drm/i915/guc: Enable default/critical logging in GuC by default from GuC v9

With GuC v9, new type of Default/critical logging in GuC to enable capturing minimal important logs in production systems efficiently. This patch enables this logging in GuC by default always. It should be noted that streaming support with half-full interrupt mechanism that is present for normal

[Intel-gfx] [PATCH v4 2/9] drm/i915/guc: Update prototype/name of GuC suspend/resume fns and move to intel_uc.c

Renamed intel_guc_suspend to intel_guc_enter_sleep and intel_guc_resume to intel_guc_exit_sleep to match GuC nomenclature compatibility. We plan to use intel_guc_suspend and intel_guc_resume through intel_uc_suspend and intel_uc_resume in the path i915_drm_suspend and i915_drm_resume respectively

[Intel-gfx] [PATCH v4 5/9] drm/i915/guc: Disable GuC submission and suspend it prior to i915 reset

Before i915 reset we need to disable GuC submission and suspend GuC operarions as it is recreated during intel_uc_init_hw. We can't reuse the intel_uc_suspend functionality as reset path already holds struct_mutex. v2: Rebase w.r.t removal of GuC code restructuring. Updated reset_prepare function

[Intel-gfx] [PATCH v4 1/9] drm/i915: Create uc runtime and system suspend/resume helpers

Prepared generic helpers intel_uc_suspend, intel_uc_resume, intel_uc_runtime_suspend, intel_uc_runtime_resume. Added error handling to all the calls for suspend/resume. v2: Rebase w.r.t removal of GuC code restructuring. Cc: Michal Wajdeczko Cc: Michał Winiarski

[Intel-gfx] [PULL] drm-misc-next

Hi Dave, I heard you're nicely sleep-deprived again, so perfect time to send you a pull request. First pile of drm-misc for 4.15, busy as usual (but still well less than half the patch activity drm-intel.git has seen in the same time). drm-misc-next-2017-09-20: UAPI Changes: Cross-subsystem

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915: Drop useless HAS_PSR() check (rev3)

== Series Details == Series: series starting with [v2,1/2] drm/i915: Drop useless HAS_PSR() check (rev3) URL : https://patchwork.freedesktop.org/series/30543/ State : success == Summary == Test perf: Subgroup polling: fail -> PASS (shard-hsw) fdo#102252

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Reorganize .disable hooks for pre-DDI DP

On Mon, Sep 18, 2017 at 01:45:50PM -0700, Rodrigo Vivi wrote: > On Mon, Sep 18, 2017 at 05:31:28PM +, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Most of our DP encoder hooks are split into per-platform variants. > > .disable() an exception, and thus

[Intel-gfx] ✗ Fi.CI.BAT: warning for IGT PMU support (rev3)

== Series Details == Series: IGT PMU support (rev3) URL : https://patchwork.freedesktop.org/series/28253/ State : warning == Summary == IGT patchset tested on top of latest successful build 1043c09ccbcba8e5c2ec5f2a358a442346348bd8 tests/kms_cursor_legacy: Do not start collecting CRC after

[Intel-gfx] [PATCH i-g-t] tests/kms_cursor_legacy: Use gem_mmap__gtt() rather than gem_mmap__wc()

From: Ville Syrjälä WC mmaps aren't universally supported, so let's not depend on them when any kind of mmap will do. Signed-off-by: Ville Syrjälä --- tests/kms_cursor_legacy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[Intel-gfx] [PATCH i-g-t] scripts/run-tests.sh: Look for test-lists.txt in 'build' as well

From: Ville Syrjälä Meson always uses a separate build directotry. Adjust the assumptions in run-tests.sh to work in that environment. For now I'll just hardcode it to look for a directly called 'build'. I suppose we might want to let the user pass that in, but for

[Intel-gfx] ✓ Fi.CI.IGT: success for Support for more than two execlist ports (rev2)

== Series Details == Series: Support for more than two execlist ports (rev2) URL : https://patchwork.freedesktop.org/series/30183/ State : success == Summary == Test perf: Subgroup blocking: pass -> FAIL (shard-hsw) fdo#102252 +1 fdo#102252

Re: [Intel-gfx] [PATCH i-g-t 2/3] meson: align test-list.txt generation with automake

On Fri, Sep 08, 2017 at 05:14:47PM +0200, Daniel Vetter wrote: > - I forgot the chamelium tests > - Order tests the same way in both build systems. Since testdisplay is > special, it's easier to put that at the end in meson, so adjusted > automake to suit. > > With this you can diff the 2

[Intel-gfx] ✗ Fi.CI.BAT: warning for i915 PMU and engine busy stats (rev11)

== Series Details == Series: i915 PMU and engine busy stats (rev11) URL : https://patchwork.freedesktop.org/series/27488/ State : warning == Summary == Series 27488v11 i915 PMU and engine busy stats https://patchwork.freedesktop.org/api/1.0/series/27488/revisions/11/mbox/ Test chamelium:

[Intel-gfx] [PATCH v2 i-g-t 5/5] tests/perf_pmu: Tests for i915 PMU API

From: Tvrtko Ursulin A bunch of tests for the new i915 PMU feature. Parts of the code were initialy sketched by Dmitry Rogozhkin. v2: (Most suggestions by Chris Wilson) * Add new class/instance based engine list. * Add gem_has_engine/gem_require_engine to work with

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915: Drop useless HAS_PSR() check (rev3)

== Series Details == Series: series starting with [v2,1/2] drm/i915: Drop useless HAS_PSR() check (rev3) URL : https://patchwork.freedesktop.org/series/30543/ State : success == Summary == Series 30543v3 series starting with [v2,1/2] drm/i915: Drop useless HAS_PSR() check

[Intel-gfx] [PATCH v10 3/8] drm/i915/pmu: Expose a PMU interface for perf queries

From: Tvrtko Ursulin From: Chris Wilson From: Tvrtko Ursulin From: Dmitry Rogozhkin The first goal is to be able to measure GPU (and invidual ring) busyness without having to poll

[Intel-gfx] ✗ Fi.CI.IGT: warning for series starting with [1/2] drm/dp: Add defines for latency in sink

== Series Details == Series: series starting with [1/2] drm/dp: Add defines for latency in sink URL : https://patchwork.freedesktop.org/series/30658/ State : warning == Summary == Test perf: Subgroup polling: fail -> PASS (shard-hsw) fdo#102252 +1 Test

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Eliminate DDI encoder->type frobbery redux (rev2)

On Wed, Sep 20, 2017 at 03:40:06PM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: Eliminate DDI encoder->type frobbery redux (rev2) > URL : https://patchwork.freedesktop.org/series/30548/ > State : failure > > == Summary == > > Series 30548v2 drm/i915: Eliminate DDI

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Eliminate DDI encoder->type frobbery redux (rev2)

== Series Details == Series: drm/i915: Eliminate DDI encoder->type frobbery redux (rev2) URL : https://patchwork.freedesktop.org/series/30548/ State : failure == Summary == Series 30548v2 drm/i915: Eliminate DDI encoder->type frobbery redux

[Intel-gfx] ✓ Fi.CI.BAT: success for Support for more than two execlist ports (rev2)

== Series Details == Series: Support for more than two execlist ports (rev2) URL : https://patchwork.freedesktop.org/series/30183/ State : success == Summary == Series 30183v2 Support for more than two execlist ports https://patchwork.freedesktop.org/api/1.0/series/30183/revisions/2/mbox/

Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

> On Sep 20, 2017, at 7:33 AM, Nagaraju, Vathsala > wrote: > > Set frames before SU entry value for max resync frame count of > dpcd register 2009, bit field 0:3. > > Cc: Rodrigo Vivi > CC: Puthikorn Voravootivat >

[Intel-gfx] [PATCH v2 2/2] drm/i915: Reorganize .disable hooks for pre-DDI DP

From: Ville Syrjälä Most of our DP encoder hooks are split into per-platform variants. .disable() an exception, and thus it's a bit messy. Let's split it up as well. We'll leave the common parts in a helper called by each platform specific hook. Now each platform

[Intel-gfx] [PATCH v2 1/2] drm/i915: Drop useless HAS_PSR() check

From: Ville Syrjälä It is safe to call intel_psr_disable() on a platform without PSR. We don't have such a check when calling intel_psr_enable() either. v2: Don't drop the HAS_DDI check quite yet (Rodrigo) Reviewed-by: Rodrigo Vivi

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: Add defines for latency in sink

== Series Details == Series: series starting with [1/2] drm/dp: Add defines for latency in sink URL : https://patchwork.freedesktop.org/series/30658/ State : success == Summary == Series 30658v1 series starting with [1/2] drm/dp: Add defines for latency in sink

Re: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

On Wed, Sep 20, 2017 at 08:02:35PM +0530, vathsala nagaraju wrote: > Set frames before SU entry value for max resync frame count of > dpcd register 2009, bit field 0:3. > > Cc: Rodrigo Vivi > CC: Puthikorn Voravootivat > Signed-off-by: Vathsala

[Intel-gfx] [PATCH 3/8] drm/i915: Wrap port cancellation into a function

On reset and wedged path, we want to release the requests that are tied to ports and then mark the ports to be unset. Introduce a function for this. v2: rebase Cc: Chris Wilson Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_lrc.c

[Intel-gfx] [PATCH 7/8] drm/i915: Keep track of reserved execlist ports

To further enchance port processing, keep track of reserved ports. This way we can iterate only the used subset of port space. Note that we lift the responsibility of execlists_submit_request() to inspect hw availability and always do dequeuing. This is to ensure that only the irq handler will be

[Intel-gfx] [PATCH 5/8] drm/i915: Make execlist port count variable

As we emulate execlists on top of the GuC workqueue, it is not restricted to just 2 ports and we can increase that number arbitrarily to trade-off queue depth (i.e. scheduling latency) against pipeline bubbles. v2: rebase. better commit msg (Chris) Signed-off-by: Mika Kuoppala

[Intel-gfx] [PATCH 8/8] drm/i915: Improve GuC request coalescing

Now that we can keep track of what ports we have dequeued, coalesce only those ports instead of iterating through all ports. Cc: Michał Winiarski Cc: Chris Wilson Signed-off-by: Mika Kuoppala ---

[Intel-gfx] [PATCH 4/8] drm/i915: Add execlist_port_complete

When first execlist entry is processed, we move the port (contents). Introduce function for this as execlist and guc use this common operation. v2: rebase. s/GEM_DEBUG_BUG/GEM_BUG (Chris) Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_guc_submission.c | 8

[Intel-gfx] [PATCH 1/8] drm/i915: Make own struct for execlist items

Engine's execlist related items have been increasing to a point where a separate struct is warranted. Carve execlist specific items to a dedicated struct to add clarity. v2: add kerneldoc and fix whitespace (Joonas, Chris) v3: csb_mmio changes, rebase Suggested-by: Chris Wilson

[Intel-gfx] [PATCH 2/8] drm/i915: Move execlist initialization into intel_engine_cs.c

Move execlist init into a common engine setup. As it is common to both guc and hw execlists. v2: rebase with csb changes Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_engine_cs.c | 31 --- drivers/gpu/drm/i915/intel_lrc.c

[Intel-gfx] [PATCH 0/8] Support for more than two execlist ports (v2)

Hi, HWSP context status buffer handling and guc cleanup and request coalescing series were merged and those triggered non trivial rebase. So I had to drop reviewed-by's from the patches :( First 4 should be tasting more or less the same though. Thankyou for review and comments! -Mika Mika

[Intel-gfx] [PATCH 6/8] drm/i915: Introduce execlist_port_* accessors

Instead of trusting that first available port is at index 0, use accessor to hide this. This is a preparation for a following patches where head can be at arbitrary location in the port array. v2: improved commit message, elsp_ready readability (Chris) Signed-off-by: Mika Kuoppala

[Intel-gfx] [PATCH 1/2] drm/dp: Add defines for latency in sink

Add defines for dpcd register 2009 (synchronization latency in sink). Cc: Rodrigo Vivi CC: Puthikorn Voravootivat Signed-off-by: Vathsala Nagaraju --- include/drm/drm_dp_helper.h | 3 +++ 1 file changed, 3 insertions(+)

[Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

Set frames before SU entry value for max resync frame count of dpcd register 2009, bit field 0:3. Cc: Rodrigo Vivi CC: Puthikorn Voravootivat Signed-off-by: Vathsala Nagaraju --- drivers/gpu/drm/i915/intel_psr.c | 12

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Eliminate DDI encoder->type frobbery redux (rev2)

== Series Details == Series: drm/i915: Eliminate DDI encoder->type frobbery redux (rev2) URL : https://patchwork.freedesktop.org/series/30548/ State : failure == Summary == Series 30548v2 drm/i915: Eliminate DDI encoder->type frobbery redux

[Intel-gfx] [PATCH v2 04/29] drm/i915: Dump 'output_types' in crtc state dump

From: Ville Syrjälä To make it easier to debug things let's dump the output types bitmask in the crtc state dump. And to make life that much better, let's pretty print it as a a human reaadable string as well. v2: Have the caller pass in the buffer (Chris)

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Set our shrinker->batch to 4096 (~16MiB)

On Wed, 2017-08-16 at 14:55 +0100, Chris Wilson wrote: > Quoting Joonas Lahtinen (2017-08-16 14:39:00) > > On Sat, 2017-08-12 at 12:51 +0100, Chris Wilson wrote: > > > Prefer to defer activating our GEM shrinker until we have a few > > > megabytes to free; or we have accumulated sufficient

Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Make i915_modparams members const

On Wed, 2017-09-20 at 15:01 +0300, Jani Nikula wrote: > On Wed, 20 Sep 2017, Joonas Lahtinen wrote: > > On Tue, 2017-09-19 at 19:38 +, Michal Wajdeczko wrote: > > > We should discourage developers from modifying modparams. > > > Introduce special macro for

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_cursor_legacy: Do not start collecting CRC after making FB busy

Op 19-09-17 om 13:49 schreef Ville Syrjälä: > On Tue, Sep 19, 2017 at 01:31:13PM +0200, Maarten Lankhorst wrote: >> Collecting CRC may force a modeset, which is a bad idea after we just >> forced a hang. The hang is intended to make sure the page flip doesn't >> complete before the cursor, making

[Intel-gfx] [PATCH] dim: Accept author x signed-off based on email.

It seems Patchwork or SMTP servers are messing some patches and changing the original git's author name on git per "Last, First". So we end up with a mismatch were signed-off uses one name format and author is using another format. So, let's check for email addresses instead. v2: Avoid useles

Re: [Intel-gfx] [PATCH] dim: Accept author x signed-off based on email, but warn.

On Wed, Sep 20, 2017 at 11:51:50AM +, Jani Nikula wrote: > On Wed, 20 Sep 2017, Joonas Lahtinen wrote: > > On Tue, 2017-09-19 at 10:48 -0700, Rodrigo Vivi wrote: > >> It seems Patchwork or SMTP servers are messing some patches > >> and changing the original

[Intel-gfx] [PULL] drm-intel-fixes v2

Hi Dave, I'm sorry for the previous version generated on wrong base. I believe this one looks sane now. drm/i915 fixes for 4.14-rc1 Couple fixes for stable: - Fix MIPI panels on BXT. - Fix PCI BARs information on GVT. Plus other fixes: - Fix minimal brightness for BXT, GLK, CFL and CNL. -

Re: [Intel-gfx] [PATCH 06/31] drm/i915: Name i915_runtime_pm structure in dev_priv as "rpm"

On Tue, 2017-09-19 at 23:11 +0530, Sagar Arun Kamble wrote: > Will be using pm for state containing RPS/RC6 state in the next patch. > > Cc: Imre Deak > Cc: Chris Wilson > Signed-off-by: Sagar Arun Kamble Reviewed-by:

Re: [Intel-gfx] [PATCH 05/31] drm/i915: Separate RPS and RC6 handling for CHV

On Tue, 2017-09-19 at 23:11 +0530, Sagar Arun Kamble wrote: > This patch separates enable/disable of RC6 and RPS for CHV. > > Cc: Imre Deak > Cc: Chris Wilson > Signed-off-by: Sagar Arun Kamble Reviewed-by: Radoslaw

Re: [Intel-gfx] [PATCH 03/31] drm/i915: Separate RPS and RC6 handling for BDW

On Wed, 2017-09-20 at 11:14 +, Szwichtenberg, Radoslaw wrote: > On Tue, 2017-09-19 at 23:11 +0530, Sagar Arun Kamble wrote: > > This patch separates RC6 and RPS enabling for BDW. > > RC6/RPS Disabling are handled through gen6 functions. > > > > Cc: Imre Deak > > Cc:

Re: [Intel-gfx] [PATCH 04/31] drm/i915: Separate RPS and RC6 handling for VLV

On Tue, 2017-09-19 at 23:11 +0530, Sagar Arun Kamble wrote: > This patch separates enable/disable of RC6 and RPS for VLV. > > Cc: Imre Deak > Cc: Chris Wilson > Signed-off-by: Sagar Arun Kamble Reviewed-by: Radoslaw

Re: [Intel-gfx] [PATCH 02/31] drm/i915: Separate RPS and RC6 handling for gen6+

On Tue, 2017-09-19 at 23:11 +0530, Sagar Arun Kamble wrote: > This patch separates enable/disable of RC6 and RPS for gen6+ > platforms prior to VLV. > > Cc: Imre Deak > Cc: Chris Wilson > Signed-off-by: Sagar Arun Kamble

Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Make i915_modparams members const

On Wed, 2017-09-20 at 15:06 +0300, Joonas Lahtinen wrote: > On Wed, 2017-09-20 at 11:34 +0300, Jani Nikula wrote: > > On Tue, 19 Sep 2017, Michal Wajdeczko wrote: > > > We should discourage developers from modifying modparams. > > > Introduce special macro for easier

Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Make i915_modparams members const

On Wed, 2017-09-20 at 11:34 +0300, Jani Nikula wrote: > On Tue, 19 Sep 2017, Michal Wajdeczko wrote: > > We should discourage developers from modifying modparams. > > Introduce special macro for easier tracking of changes done > > in modparams and enforce its use by

Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Make i915_modparams members const

On Wed, 20 Sep 2017, Joonas Lahtinen wrote: > On Tue, 2017-09-19 at 19:38 +, Michal Wajdeczko wrote: >> We should discourage developers from modifying modparams. >> Introduce special macro for easier tracking of changes done >> in modparams and enforce its use

Re: [Intel-gfx] [PATCH] dim: Accept author x signed-off based on email, but warn.

On Wed, 20 Sep 2017, Joonas Lahtinen wrote: > On Tue, 2017-09-19 at 10:48 -0700, Rodrigo Vivi wrote: >> It seems Patchwork or SMTP servers are messing some patches >> and changing the original git's author name on git per "Last, First". >> So we end up with a

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