Thanks for the explanation 2). :)
I'm thinking about the rough design of preemption in GVT-g since host is moving
to support preemption.
1) Global MMIO save/restore, which is covered by context status notifier.
2) Support host preemption. GVT-g request is preempted by host. Since this
preempt
On Thu, Sep 21, 2017 at 07:42:07AM -0700, Rodrigo Vivi wrote:
> On Wed, Sep 20, 2017 at 02:32:34PM +, vathsala nagaraju wrote:
> > Add defines for dpcd register 2009 (synchronization latency
> > in sink).
> >
> > Cc: Rodrigo Vivi
> > CC: Puthikorn Voravootivat
> > Signed-off-by: Vathsala Nag
On Fri, Sep 15, 2017 at 05:48:25PM +0200, Mario Kleiner wrote:
> The new module parameter enable_hw_color_correction defaults to
> true, to retain the current behaviour. If set to false, it will
> disable all hardware color correction, like gamma/degamma and
> csc.
>
> This is useful for debugging
On Mon, Sep 25, 2017 at 08:43:44AM +0200, Maarten Lankhorst wrote:
> Op 24-09-17 om 16:33 schreef Dmitry Osipenko:
> > On 04.09.2017 13:48, Maarten Lankhorst wrote:
> >> By always keeping track of the last commit in plane_state, we know
> >> whether there is an active update on the plane or not. Wi
On Fri, Aug 25, 2017 at 10:09:45AM -0700, Matthias Kaehlcke wrote:
> The only call of wait_for_engine() is wrapped in a GEM_WARN_ON macro,
> which confusingly suppresses the call unless CONFIG_DRM_I915_DEBUG_GEM
> is set.
>
> According to http://www.spinics.net/lists/intel-gfx/msg128768.html the
>
== Series Details ==
Series: drm/i915/edp: Be less aggressive about changing link config on eDP
(rev4)
URL : https://patchwork.freedesktop.org/series/28588/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
T
== Series Details ==
Series: igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION
URL : https://patchwork.freedesktop.org/series/30860/
State : success
== Summary ==
Test prime_mmap:
Subgroup test_userptr:
dmesg-warn -> PASS (shard-hsw) fdo#102939
Signed-off-by: Nick Desaulniers
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
== Series Details ==
Series: series starting with [1/3] benchmark/gem_busy: Compare polling with
syncobj_wait
URL : https://patchwork.freedesktop.org/series/30858/
State : success
== Summary ==
Test prime_mmap:
Subgroup test_userptr:
dmesg-warn -> PASS (shard-hsw
== Series Details ==
Series: igt/gem_exec_schedule: Ignore set-priority failures on old kernels
(rev2)
URL : https://patchwork.freedesktop.org/series/30855/
State : success
== Summary ==
Test gem_exec_schedule:
Subgroup fifo-render:
fail -> PASS (shard-hsw)
== Series Details ==
Series: series starting with [1/2] drm/i915: Wrap context schedule notification
URL : https://patchwork.freedesktop.org/series/30854/
State : failure
== Summary ==
Test kms_cursor_legacy:
Subgroup flip-vs-cursor-crc-legacy:
pass -> FAIL
Em Seg, 2017-09-25 às 16:16 -0700, Rodrigo Vivi escreveu:
> Shouldn't we filter them out per platform?
Yes, although doing it like this doesn't hurt much. See the cover
letter: we can probably organize our structs in per-platform unions or
something like that.
Thanks for the review.
>
> Anyways
I wonder why are we adding all of this to debugfs that can be checked
with intel_reg dumps... Assuming it will be already noisy on dmesg if
this and HW missmatch...
But yeap, since we were missing the checks and it is probably making
our life easier, let's move with it and keep everything in sync
Shouldn't we filter them out per platform?
Anyways it is good for me
Reviewed-by: Rodrigo Vivi
On Fri, Sep 22, 2017 at 08:53:42PM +, Paulo Zanoni wrote:
> Looks like we were missing them.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_display.c | 12
> 1
== Series Details ==
Series: drm/i915/edp: Be less aggressive about changing link config on eDP
(rev4)
URL : https://patchwork.freedesktop.org/series/28588/
State : success
== Summary ==
Series 28588v4 drm/i915/edp: Be less aggressive about changing link config on
eDP
https://patchwork.freed
== Series Details ==
Series: huge gtt pages (rev9)
URL : https://patchwork.freedesktop.org/series/25118/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test perf:
Subgroup polling:
p
== Series Details ==
Series: IGT PMU support (rev4)
URL : https://patchwork.freedesktop.org/series/28253/
State : success
== Summary ==
Test gem_eio:
Subgroup in-flight:
pass -> DMESG-WARN (shard-hsw) fdo#102886 +3
Test kms_busy:
Subgroup extended-modeset-
== Series Details ==
Series: igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION
URL : https://patchwork.freedesktop.org/series/30860/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
c117213c06d0f47937c1f225ebead5e1fe8c7a0e igt/gem_exec_whis
== Series Details ==
Series: i915 PMU and engine busy stats (rev12)
URL : https://patchwork.freedesktop.org/series/27488/
State : failure
== Summary ==
Test perf:
Subgroup polling:
pass -> FAIL (shard-hsw) fdo#102252
Test kms_cursor_legacy:
Subgroup
== Series Details ==
Series: series starting with [1/3] benchmark/gem_busy: Compare polling with
syncobj_wait
URL : https://patchwork.freedesktop.org/series/30858/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
c117213c06d0f47937c1f225ebead5e1fe8c7a0e igt/
Quoting Chris Wilson (2017-09-25 21:48:35)
> Michal wants to limit machines that can do preemption, which means that
> we no longer can assume that if we have a scheduler for execbuf, that
> implies we have preemption.
The alternative to a separate param is to use capability bits in
HAS_SCHEDULER.
Michal wants to limit machines that can do preemption, which means that
we no longer can assume that if we have a scheduler for execbuf, that
implies we have preemption.
Signed-off-by: Chris Wilson
---
tests/gem_exec_schedule.c | 35 +++
1 file changed, 27 inserti
== Series Details ==
Series: igt/gem_exec_schedule: Ignore set-priority failures on old kernels
(rev2)
URL : https://patchwork.freedesktop.org/series/30855/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
c117213c06d0f47937c1f225ebead5e1fe8c7a0e igt/gem_exe
== Series Details ==
Series: series starting with [1/3] drm/i915/execlists: Microoptimise
execlists_cancel_port_request() (rev2)
URL : https://patchwork.freedesktop.org/series/30838/
State : success
== Summary ==
Test perf:
Subgroup polling:
pass -> FAIL (s
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
benchmarks/gem_exec_fault.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/benchmarks/gem_exec_fault.c b/benchmarks/gem_exec_fault.c
index a5446ea1..21bdbc9b 100644
--- a/benchmarks/gem_exec_fault.c
+++ b
== Series Details ==
Series: series starting with [1/2] drm/i915: Wrap context schedule notification
URL : https://patchwork.freedesktop.org/series/30854/
State : success
== Summary ==
Series 30854v1 series starting with [1/2] drm/i915: Wrap context schedule
notification
https://patchwork.fre
Signed-off-by: Chris Wilson
---
benchmarks/gem_busy.c | 73 ++-
1 file changed, 72 insertions(+), 1 deletion(-)
diff --git a/benchmarks/gem_busy.c b/benchmarks/gem_busy.c
index f050454b..9649ea02 100644
--- a/benchmarks/gem_busy.c
+++ b/benchmarks/
Signed-off-by: Chris Wilson
---
benchmarks/gem_syslatency.c | 86 +++--
1 file changed, 83 insertions(+), 3 deletions(-)
diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
index 4ed23638..b8788497 100644
--- a/benchmarks/gem_syslatency.
When plugging the device, we need to submit batches at highest priority
so that they cannot be gazumped by the queued requests. On older kernels
that do not support the user changing context priority, all contexts
therefore have max priority and we can ignore the error.
Signed-off-by: Chris Wilson
When plugging the device, we need to submit batches at highest priority
so that they cannot be gazumped by the queued requests. On older kernels
that do not support the user changing context priority, all contexts
therefore have max priority and we can ignore the error.
Signed-off-by: Chris Wilson
From: Tvrtko Ursulin
No functional change just something which will be handy in the
following patch.
Signed-off-by: Tvrtko Ursulin
Link:
https://patchwork.freedesktop.org/patch/msgid/20170925151543.7395-6-tvrtko.ursu...@linux.intel.com
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
--
When cancelling requests, also send the notification to any listeners
(gvt) that the request is no longer scheduler on hw. They may require to
keep the in/out exactly balanced, and so the reuse after the reset may
confuse the listener.
Fixes: 221ab9719bf3 ("drm/i915/execlists: Unwind incomplete re
== Series Details ==
Series: drm/i915: Enable scanline read based on frame timestamps
URL : https://patchwork.freedesktop.org/series/30841/
State : warning
== Summary ==
Test perf:
Subgroup blocking:
fail -> PASS (shard-hsw) fdo#102252
Test kms_chv_cursor_fa
Quoting Mika Kuoppala (2017-09-25 14:00:17)
> Chris Wilson writes:
>
> > Just rearrange the code slightly to trim the number of iterations
> > required.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/intel_lrc.c | 17 ++---
> > 1 file changed, 10 insertions(+),
Quoting Matthew Auld (2017-09-25 19:47:18)
> In i915 we now have our own tmpfs mount, so ensure that shmem_fill_super
> also calls shmem_parse_options when dealing with a kernel mount.
> Otherwise we have to clumsily call remount_fs when we want to supply our
> mount options.
>
> Signed-off-by: Ma
Quoting ville.syrj...@linux.intel.com (2016-04-01 19:48:50)
> From: Ville Syrjälä
>
> Eliminate the duplicate code for pipe timing readout in
> intel_crtc_mode_get() by using the functions we use for the normal state
> readout.
>
> v2: Store dotclock in adjusted_mode instead of the final mode
>
Quoting Matthew Auld (2017-09-25 19:47:33)
> +static int igt_tmpfs_fallback(void *arg)
> +{
> + struct drm_i915_private *i915 = arg;
> + struct vfsmount *gemfs = i915->mm.gemfs;
> + struct drm_i915_gem_object *obj;
> + int err = 0;
> +
> + /*
> +* Make sure tha
== Series Details ==
Series: huge gtt pages (rev9)
URL : https://patchwork.freedesktop.org/series/25118/
State : success
== Summary ==
Series 25118v9 huge gtt pages
https://patchwork.freedesktop.org/api/1.0/series/25118/revisions/9/mbox/
Test chamelium:
Subgroup dp-crc-fast:
Quoting Matthew Auld (2017-09-25 19:47:19)
> Enable transparent-huge-pages through gemfs by mounting with
> huge=within_size.
>
> v2: prefer kern_mount_data
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Cc: Chris Wilson
> Cc: Dave Hansen
> Cc: Kirill A. Shutemov
> Cc: Andrew Morton
Quoting Matthew Auld (2017-09-25 19:47:17)
> Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
> moves us away from the shmemfs shm_mnt, and gives us the much needed
> flexibility to do things like set our own mount options, namely huge=
> which should allow us to enable the u
Quoting Matthew Auld (2017-09-25 19:47:16)
> We are planning to use our own tmpfs mnt in i915 in place of the
> shm_mnt such that we can control the mount options, in particular
> huge=, which we require to support huge-gtt-pages. So rather than roll
> our own version of __shmem_file_setup, it woul
Good to know, mostly for debugging purposes.
v2: some improvements from Chris
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 61 ++---
1 file changed, 57 insertions(+), 4 del
For gen8+ platforms which support the 48b PPGTT, enable platform level
support for 2M pages. Also enable for mock testing.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 6 --
drivers/gpu/dr
Currently gvt gtt handling doesn't support huge page entries, so disable
for now.
v2: remove useless 48b PPGTT check
Suggested-by: Zhenyu Wang
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Zhenyu Wang
Reviewed-by: Zhenyu Wang
Reviewed-by: Chris Wilson
---
drivers/gp
v2: mock test page support configurations and add MI_STORE_DWORD test
v3: run all mockable huge page tests on all platforms via the mock_device
v4: add pin_update regression test
various improvements suggested by Chris
v5: fix issues reported by kbuild
test single sg spanning multiple pa
Try to mix sg page sizes for 4K, 64K and 2M pages.
v2: s/BIT(x) >> 12/BIT(x) >> PAGE_SHIFT/
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/scatterlist.c | 15 +++
1 file cha
For gen9+ enable platform level support for 64K pages. Also enable for
mock testing.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 3 ++
When SW enables the use of 2M/1G pages, it must disable the GTT cache.
v2: don't disable for Cherryview which doesn't even support 48b PPGTT!
v3: explicitly check that the system does support 2M/1G pages
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i91
Now that we support multiple page sizes for the ppgtt, it would be
useful to track the real usage for debugging purposes.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c| 11 +++
drivers/gpu/drm/i91
Before we can fully enable 64K pages, we need to first support a 64K
scratch page if we intend to support the case where we have object sizes
< 2M, since any scratch PTE must also point to a 64K region. Without
this our 64K usage is limited to objects which completely fill the
page-table, and ther
We can't mix 64K and 4K pte's in the same page-table, so for now we
align 64K objects to 2M to avoid any potential mixing. This is
potentially wasteful but in reality shouldn't be too bad since this only
applies to the virtual address space of a 48b PPGTT.
v2: don't separate logically connected op
For the 48b PPGTT try to align the vma start address to the required
page size boundary to guarantee we use said page size in the gtt. If we
are dealing with multiple page sizes, we can't guarantee anything and
just align to the largest. For soft pinning and objects which need to be
tightly packed
Support inserting 64K pages into the 48b PPGTT.
v2: check for 64K scratch
v3: we should only have to re-adjust maybe_64K at every sg interval
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 31 +
Before we can enable 64K pages through the IPS bit, we must first enable
it through MMIO, otherwise the page-walker will simply ignore it.
v2: add comment mentioning that 64K is BDW+
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 17
Support inserting 2M gtt pages into the 48b PPGTT.
v2: sanity check sg->length against page_size
v3: don't recalculate rem on each loop
whitespace breakup
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c |
In preparation for supporting huge gtt pages for the ppgtt, we introduce
page size members for gem objects. We fill in the page sizes by
scanning the sg table.
v2: pass the sg_mask to set_pages
v3: calculate the sg_mask inline with populating the sg_table where
possible, and pass to set_pages al
Move the setting/clearing of the vma->pages to a vm operation. Doing so
neatens things up a little, but more importantly gives us a sane place
to also set/clear the vma->pages_sizes, which we introduce later in
preparation for supporting huge-pages.
v2: remove redundant vma->pages check
v3: GEM_B
Not a fully blown gemfs, just our very own tmpfs kernel mount. Doing so
moves us away from the shmemfs shm_mnt, and gives us the much needed
flexibility to do things like set our own mount options, namely huge=
which should allow us to enable the use of transparent-huge-pages for
our shmem backed o
Enable transparent-huge-pages through gemfs by mounting with
huge=within_size.
v2: prefer kern_mount_data
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Dave Hansen
Cc: Kirill A. Shutemov
Cc: Andrew Morton
Cc: Hugh Dickins
Cc: linux...@kvack.org
---
drivers/gpu/drm/i
In i915 we now have our own tmpfs mount, so ensure that shmem_fill_super
also calls shmem_parse_options when dealing with a kernel mount.
Otherwise we have to clumsily call remount_fs when we want to supply our
mount options.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc:
In preparation for huge gtt pages expose page_sizes as part of the
device info, to indicate the page sizes supported by the HW. Currently
only 4K is supported.
v2: s/page_size_mask/page_sizes/
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Chris Wilson
Reviewed-by: Joo
Each backend is now responsible for calling __i915_gem_object_set_pages
upon successfully gathering its backing storage. This eliminates the
inconsistency between the async and sync paths, which stands out even
more when we start throwing around an sg_mask in a later patch.
Suggested-by: Chris Wil
We are planning to use our own tmpfs mnt in i915 in place of the
shm_mnt such that we can control the mount options, in particular
huge=, which we require to support huge-gtt-pages. So rather than roll
our own version of __shmem_file_setup, it would be preferred if we could
just give shmem our mnt,
Some minor bits of polish, with the bulk of the changes being the mm/shmem
patches.
Matthew Auld (22):
mm/shmem: support passing mnt to shmem_file_setup
drm/i915: introduce simple gemfs
mm/shmem: parse mount options for MS_KERNMOUNT
drm/i915/gemfs: enable THP
drm/i915: introduce page_siz
Quoting Chris Wilson (2017-09-25 18:40:20)
> Quoting Tvrtko Ursulin (2017-09-25 16:15:40)
> > From: Tvrtko Ursulin
> >
> > No functional change just something which will be handy in the
> > following patch.
> >
> > Signed-off-by: Tvrtko Ursulin
> Reviewed-by: Chris Wilson
This would be handy
Quoting Wang, Zhi A (2017-09-25 19:31:15)
> Two ideas from me. :)
>
> 1) For GVT-g, can we have an execlist context status notification in lrc irq
> handler? Then we can switch back those MMIO registers for host in the handler
> if a GVT-g request is preempted.
GVT-g is hosed with this patch if
Two ideas from me. :)
1) For GVT-g, can we have an execlist context status notification in lrc irq
handler? Then we can switch back those MMIO registers for host in the handler
if a GVT-g request is preempted.
2) Might need a flag to indicate if a request can be pre-emptible in GEM
request.
I
Quoting Matthew Auld (2017-09-22 18:32:33)
> @@ -4914,6 +4938,8 @@ i915_gem_load_init(struct drm_i915_private *dev_priv)
>
> spin_lock_init(&dev_priv->fb_tracking.lock);
>
> + WARN_ON(i915_gemfs_init(dev_priv));
Make this kinder, the driver will happily continue without a special
== Series Details ==
Series: series starting with [1/3] drm/i915/execlists: Microoptimise
execlists_cancel_port_request()
URL : https://patchwork.freedesktop.org/series/30838/
State : success
== Summary ==
Test perf:
Subgroup polling:
fail -> PASS (shard-hs
Quoting Tvrtko Ursulin (2017-09-25 16:15:43)
> From: Tvrtko Ursulin
>
> This reduces the cost of the software engine busyness tracking
> to a single no-op instruction when there are no listeners.
>
> v2: Rebase and some comments.
> v3: Rebase.
> v4: Checkpatch fixes.
> v5: Rebase.
> v6: Use syst
Quoting Tvrtko Ursulin (2017-09-25 16:15:42)
> From: Tvrtko Ursulin
>
> We can use engine busy stats instead of the MMIO sampling timer
> for better efficiency.
>
> As minimum this saves period * num_engines / sec mmio reads,
> and in a better case, when only engine busy samplers are active,
> i
Quoting Tvrtko Ursulin (2017-09-25 16:15:41)
> From: Tvrtko Ursulin
>
> Track total time requests have been executing on the hardware.
>
> We add new kernel API to allow software tracking of time GPU
> engines are spending executing requests.
>
> Both per-engine and global API is added with the
Quoting Tvrtko Ursulin (2017-09-25 16:15:39)
> From: Tvrtko Ursulin
>
> If only a subset of events is enabled we can afford to suspend
> the sampling timer when the GPU is idle and so save some cycles
> and power.
>
> v2: Rebase and limit timer even more.
> v3: Rebase.
> v4: Rebase.
> v5: Skip a
Quoting Tvrtko Ursulin (2017-09-25 16:15:40)
> From: Tvrtko Ursulin
>
> No functional change just something which will be handy in the
> following patch.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
In
Quoting Tvrtko Ursulin (2017-09-25 16:15:38)
> From: Tvrtko Ursulin
>
> From: Chris Wilson
> From: Tvrtko Ursulin
> From: Dmitry Rogozhkin
>
> The first goal is to be able to measure GPU (and invidual ring) busyness
> without having to poll registers from userspace. (Which not only incurs
> h
On Mon, 25 Sep 2017, Rodrigo Vivi wrote:
> On Mon, Sep 25, 2017 at 09:01:38AM +, vathsala nagaraju wrote:
>> On Monday 25 September 2017 01:53 PM, Jani Nikula wrote:
>>
>> On Sat, 23 Sep 2017, vathsala nagaraju
>> wrote:
>>
>> Add defines for dpcd register 2009 (synchronization
HI,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Saarinen, Jani
> Sent: maanantai 25. syyskuuta 2017 19.34
> To: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
> ; Ville Syrjälä
> Subject: Re: [Intel-gfx] ✓ Fi.CI.BAT: success for
>-Original Message-
>From: Srinivas, Vidya
>Sent: Monday, September 25, 2017 7:26 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville ; Kahola, Mika
>; Kamath, Sunil ; Shankar,
>Uma ; Konduru, Chandra
>; Srinivas, Vidya
>Subject: [PATCH v8] drm/i915: Enable scanline read based on
Quoting Tvrtko Ursulin (2017-09-25 16:15:36)
> From: Tvrtko Ursulin
>
> Will be used for exposing the PMU counters.
>
> v2:
> * Move intel_runtime_pm_get/put to the callers. (Chris Wilson)
> * Restore full unit conversion precision.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/
On Mon, Sep 25, 2017 at 09:01:38AM +, vathsala nagaraju wrote:
> On Monday 25 September 2017 01:53 PM, Jani Nikula wrote:
>
> On Sat, 23 Sep 2017, vathsala nagaraju
> wrote:
>
> Add defines for dpcd register 2009 (synchronization latency
> in sink).
>
> Cc: Rodr
Quoting Michał Winiarski (2017-09-25 16:16:33)
> On Mon, Sep 25, 2017 at 12:44:07PM +0100, Chris Wilson wrote:
> > Add another perma-pinned context for using for preemption at any time.
> > We cannot just reuse the existing kernel context, as first and foremost
> > we need to ensure that we can pre
On Mon, Sep 25, 2017 at 09:10:28AM +, vathsala nagaraju wrote:
> On Monday 25 September 2017 02:00 PM, Jani Nikula wrote:
>
> On Sat, 23 Sep 2017, vathsala nagaraju
> wrote:
>
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit fiel
Quoting Tvrtko Ursulin (2017-09-25 16:15:01)
> From: Tvrtko Ursulin
>
> Add busy and busy-avg balancers which make balancing
> decisions by looking at engine busyness via the i915 PMU.
"And thus are able to make decisions on the actual instantaneous load of
the system, and not use metrics that l
Hi,
Ville, trybot also passed for DSI system again :
https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_1193/
It did some GEM code on BDW that Vidya can comment but should not be related
to this patch.
Are we good to merge now, finally and get this machine also back to normal
pool?
Br,
Jani
>
Quoting Tvrtko Ursulin (2017-09-25 16:15:00)
> From: Tvrtko Ursulin
>
> A bunch of tests for the new i915 PMU feature.
>
> Parts of the code were initialy sketched by Dmitry Rogozhkin.
>
> v2: (Most suggestions by Chris Wilson)
> * Add new class/instance based engine list.
> * Add gem_has_eng
== Series Details ==
Series: series starting with [1/7] drm/i915/execlists: Microoptimise
execlists_cancel_port_request()
URL : https://patchwork.freedesktop.org/series/30834/
State : failure
== Summary ==
Test perf:
Subgroup polling:
fail -> PASS (shard-hs
== Series Details ==
Series: IGT PMU support (rev4)
URL : https://patchwork.freedesktop.org/series/28253/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
c117213c06d0f47937c1f225ebead5e1fe8c7a0e igt/gem_exec_whisper: Smoketest
context priorities
with lates
== Series Details ==
Series: i915 PMU and engine busy stats (rev12)
URL : https://patchwork.freedesktop.org/series/27488/
State : success
== Summary ==
Series 27488v12 i915 PMU and engine busy stats
https://patchwork.freedesktop.org/api/1.0/series/27488/revisions/12/mbox/
Test kms_pipe_crc_ba
Quoting Tvrtko Ursulin (2017-09-25 16:14:59)
> From: Tvrtko Ursulin
>
> Signed-off-by: Tvrtko Ursulin
> ---
> lib/igt_perf.h | 93
> ++--
> overlay/gem-interrupts.c | 2 +-
> overlay/gpu-freq.c | 4 +--
> overlay/gpu-top.c|
Quoting Tvrtko Ursulin (2017-09-25 16:14:57)
> From: Tvrtko Ursulin
>
> Signed-off-by: Tvrtko Ursulin
> ---
> lib/igt_perf.c | 33 +
> lib/igt_perf.h | 2 ++
> overlay/gem-interrupts.c | 16 +---
> overlay/gpu-freq.c | 22 ++
== Series Details ==
Series: igt_command_line.sh: Fix bashism
URL : https://patchwork.freedesktop.org/series/30826/
State : warning
== Summary ==
Test prime_mmap:
Subgroup test_userptr:
dmesg-warn -> PASS (shard-hsw) fdo#102939
Test perf:
Subgroup polling:
Quoting Tvrtko Ursulin (2017-09-25 16:14:56)
> From: Tvrtko Ursulin
>
> Signed-off-by: Tvrtko Ursulin
> ---
> lib/Makefile.sources | 2 ++
> overlay/perf.c => lib/igt_perf.c | 2 +-
> overlay/perf.h => lib/igt_perf.h | 2 ++
> overlay/Makefile.am | 6 ++
> overlay/g
On Mon, Sep 25, 2017 at 12:44:07PM +0100, Chris Wilson wrote:
> Add another perma-pinned context for using for preemption at any time.
> We cannot just reuse the existing kernel context, as first and foremost
> we need to ensure that we can preempt the kernel context itself, so
> require a distinct
From: Tvrtko Ursulin
If only a subset of events is enabled we can afford to suspend
the sampling timer when the GPU is idle and so save some cycles
and power.
v2: Rebase and limit timer even more.
v3: Rebase.
v4: Rebase.
v5: Skip action if perf PMU failed to register.
v6: Checkpatch cleanup.
v7:
From: Tvrtko Ursulin
This reduces the cost of the software engine busyness tracking
to a single no-op instruction when there are no listeners.
v2: Rebase and some comments.
v3: Rebase.
v4: Checkpatch fixes.
v5: Rebase.
v6: Use system_long_wq to avoid being blocked by struct_mutex
users.
v7:
From: Tvrtko Ursulin
Will be used for exposing the PMU counters.
v2:
* Move intel_runtime_pm_get/put to the callers. (Chris Wilson)
* Restore full unit conversion precision.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 8 +++-
drivers/gpu/drm/i915/i915_sysfs.c
From: Tvrtko Ursulin
Fifth spin of the i915 PMU series.
Just some small cleanups across a few patches and a rebase to latest drm-tip.
Patches 1-2 are small refactors to make the following work easier.
Patch 3 is the main bit.
Patch 4 is a small optimisation on top, to only run the sampling ti
From: Tvrtko Ursulin
We can use engine busy stats instead of the MMIO sampling timer
for better efficiency.
As minimum this saves period * num_engines / sec mmio reads,
and in a better case, when only engine busy samplers are active,
it enables us to not kick off the sampling timer at all.
v2:
From: Tvrtko Ursulin
Track total time requests have been executing on the hardware.
We add new kernel API to allow software tracking of time GPU
engines are spending executing requests.
Both per-engine and global API is added with the latter also
being exported for use by external users.
v2:
From: Tvrtko Ursulin
From: Chris Wilson
From: Tvrtko Ursulin
From: Dmitry Rogozhkin
The first goal is to be able to measure GPU (and invidual ring) busyness
without having to poll registers from userspace. (Which not only incurs
holding the forcewake lock indefinitely, perturbing the system,
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