[Intel-gfx] [PATCH] drm/i915/psr : Add psr1 live status

From: Vathsala Nagaraju Prints live state of psr1.Extending the existing PSR2 live state function to cover psr1. Tested on KBL with psr2 and psr1 panel. v2: rebase v3: DK Rename psr2_live_status to psr_source_status. v4: DK Move EDP_PSR_STATUS_STATE_SHIFT

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Set idle frame count based on sink synchronization latency

== Series Details == Series: drm/i915/psr: Set idle frame count based on sink synchronization latency URL : https://patchwork.freedesktop.org/series/43742/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4236 -> Patchwork_9113 = == Summary - WARNING == Minor unknown

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Set idle frame count based on sink synchronization latency

== Series Details == Series: drm/i915/psr: Set idle frame count based on sink synchronization latency URL : https://patchwork.freedesktop.org/series/43742/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/psr: Set idle frame count based on sink synchronization

[Intel-gfx] [PATCH] drm/i915/psr: Set idle frame count based on sink synchronization latency

DPCD 2009h "Synchronization latency in sink" has bits that tell us the maximum number of frames sink can take to resynchronize to source timing when exiting PSR. More importantly, as per eDP 1.4b, this is the "Minimum number of frames following PSR exit that the Source device needs to wait for PSR

[Intel-gfx] ✓ Fi.CI.IGT: success for gpu: Consistently use octal not symbolic permissions

== Series Details == Series: gpu: Consistently use octal not symbolic permissions URL : https://patchwork.freedesktop.org/series/43729/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4234_full -> Patchwork_9110_full = == Summary - WARNING == Minor unknown changes coming

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/edid: Fix up edid_cea_modes[] formatting

== Series Details == Series: drm/edid: Fix up edid_cea_modes[] formatting URL : https://patchwork.freedesktop.org/series/43722/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4234_full -> Patchwork_9109_full = == Summary - WARNING == Minor unknown changes coming with

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

== Series Details == Series: series starting with [1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB URL : https://patchwork.freedesktop.org/series/43721/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4234_full -> Patchwork_9108_full = == Summary -

[Intel-gfx] ✗ Fi.CI.BAT: failure for More ICL display patches (rev8)

== Series Details == Series: More ICL display patches (rev8) URL : https://patchwork.freedesktop.org/series/43546/ State : failure == Summary == Applying: drm/i915/icl: Extend AUX F interrupts to ICL Applying: drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC Applying: drm/i915/icl:

Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support

On Thu, May 24, 2018 at 05:45:43PM -0700, Dhinakaran Pandiyan wrote: > On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote: > > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote: > > > > > > From: Anusha Srivatsa > > > > > > This patch addresses

Re: [Intel-gfx] [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping

On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote: > From: Mahesh Kumar > > ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12 > mapped to tc ports[1-4]. > This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO > pin

Re: [Intel-gfx] [PATCH 12/24] drm/i915/icl: Calculate link clock using the new registers

Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu: > From: Arkadiusz Hiler > > Start using the new registers for ICL and on. I previously put this patch in a series that did not make use of cnl_calc_wrpll_link() for ICL yet. This series makes ICL run

Re: [Intel-gfx] [PATCH 09/24] drm/i915/icl: Add Icelake PCH detection

Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu: > From: Anusha Srivatsa > > This patch adds the support to detect PCH_ICP. > > Suggested-by: Paulo Zanoni Reviewed-by: Paulo Zanoni > Signed-off-by:

Re: [Intel-gfx] [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE

Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu: > From: Manasi Navare > > DFLEXDPMLE register is required to tell the FIA hardware which > main links of DP are enabled on TCC Connectors. FIA uses this > information to program PHY to Controller signal mapping.

Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support

On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote: > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote: > > > > From: Anusha Srivatsa > > > > This patch addresses Interrupts from south display engine (SDE). > > > > ICP has two registers -

[Intel-gfx] ✗ Fi.CI.BAT: failure for More ICL display patches (rev7)

== Series Details == Series: More ICL display patches (rev7) URL : https://patchwork.freedesktop.org/series/43546/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4234 -> Patchwork_9111 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_9111

Re: [Intel-gfx] [PATCH 29/24] drm/i915/icl: DP_AUX_E is valid on ICL+

Em Qui, 2018-05-24 às 16:42 -0700, Paulo Zanoni escreveu: > From: James Ausmus > > Add support for DP_AUX_E. Here we also introduce the bits for the AUX > power well E, however ICL power well support is still not enabled > yet, > so the power well is not used. > > Cc:

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for More ICL display patches (rev7)

== Series Details == Series: More ICL display patches (rev7) URL : https://patchwork.freedesktop.org/series/43546/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915/icl: Extend AUX F interrupts to ICL Okay! Commit: drm/i915/icl: GSE interrupt moves from DE_MISC to

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches (rev7)

== Series Details == Series: More ICL display patches (rev7) URL : https://patchwork.freedesktop.org/series/43546/ State : warning == Summary == $ dim checkpatch origin/drm-tip d9841751b963 drm/i915/icl: Extend AUX F interrupts to ICL 7913b8e944f7 drm/i915/icl: GSE interrupt moves from

Re: [Intel-gfx] [PATCH 05/24] drm/i915/icp: Add Interrupt Support

On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote: > From: Anusha Srivatsa > > This patch addresses Interrupts from south display engine (SDE). > > ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. > Introduce these registers and their intended

[Intel-gfx] [PATCH 29/24] drm/i915/icl: DP_AUX_E is valid on ICL+

From: James Ausmus Add support for DP_AUX_E. Here we also introduce the bits for the AUX power well E, however ICL power well support is still not enabled yet, so the power well is not used. Cc: Paulo Zanoni Cc: Rodrigo Vivi

[Intel-gfx] [PATCH 30/24] drm/i915/icl: update VBT's child_device_config flags2 field

Some bits from the flags2 field are going to be used in the next patches, so replace the whole-byte definition with the actual bits and document their versions. This patch is based on a patch by Animesh Manna. Cc: Animesh Manna Credits-to: Animesh Manna

[Intel-gfx] [PATCH 27/24] drm/i915/dp: Add support for HBR3 and TPS4 during link training

From: Manasi Navare DP spec 1.4 supports training pattern set 4 (TPS4) for HBR3 link rate. This will be used in link training's channel equalization phase if supported by both source and sink. This patch adds the helpers to check if HBR3 is supported and uses TPS4 in

[Intel-gfx] [PATCH 28/24] drm/i915/icl: implement DVFS for ICL

ICL DVFS is almost the same as CNL, except for the CDCLK/DDICLK table. Implement it just like CNL does. References: commit 48469eced282 ("drm/i915: Use cdclk_state->voltage on CNL") References: commit 53e9bf5e8159 ("drm/i915: Adjust system agent voltage on CNL if required by DDI ports") Cc:

[Intel-gfx] [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake

From: Manasi Navare For ICL, on Combo PHY the allowed max rates are: - HBR3 8.1 eDP (DDIA) - HBR2 5.4 DisplayPort (DDIB) and for MG PHY/TC DDI Ports allowed DP rates are: - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT, - DP on legacy connector - DDIC/D/E/F)

[Intel-gfx] [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping

From: Mahesh Kumar ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12 mapped to tc ports[1-4]. This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO pin mapping table. Cc: Anusha Srivatsa Cc: Madhav

Re: [Intel-gfx] [PATCH 02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC

On Thu, 2018-05-24 at 12:22 +0300, Mika Kuoppala wrote: > Paulo Zanoni writes: > > > > > From: Dhinakaran Pandiyan > > > > The Graphics System Event(GSE) interrupt bit has a new location in > > the > > GU_MISC_INTERRUPT_{IIR, ISR, IMR,

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: Include i915_scheduler.h from i915_gem_context.h

== Series Details == Series: series starting with [CI,1/2] drm/i915: Include i915_scheduler.h from i915_gem_context.h URL : https://patchwork.freedesktop.org/series/43710/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4233_full -> Patchwork_9107_full = == Summary -

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

Quoting Ville Syrjala (2018-05-24 20:04:05) > From: Ville Syrjälä > > My ILK seems to generate a spurious PCH underrun with most interlaced > HDMI modes. Add a second vblank wait to avoid it. Fwiw, a second vblank because of interlacing is very believable. > We

[Intel-gfx] ✓ Fi.CI.BAT: success for gpu: Consistently use octal not symbolic permissions

== Series Details == Series: gpu: Consistently use octal not symbolic permissions URL : https://patchwork.freedesktop.org/series/43729/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4234 -> Patchwork_9110 = == Summary - SUCCESS == No regressions found. External URL:

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/drv_suspend: Suspend under memory pressure

Quoting Antonio Argenziano (2018-05-24 21:55:38) > > > On 24/05/18 05:42, Chris Wilson wrote: > > Recently we discovered that we have a race between swapping and > > suspend in our resume path (we might be trying to page in an object > > after disabling the block devices). Let's try to exercise

Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for gpu: Consistently use octal not symbolic permissions

On Thu, 2018-05-24 at 20:55 +, Patchwork wrote: > == Series Details == > > Series: gpu: Consistently use octal not symbolic permissions > URL : https://patchwork.freedesktop.org/series/43729/ > State : warning All of these are existing and expected. Is there something else required? > ==

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for gpu: Consistently use octal not symbolic permissions

== Series Details == Series: gpu: Consistently use octal not symbolic permissions URL : https://patchwork.freedesktop.org/series/43729/ State : warning == Summary == $ dim checkpatch origin/drm-tip ce883dbd4f90 gpu: Consistently use octal not symbolic permissions -:18:

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] tests/drv_suspend: Suspend under memory pressure

On 24/05/18 05:42, Chris Wilson wrote: Recently we discovered that we have a race between swapping and suspend in our resume path (we might be trying to page in an object after disabling the block devices). Let's try to exercise that by exhausting all of system memory before suspend.

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/trace: Describe engines as class:instance pairs

== Series Details == Series: series starting with [1/2] drm/i915/trace: Describe engines as class:instance pairs URL : https://patchwork.freedesktop.org/series/43709/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4233_full -> Patchwork_9106_full = == Summary - WARNING ==

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

On Thu, May 24, 2018 at 09:15:37PM +0100, Chris Wilson wrote: > Quoting Chris Wilson (2018-05-24 21:14:23) > > Quoting Ville Syrjala (2018-05-24 20:04:05) > > > From: Ville Syrjälä > > > > > > My ILK seems to generate a spurious PCH underrun with most interlaced >

[Intel-gfx] [PATCH] gpu: Consistently use octal not symbolic permissions

There is currently a mixture of octal and symbolic permissions uses in files in drivers/gpu/drm and one file in drivers/gpu. There are ~270 existing octal uses and ~115 S_ uses. Convert all the S_ symbolic permissions to their octal equivalents as using octal and not symbolic permissions is

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

Quoting Chris Wilson (2018-05-24 21:14:23) > Quoting Ville Syrjala (2018-05-24 20:04:05) > > From: Ville Syrjälä > > > > My ILK seems to generate a spurious PCH underrun with most interlaced > > HDMI modes. Add a second vblank wait to avoid it. > > > > We have

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

Quoting Ville Syrjala (2018-05-24 20:04:05) > From: Ville Syrjälä > > My ILK seems to generate a spurious PCH underrun with most interlaced > HDMI modes. Add a second vblank wait to avoid it. > > We have seen some spurious PCH underruns still in CI as well, some >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: Fix up edid_cea_modes[] formatting

== Series Details == Series: drm/edid: Fix up edid_cea_modes[] formatting URL : https://patchwork.freedesktop.org/series/43722/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4234 -> Patchwork_9109 = == Summary - WARNING == Minor unknown changes coming with

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: per context slice/subslice powergating (rev6)

== Series Details == Series: drm/i915: per context slice/subslice powergating (rev6) URL : https://patchwork.freedesktop.org/series/42285/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4233_full -> Patchwork_9105_full = == Summary - FAILURE == Serious unknown changes

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

== Series Details == Series: series starting with [1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB URL : https://patchwork.freedesktop.org/series/43721/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4234 -> Patchwork_9108 = == Summary - WARNING ==

[Intel-gfx] [PATCH] drm/edid: Fix up edid_cea_modes[] formatting

From: Ville Syrjälä Fix up a bunch of bad indentation and insconsistent comments in edid_cea_modes[]. v2: Instead of stripping the aspect ratio comments let's add them to all modes Signed-off-by: Ville Syrjälä ---

[Intel-gfx] [PATCH 2/2] drm/i915: Simplify ilk-ivb underrun suppression

From: Ville Syrjälä Let's suppress the underruns around every modeset sequence instead of trying to avoid it. Planes are disabled at this point anyway so we don't really gain anything from keeping the underrun reporting enabled. Also for PCH ports we already

[Intel-gfx] [PATCH 1/2] drm/i915: Try to suppress more spurious PCH underruns on ILK-IVB

From: Ville Syrjälä My ILK seems to generate a spurious PCH underrun with most interlaced HDMI modes. Add a second vblank wait to avoid it. We have seen some spurious PCH underruns still in CI as well, some of which seem to be progressive DP. The logs also point

Re: [Intel-gfx] [PATCH] drm/i915: Prepare GEM for suspend earlier

/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prepare-GEM-for-suspend-earlier/20180524-231951 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: i386-randconfig-x000-201820 (attached as .config) compiler: gcc-7 (Debian 7.3.0-16) 7.3.0 reproduce: # save the attached .config

Re: [Intel-gfx] [PATCH 4/4] drm/i915: "Race-to-idle" on switching to the kernel context

: https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prepare-GEM-for-suspend-earlier/20180524-224509 reproduce: # apt-get install sparse make ARCH=x86_64 allmodconfig make C=1 CF=-D__CHECK_ENDIAN__ sparse warnings: (new ones prefixed by >>) >>

Re: [Intel-gfx] [PATCH] drm/i915: Prepare GEM for suspend earlier

://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prepare-GEM-for-suspend-earlier/20180524-231951 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: x86_64-randconfig-x015-201820 (attached as .config) compiler: gcc-7 (Debian 7.3.0-16) 7.3.0 reproduce: # save the attached

Re: [Intel-gfx] [PATCH 4/4] drm/i915: "Race-to-idle" on switching to the kernel context

: https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prepare-GEM-for-suspend-earlier/20180524-224509 config: x86_64-randconfig-x015-201820 (attached as .config) compiler: gcc-7 (Debian 7.3.0-16) 7.3.0 reproduce: # save the attached .config to linux build tree make ARCH

Re: [Intel-gfx] [PATCH 4/9] drm: Begin an API for in-kernel clients

On 05/24/2018 12:14 PM, Daniel Vetter wrote: On Thu, May 24, 2018 at 11:25:04AM +0200, Thomas Hellstrom wrote: On 05/24/2018 10:32 AM, Daniel Vetter wrote: On Wed, May 23, 2018 at 11:45:00PM +0200, Thomas Hellstrom wrote: Hi, Noralf. A couple of issues below: On 05/23/2018 04:34 PM, Noralf

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915: Include i915_scheduler.h from i915_gem_context.h

== Series Details == Series: series starting with [CI,1/2] drm/i915: Include i915_scheduler.h from i915_gem_context.h URL : https://patchwork.freedesktop.org/series/43710/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4233 -> Patchwork_9107 = == Summary - WARNING ==

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI

== Series Details == Series: drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI URL : https://patchwork.freedesktop.org/series/43698/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4230_full -> Patchwork_9104_full = == Summary - FAILURE == Serious unknown changes

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/trace: Describe engines as class:instance pairs

== Series Details == Series: series starting with [1/2] drm/i915/trace: Describe engines as class:instance pairs URL : https://patchwork.freedesktop.org/series/43709/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4233 -> Patchwork_9106 = == Summary - WARNING == Minor

Re: [Intel-gfx] [PATCH 1/2] drm/i915/trace: Describe engines as class:instance pairs

On 24/05/18 17:07, Tvrtko Ursulin wrote: On 24/05/2018 16:53, Lionel Landwerlin wrote: On 24/05/18 16:04, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Instead of using the engine->id, use uabi_class:instance pairs in trace- points including engine info. This will

Re: [Intel-gfx] [PATCH v7 7/7] drm/i915: add a sysfs entry to let users set sseu configs

On 24/05/18 16:35, Tvrtko Ursulin wrote: On 24/05/2018 15:54, Lionel Landwerlin wrote: There are concerns about denial of service around the per context sseu configuration capability. In a previous commit introducing the capability we allowed it only for capable users. This changes adds a new

Re: [Intel-gfx] [PATCH 1/2] drm/i915/trace: Describe engines as class:instance pairs

On 24/05/2018 16:53, Lionel Landwerlin wrote: On 24/05/18 16:04, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Instead of using the engine->id, use uabi_class:instance pairs in trace- points including engine info. This will be more readable, more future proof and more

Re: [Intel-gfx] [PATCH 2/2] drm/i915/trace: Remove engine out of the context sandwich

Quoting Tvrtko Ursulin (2018-05-24 16:48:45) > > On 24/05/2018 16:33, Chris Wilson wrote: > > But what we call ctx here isn't really context, but timeline; how about > > if we switch to the fence=%llx:%d representation we've mostly settled on > > for the debug messages? > > For the ctx and seqno

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/trace: Describe engines as class:instance pairs

== Series Details == Series: series starting with [1/2] drm/i915/trace: Describe engines as class:instance pairs URL : https://patchwork.freedesktop.org/series/43709/ State : warning == Summary == $ dim checkpatch origin/drm-tip 29e13710369f drm/i915/trace: Describe engines as class:instance

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: per context slice/subslice powergating (rev6)

== Series Details == Series: drm/i915: per context slice/subslice powergating (rev6) URL : https://patchwork.freedesktop.org/series/42285/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4233 -> Patchwork_9105 = == Summary - SUCCESS == No regressions found. External

Re: [Intel-gfx] [PATCH 1/2] drm/i915/trace: Describe engines as class:instance pairs

On 24/05/18 16:04, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Instead of using the engine->id, use uabi_class:instance pairs in trace- points including engine info. This will be more readable, more future proof and more stable for userspace consumption.

Re: [Intel-gfx] [PATCH 2/2] drm/i915/trace: Remove engine out of the context sandwich

On 24/05/2018 16:48, Lionel Landwerlin wrote: On 24/05/18 16:04, Tvrtko Ursulin wrote: From: Tvrtko Ursulin In the string tracepoint representation we ended up with the engine sandwiched between context hardware id and context fence id. Move the two pieces of

Re: [Intel-gfx] [PATCH 2/2] drm/i915/trace: Remove engine out of the context sandwich

On 24/05/18 16:04, Tvrtko Ursulin wrote: From: Tvrtko Ursulin In the string tracepoint representation we ended up with the engine sandwiched between context hardware id and context fence id. Move the two pieces of context data together and consolidate for redability

Re: [Intel-gfx] [PATCH 2/2] drm/i915/trace: Remove engine out of the context sandwich

On 24/05/2018 16:33, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-05-24 16:04:47) From: Tvrtko Ursulin In the string tracepoint representation we ended up with the engine sandwiched between context hardware id and context fence id. Move the two pieces of

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: per context slice/subslice powergating (rev6)

== Series Details == Series: drm/i915: per context slice/subslice powergating (rev6) URL : https://patchwork.freedesktop.org/series/42285/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Program RPCS for Broadwell Okay! Commit: drm/i915: Record the sseu

Re: [Intel-gfx] [PATCH 1/2] drm/i915/trace: Describe engines as class:instance pairs

On 24/05/2018 16:29, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-05-24 16:04:46) From: Tvrtko Ursulin Instead of using the engine->id, use uabi_class:instance pairs in trace- points including engine info. Should we not pack dev,hw_id,class,instance into u16s?

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: per context slice/subslice powergating (rev6)

== Series Details == Series: drm/i915: per context slice/subslice powergating (rev6) URL : https://patchwork.freedesktop.org/series/42285/ State : warning == Summary == $ dim checkpatch origin/drm-tip 966969f546ac drm/i915: Program RPCS for Broadwell eb3c2a521a10 drm/i915: Record the sseu

Re: [Intel-gfx] [PATCH v7 7/7] drm/i915: add a sysfs entry to let users set sseu configs

On 24/05/2018 15:54, Lionel Landwerlin wrote: There are concerns about denial of service around the per context sseu configuration capability. In a previous commit introducing the capability we allowed it only for capable users. This changes adds a new debugfs entry to let any user configure

Re: [Intel-gfx] [PATCH 2/2] drm/i915/trace: Remove engine out of the context sandwich

Quoting Tvrtko Ursulin (2018-05-24 16:04:47) > From: Tvrtko Ursulin > > In the string tracepoint representation we ended up with the engine > sandwiched between context hardware id and context fence id. > > Move the two pieces of context data together and consolidate

Re: [Intel-gfx] [PATCH 1/2] drm/i915/trace: Describe engines as class:instance pairs

Quoting Tvrtko Ursulin (2018-05-24 16:04:46) > From: Tvrtko Ursulin > > Instead of using the engine->id, use uabi_class:instance pairs in trace- > points including engine info. Should we not pack dev,hw_id,class,instance into u16s? > This will be more readable, more

[Intel-gfx] [CI 2/2] drm/i915: Forward declare struct intel_context

From: Tvrtko Ursulin This is to avoid an error with structure declared in parameter list if the include ordering changes. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson ---

[Intel-gfx] [CI 1/2] drm/i915: Include i915_scheduler.h from i915_gem_context.h

From: Tvrtko Ursulin struct i915_gem_context embeds structr i915_sched_attr so needs to include the respective header. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson ---

[Intel-gfx] [PATCH 2/2] drm/i915/trace: Remove engine out of the context sandwich

From: Tvrtko Ursulin In the string tracepoint representation we ended up with the engine sandwiched between context hardware id and context fence id. Move the two pieces of context data together and consolidate for redability using the format of

[Intel-gfx] [PATCH 1/2] drm/i915/trace: Describe engines as class:instance pairs

From: Tvrtko Ursulin Instead of using the engine->id, use uabi_class:instance pairs in trace- points including engine info. This will be more readable, more future proof and more stable for userspace consumption. Signed-off-by: Tvrtko Ursulin

[Intel-gfx] [PATCH v7 6/7] drm/i915: Expose RPCS (SSEU) configuration to userspace

From: Chris Wilson We want to allow userspace to reconfigure the subslice configuration for its own use case. To do so, we expose a context parameter to allow adjustment of the RPCS register stored within the context image (and currently not accessible via LRI). If the

[Intel-gfx] [PATCH v7 5/7] drm/i915/perf: lock powergating configuration to default when active

If some of the contexts submitting workloads to the GPU have been configured to shutdown slices/subslices, we might loose the NOA configurations written in the NOA muxes. One possible solution to this problem is to reprogram the NOA muxes when we switch to a new context. We initially tried this

[Intel-gfx] [PATCH v7 1/7] drm/i915: Program RPCS for Broadwell

From: Chris Wilson Currently we only configure the power gating for Skylake and above, but the configuration should equally apply to Broadwell and Braswell. Even though, there is not as much variation as for later generations, we want to expose control over the

[Intel-gfx] [PATCH v7 7/7] drm/i915: add a sysfs entry to let users set sseu configs

There are concerns about denial of service around the per context sseu configuration capability. In a previous commit introducing the capability we allowed it only for capable users. This changes adds a new debugfs entry to let any user configure its own context powergating setup. v2: Rename

[Intel-gfx] [PATCH v7 2/7] drm/i915: Record the sseu configuration per-context & engine

From: Chris Wilson We want to expose the ability to reconfigure the slices, subslice and eu per context and per engine. To facilitate that, store the current configuration on the context for each engine, which is initially set to the device default upon creation. v2:

[Intel-gfx] [PATCH v7 0/7] drm/i915: per context slice/subslice powergating

Hi all, This iteration addresses the last round of review. The last remaining open is on how to deal contexts setting powergating configurations while the sysfs entry disallow the setting. Tvrtko proposed to just silently ignore it and just set it when the sysfs entry allow it. The currently

[Intel-gfx] [PATCH v7 4/7] drm/i915/perf: reuse intel_lrc ctx regs macro

Abstract the context image access a bit. Signed-off-by: Lionel Landwerlin Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_perf.c | 34 +++- 1 file changed, 16 insertions(+), 18 deletions(-) diff

[Intel-gfx] [PATCH v7 3/7] drm/i915/perf: simplify configure all context function

We don't need any special treatment on error so just return as soon as possible. Signed-off-by: Lionel Landwerlin Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_perf.c | 11 --- 1 file changed, 4 insertions(+), 7

Re: [Intel-gfx] [PATCH] drm/i915: Look for an active kernel context before switching

Quoting Mika Kuoppala (2018-05-24 15:40:47) > Chris Wilson writes: > > > We were not very carefully checking to see if an older request on the > > engine was an earlier switch-to-kernel-context before deciding to emit a > > new switch. The end result would be that we

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/4] drm/mm: Reject over-sized allocation requests early

Quoting Patchwork (2018-05-21 12:15:36) > == Series Details == > > Series: series starting with [v2,1/4] drm/mm: Reject over-sized allocation > requests early > URL : https://patchwork.freedesktop.org/series/43497/ > State : success > > == Summary == > > = CI Bug Log - changes from

Re: [Intel-gfx] [PATCH] drm/i915: Look for an active kernel context before switching

Chris Wilson writes: > We were not very carefully checking to see if an older request on the > engine was an earlier switch-to-kernel-context before deciding to emit a > new switch. The end result would be that we could get into a permanent > loop of trying to emit a

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Special case kernel_context switch request

: https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prepare-GEM-for-suspend-earlier/20180524-214128 config: i386-randconfig-x071-201820 (attached as .config) compiler: gcc-7 (Debian 7.3.0-16) 7.3.0 reproduce: # save the attached .config to linux build tree make ARCH

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Special case kernel_context switch request

: https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prepare-GEM-for-suspend-earlier/20180524-214128 config: x86_64-randconfig-x015-201820 (attached as .config) compiler: gcc-7 (Debian 7.3.0-16) 7.3.0 reproduce: # save the attached .config to linux build tree make ARCH

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI

== Series Details == Series: drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI URL : https://patchwork.freedesktop.org/series/43698/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4230 -> Patchwork_9104 = == Summary - SUCCESS == No regressions found. External URL:

Re: [Intel-gfx] [PATCH 4/6] drm/i915/psr: Avoid unnecessary DPCD read of DP_PSR_CAPS

On Sun, 20 May 2018, Tarun Vyas wrote: > On Fri, May 11, 2018 at 12:51:43PM -0700, Dhinakaran Pandiyan wrote: >> intel_dp->psr_dpcd already has the required values. >> >> Cc: Jose Roberto de Souza >> Signed-off-by: Dhinakaran Pandiyan

Re: [Intel-gfx] [PATCH 3/6] drm/psr: Fix missed entry in PSR setup time table.

On Fri, 11 May 2018, Dhinakaran Pandiyan wrote: > Entry corresponding to 220 us setup time was missing. I am not aware of > any specific bug this fixes, but this could potentially result in enabling > PSR on a panel with a higher setup time requirement than

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add ChromeOS EC CEC Support (rev7)

== Series Details == Series: Add ChromeOS EC CEC Support (rev7) URL : https://patchwork.freedesktop.org/series/43162/ State : failure == Summary == Applying: media: cec-notifier: Get notifier by device and connector name Applying: drm/i915: hdmi: add CEC notifier to intel_hdmi Applying: mfd:

Re: [Intel-gfx] [PATCH v4] drm/i915: Flush the ring stop bit after clearing RING_HEAD in reset

Quoting Tvrtko Ursulin (2018-05-24 14:34:41) > > On 19/05/2018 10:04, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-05-18 15:42:00) > >> > >> On 18/05/2018 15:13, Chris Wilson wrote: > >>> Quoting Tvrtko Ursulin (2018-05-18 13:36:52) > > On 18/05/2018 13:28, Chris Wilson wrote: >

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Look for an active kernel context before switching (rev2)

== Series Details == Series: drm/i915: Look for an active kernel context before switching (rev2) URL : https://patchwork.freedesktop.org/series/43609/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4228_full -> Patchwork_9102_full = == Summary - WARNING == Minor unknown

Re: [Intel-gfx] [PATCH v4] drm/i915: Flush the ring stop bit after clearing RING_HEAD in reset

On 19/05/2018 10:04, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-05-18 15:42:00) On 18/05/2018 15:13, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-05-18 13:36:52) On 18/05/2018 13:28, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-05-18 12:50:41) On 18/05/2018 12:10, Chris

Re: [Intel-gfx] [PATCH 1/6] drm/i915/psr: Avoid DPCD reads when panel does not support PSR

On Thu, 17 May 2018, Tarun Vyas wrote: > On Fri, May 11, 2018 at 12:51:40PM -0700, Dhinakaran Pandiyan wrote: >> Ville noticed that we are unncessarily reading DPCD's after knowing >> panel did not support PSR. Looks like this check that was present >> earlier got removed

Re: [Intel-gfx] [PATCH 2/6] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.

On Fri, 11 May 2018, Dhinakaran Pandiyan wrote: > On Fri, 2018-05-11 at 12:51 -0700, Dhinakaran Pandiyan wrote: >> By moving the check from psr_compute_config() to psr_init_dpcd(), we >> get >> to set the dev_priv->psr.sink_support flag only when the panel is >>

Re: [Intel-gfx] [PATCH v2 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs.

Patch look ok to me. Reviewed-by: Mika Kahola On Wed, 2018-05-23 at 15:44 -0700, Paulo Zanoni wrote: > From: Manasi Navare > > PLLs are the source clocks for the DDIs so in order > to determine the ddi clock we need to check the PLL >

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Look for an active kernel context before switching (rev2)

== Series Details == Series: drm/i915: Look for an active kernel context before switching (rev2) URL : https://patchwork.freedesktop.org/series/43609/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4228 -> Patchwork_9102 = == Summary - SUCCESS == No regressions found.

Re: [Intel-gfx] [PATCH] drm/i915/psr: Nuke PSR support for VLV and CHV

On Mon, 14 May 2018, Dhinakaran Pandiyan wrote: > On Mon, 2018-05-14 at 12:09 +0300, Jani Nikula wrote: >> On Fri, 11 May 2018, Dhinakaran Pandiyan > om> wrote: >> > >> > PSR hardware and hence the driver code for VLV and CHV deviates

Re: [Intel-gfx] [PATCH] drm/i915/psr: vbt change for psr

On Tue, 22 May 2018, Jani Nikula wrote: > On Tue, 22 May 2018, vathsala nagaraju wrote: >> From: Vathsala Nagaraju >> >> For psr block #9, the vbt description has moved to options [0-3] for >> TP1,TP2,TP3

[Intel-gfx] [PATCH] drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI

From: Ville Syrjälä When encountering a connector with the scaling mode property both intel and modesetting ddxs sometimes add tons of DBLSCAN modes to the output's mode list. The idea presumably being that since the output will be going through the panel fitter

[Intel-gfx] [PATCH i-g-t] tests/drv_suspend: Suspend under memory pressure

Recently we discovered that we have a race between swapping and suspend in our resume path (we might be trying to page in an object after disabling the block devices). Let's try to exercise that by exhausting all of system memory before suspend. References:

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