On Wed, Jun 27, 2018 at 07:41:05PM +0530, Kumar, Mahesh wrote:
> Hi,
>
> thanks for review.
> On 6/26/2018 1:59 PM, Daniel Vetter wrote:
> > On Tue, Jun 26, 2018 at 11:52:57AM +0530, Mahesh Kumar wrote:
> > > This patch implements get_crc_sources callback, which returns list of
> > > all the valid
On Tue, Jun 26, 2018 at 01:20:58PM -0700, Tarun Vyas wrote:
> On Tue, Jun 26, 2018 at 12:43:42PM -0700, Dhinakaran Pandiyan wrote:
> > On Tue, 2018-06-26 at 10:26 +0200, Daniel Vetter wrote:
> > > On Mon, Jun 25, 2018 at 10:57:23PM -0700, Tarun Vyas wrote:
> > > >
> > > > This is a lockless versio
On Wed, Jun 27, 2018 at 11:18:54PM -0700, Dhinakaran Pandiyan wrote:
> There is already a check to allow only RGB formats with CCS
> modifiers.
>
> Signed-off-by: Dhinakaran Pandiyan
Reviewed-by: Daniel Vetter
Aside: intel_framebuffer_init is horribly long function, and it would
probably m
On Wed, Jun 27, 2018 at 02:49:40PM +0300, Jani Nikula wrote:
> On Thu, 21 Jun 2018, Ville Syrjälä wrote:
> > On Thu, Jun 21, 2018 at 04:03:30PM +0300, Jani Nikula wrote:
> >> Commit 9504a8924759 ("drm/i915/vlv: Reset the ADPA in
> >> vlv_display_power_well_init()") started calling intel_crt_reset(
There is already a check to allow only RGB formats with CCS
modifiers.
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/intel_display.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index eaa066
On Wed, Jun 27, 2018 at 06:07:39PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 27, 2018 at 11:11:57AM +0200, Daniel Vetter wrote:
> > On Wed, Jun 27, 2018 at 11:08:48AM +0200, Daniel Vetter wrote:
> > > On Tue, Jun 26, 2018 at 08:47:09PM +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > >
== Series Details ==
Series: drm/i915: Fix CHICKEN_TRANS register offset
URL : https://patchwork.freedesktop.org/series/45536/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4392_full -> Patchwork_9456_full =
== Summary - SUCCESS ==
No regressions found.
== Known iss
On Wed, Jun 27, 2018 at 06:13:01PM +0300, Jani Nikula wrote:
> As a rule of thumb, don't change patches while committing.
>
> Cc: Imre Deak
> Signed-off-by: Jani Nikula
Acked-by: Rodrigo Vivi
> ---
> drm-intel.rst | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drm-intel.rst
On Wed, Jun 27, 2018 at 06:13:00PM +0300, Jani Nikula wrote:
> Lots has happened in the CI front since the first version was added.
>
> Signed-off-by: Jani Nikula
Acked-by: Rodrigo Vivi
> ---
> drm-intel.rst | 45 -
> 1 file changed, 28 insertions(+
On Wed, Jun 27, 2018 at 05:41:13PM +0300, Jani Nikula wrote:
> There's already some BIT() usage here and there, embrace it.
>
> Cc: Paulo Zanoni
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git
On Wed, Jun 27, 2018 at 04:14:01PM -0700, José Roberto de Souza wrote:
> This registers offsets is not sequential for transcoder D and EDP so
> for EDP transcoder it was writing to 0x420d0 that do not map to
> any register in spec.
>
> CHICKEN_TRANS is used in PSR2 and intel_enable_ddi_hdmi() to a
== Series Details ==
Series: series starting with [1/9] drm/i915: Drop posting reads to flush master
interrupts
URL : https://patchwork.freedesktop.org/series/45531/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4392_full -> Patchwork_9455_full =
== Summary - WARNING ==
== Series Details ==
Series: series starting with [1/4] drm/i915: Reduce spinlock hold time during
notify_ring() interrupt
URL : https://patchwork.freedesktop.org/series/45527/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4391_full -> Patchwork_9454_full =
== Summary - WA
== Series Details ==
Series: series starting with [v8,1/2] drm/i915/psr: Lockless version of
psr_wait_for_idle
URL : https://patchwork.freedesktop.org/series/45524/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4391_full -> Patchwork_9453_full =
== Summary - WARNING ==
Hi Dave,
One more for 4.19. We don't have any big change on this one,
it is mostly drivers updates here. Please pull.
Regards,
Gustavo
drm-misc-next-2018-06-27:
drm-misc-next for 4.19:
Cross-subsystem Changes:
devicetree documentation
dt-bindings defintions for sun8i (Jernej Skrabec)
Core Cha
== Series Details ==
Series: drm/i915: Fix assert_plane() warning on bootup with external display
(rev5)
URL : https://patchwork.freedesktop.org/series/44909/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] driv
On KBL, WHL RVPs, booting up with an external display connected, triggers
below warning, when the BiOS brings up the external display too.
This warning is not seen during hotplug.
[3.615226] [ cut here ]
[3.619829] plane 1A assertion failure (expected on, current of
== Series Details ==
Series: drm/i915: Fix CHICKEN_TRANS register offset
URL : https://patchwork.freedesktop.org/series/45536/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4392 -> Patchwork_9456 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://p
== Series Details ==
Series: series starting with [CI,1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode
URL : https://patchwork.freedesktop.org/series/45519/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4390_full -> Patchwork_9451_full =
== Summary - FAILURE ==
This registers offsets is not sequential for transcoder D and EDP so
for EDP transcoder it was writing to 0x420d0 that do not map to
any register in spec.
CHICKEN_TRANS is used in PSR2 and intel_enable_ddi_hdmi() to apply
WA #1143 but I'm not aware of any open issue cause by this offset
error.
Sp
On 06/25/2018 03:33 AM, Imre Deak wrote:
On Wed, Jun 13, 2018 at 02:48:49PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.
When measured on a scope the hi
== Series Details ==
Series: series starting with [1/9] drm/i915: Drop posting reads to flush master
interrupts
URL : https://patchwork.freedesktop.org/series/45531/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4392 -> Patchwork_9455 =
== Summary - SUCCESS ==
No regres
== Series Details ==
Series: drm/i915: Wait for engines to idle before retiring
URL : https://patchwork.freedesktop.org/series/45484/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4389_full -> Patchwork_9450_full =
== Summary - WARNING ==
Minor unknown changes coming wit
Em Ter, 2018-06-26 às 13:52 -0700, Anusha Srivatsa escreveu:
> This patch addresses Interrupts from south display engine (SDE).
>
> ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
> Introduce these registers and their intended values.
>
> Introduce icp_irq_handler().
>
> The icp_ir
On Wed, 27 Jun 2018 08:30:37 +0200,
Takashi Iwai wrote:
>
> On Wed, 27 Jun 2018 08:25:32 +0200,
> Chris Wilson wrote:
> >
> > Obtaining the runtime pm wakeref can fail, especially in a hotplug
> > scenario where i915.ko has been unloaded. If we do not catch the
> > failure, we end up with an unba
== Series Details ==
Series: series starting with [1/9] drm/i915: Drop posting reads to flush master
interrupts
URL : https://patchwork.freedesktop.org/series/45531/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e95bd2fda39a drm/i915: Drop posting reads to flush master interru
The current method of checking for a failed module load is flawed, as we
only report the error on probing it is not being reported back by
modprobe. So we have to dig inside the module_parameters while the
module is still loaded to discover the error.
v2: Expect i915.inject_load_failure to be zero
== Series Details ==
Series: series starting with [1/4] drm/i915: Reduce spinlock hold time during
notify_ring() interrupt
URL : https://patchwork.freedesktop.org/series/45527/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4391 -> Patchwork_9454 =
== Summary - SUCCESS ==
Now that we use the CSB stored in the CPU friendly HWSP, we do not need
to track interrupts for when the mmio CSB registers are valid and can
just check where we read up to last from the cached HWSP. This means we
can forgo the atomic bit tracking from interrupt, and in the next patch
it means we c
Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
bottom half"), we came to the conclusion that running our CSB processing
and ELSP submission from inside the irq handler was a bad idea. A really
bad idea as we could impose nearly 1s latency on other users of the
system, on av
In the next patch, we will process the CSB events directly from the
submission path, rather than only after a CS interrupt. Hence, we will
no longer have the need for a loop until the has-interrupt bit is clear,
and in the meantime can remove that small optimisation.
v2: Tvrtko pointed out it was
In the next patch, we will begin processing the CSB from inside the
submission path (underneath an irqsoff section, and even from inside
interrupt handlers). This means that updating the execlists->port[] will
no longer be serialised by the tasklet but needs to be locked by the
engine->timeline.loc
On HW reset, the HW clears the write pointer (to 0). But since it also
writes its first CSB entry to slot 0, we need to reset the write pointer
back to the element before (so the first entry we read is 0).
This is required for the next patch, where we trust the CSB completely!
Signed-off-by: Chri
In the following patch, we will process the CSB events under the
timeline.lock and not serialised by the tasklet. This also means that we
will need to protect access to common variables such as
execlists->csb_head with the timeline.lock during reset.
v2: Move sync_irq to avoid deadlocks between ta
As we now never read back our current head position from the CSB
pointers register, and the HW itself doesn't use it to prevent
overwriting unread CSB entries, we do not need to keep updating the
register. As it turns out this register is not listed as being shadowed,
and so requires forcewake -- b
Following the removal of the last workarounds, the only CSB mmio access
is for the old vGPU interface. The mmio registers presented by vGPU do
not require forcewake and can be treated as ordinary volatile memory,
i.e. they behave just like the HWSP access just at a different location.
We can reduce
We do not need to do a posting read of our uncached mmio write to
re-enable the master interrupt lines after handling an interrupt, so
don't. This saves us a slow UC read before we can process the interrupt,
most noticeable in execlists where any stalls imposes extra latency on
GPU command executio
== Series Details ==
Series: series starting with [v8,1/2] drm/i915/psr: Lockless version of
psr_wait_for_idle
URL : https://patchwork.freedesktop.org/series/45524/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4391 -> Patchwork_9453 =
== Summary - SUCCESS ==
No regress
== Series Details ==
Series: drm/i915: Wait for engines to idle before retiring
URL : https://patchwork.freedesktop.org/series/45484/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4388_full -> Patchwork_9449_full =
== Summary - WARNING ==
Minor unknown changes coming wit
By taking advantage of the RCU protection of the task struct, we can find
the appropriate signaler under the spinlock and then release the spinlock
before waking the task and signaling the fence.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 32
Rather than have multiple locked instructions inside the notify_ring()
irq handler, move them inside the spinlock and reduce their intrinsic
locking.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
drivers/gpu/drm/i915/i915_request.
If we have more interrupts pending (because we know there are more
breadcrumb signals before the completion), then we do not need to
trigger an irq_seqno_barrier or even wakeup the task on this interrupt
as there will be another. To allow some margin of error (we are trying
to work around incoheren
Avoid calling dma_fence_signal() from inside the interrupt if we haven't
enabled signaling on the request.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 8 ++--
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/intel_
== Series Details ==
Series: drm/i915: encourage BIT() macro usage in register definitions
URL : https://patchwork.freedesktop.org/series/45498/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4388_full -> Patchwork_9446_full =
== Summary - WARNING ==
Minor unknown changes
The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited, then
the pipe_update_start call schedules itself out to check back later.
On ChromeOS-4.4 kernel, which is fairly up-to-date w.r.t drm/i915 but
lags w.r.t core kernel code, hot plugging an external display triggers
tons of "potential
This is a lockless version of the exisiting psr_wait_for_idle().
We want to wait for PSR to idle out inside intel_pipe_update_start.
At the time of a pipe update, we should never race with any psr
enable or disable code, which is a part of crtc enable/disable.
The follow up patch will use this lock
== Series Details ==
Series: series starting with [v7,1/2] drm/i915/psr: Lockless version of
psr_wait_for_idle
URL : https://patchwork.freedesktop.org/series/45521/
State : failure
== Summary ==
Applying: drm/i915/psr: Lockless version of psr_wait_for_idle
Using index info to reconstruct a ba
== Series Details ==
Series: series starting with [CI,1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode
URL : https://patchwork.freedesktop.org/series/45519/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4390 -> Patchwork_9451 =
== Summary - SUCCESS ==
No regres
Setup a userptr object that only has a read-only mapping back to a file
store (memfd). Then attempt to write into that mapping using the GPU and
assert that those writes do not land (while also writing via a writable
userptr mapping into the same memfd to verify that the GPU is working!)
Signed-of
== Series Details ==
Series: series starting with [CI,1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode
URL : https://patchwork.freedesktop.org/series/45519/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/gtt: Add read only pages to gen8_pte_encode
Okay!
C
This is a lockless version of the exisiting psr_wait_for_idle().
We want to wait for PSR to idle out inside intel_pipe_update_start.
At the time of a pipe update, we should never race with any psr
enable or disable code, which is a part of crtc enable/disable.
The follow up patch will use this lock
The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited, then
the pipe_update_start call schedules itself out to check back later.
On ChromeOS-4.4 kernel, which is fairly up-to-date w.r.t drm/i915 but
lags w.r.t core kernel code, hot plugging an external display triggers
tons of "potential
== Series Details ==
Series: series starting with [CI,1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode
URL : https://patchwork.freedesktop.org/series/45519/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
edc140b84d5c drm/i915/gtt: Add read only pages to gen8_pte_encode
== Series Details ==
Series: drm: Add generic fbdev emulation
URL : https://patchwork.freedesktop.org/series/45488/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4388_full -> Patchwork_9445_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9445_f
From: Jon Bloomfield
We can set a bit inside the ppGTT PTE to indicate a page is read-only;
writes from the GPU will be discarded. We can use this to protect pages
and in particular support read-only userptr mappings (necessary for
importing PROT_READ vma).
Signed-off-by: Jon Bloomfield
Signed-
If the user created a read-only object, they should not be allowed to
circumvent the write protection using the pwrite ioctl.
Signed-off-by: Chris Wilson
Cc: Jon Bloomfield
Cc: Joonas Lahtinen
Cc: Matthew Auld
Reviewed-by: Jon Bloomfield
Reviewed-by: Joonas Lahtinen
Reviewed-by: Matthew Auld
From: Jon Bloomfield
Hook up the flags to allow read-only ppGTT mappings for gen8+
v2: Include a selftest to check that writes to a readonly PTE are
dropped
v3: Don't duplicate cpu_check() as we can just reuse it, and even worse
don't wholesale copy the theory-of-operation comment from igt_ctx_e
If the user has created a read-only object, they should not be allowed
to circumvent the write protection by using a GGTT mmapping. Deny it.
Also most machines do not support read-only GGTT PTEs, so again we have
to reject attempted writes. Fortunately, this is known a priori, so we
can at least r
On gen8 and onwards, we can mark GPU accesses through the ppGTT as being
read-only, that is cause any GPU write onto that page to be discarded
(not triggering a fault). This is all that we need to finally support
the read-only flag for userptr!
Testcase: igt/gem_userptr_blits/readonly*
Signed-off-
== Series Details ==
Series: series starting with [1/6] drm/i915/execlists: Pull submit after
dequeue under timeline lock
URL : https://patchwork.freedesktop.org/series/45482/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4388_full -> Patchwork_9444_full =
== Summary - WAR
== Series Details ==
Series: drm/i915: Wait for engines to idle before retiring
URL : https://patchwork.freedesktop.org/series/45484/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4389 -> Patchwork_9450 =
== Summary - SUCCESS ==
No regressions found.
External URL:
ht
On Wed, Jun 27, 2018 at 05:18:39PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 26, 2018 at 05:05:48PM -0700, Vito Caputo wrote:
> > Hello,
> >
> > Beginning with 4.18, when I lock my X server using the `xlock` command,
> > and close the lid, upon reopening the lid I am not presented with the
> > xlo
On Wed, Jun 27, 2018 at 10:39:56AM -0700, Radhakrishna Sripada wrote:
> On Tue, Jun 26, 2018 at 05:55:59PM -0700, Azhar Shaikh wrote:
> > On KBL, WHL RVPs, booting up with an external display connected, triggers
> > below warning, when the BiOS brings up the external display too.
> > This warning i
== Series Details ==
Series: drm/i915: Wait for engines to idle before retiring
URL : https://patchwork.freedesktop.org/series/45484/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4388 -> Patchwork_9449 =
== Summary - SUCCESS ==
No regressions found.
External URL:
ht
== Series Details ==
Series: Improve crc-core driver interface (rev3)
URL : https://patchwork.freedesktop.org/series/45246/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4388 -> Patchwork_9447 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9447 a
== Series Details ==
Series: drm/i915: Implement HDCP2.2 (rev7)
URL : https://patchwork.freedesktop.org/series/38254/
State : failure
== Summary ==
Applying: drm: hdcp2.2 authentication msg definitions
Applying: drm: HDMI and DP specific HDCP2.2 defines
Applying: mei: bus: whitelist hdcp clien
On Tue, Jun 26, 2018 at 05:55:59PM -0700, Azhar Shaikh wrote:
> On KBL, WHL RVPs, booting up with an external display connected, triggers
> below warning, when the BiOS brings up the external display too.
> This warning is not seen during hotplug.
>
> [3.615226] [ cut here ]---
== Series Details ==
Series: drm/i915: encourage BIT() macro usage in register definitions
URL : https://patchwork.freedesktop.org/series/45498/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4388 -> Patchwork_9446 =
== Summary - SUCCESS ==
No regressions found.
Extern
On Wed, Jun 27, 2018 at 5:13 PM, Jani Nikula wrote:
> As a rule of thumb, don't change patches while committing.
>
> Cc: Imre Deak
> Signed-off-by: Jani Nikula
> ---
> drm-intel.rst | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drm-intel.rst b/drm-intel.rst
> index baf48f459dd
On Wed, Jun 27, 2018 at 5:13 PM, Jani Nikula wrote:
> Lots has happened in the CI front since the first version was added.
>
> Signed-off-by: Jani Nikula
> ---
> drm-intel.rst | 45 -
> 1 file changed, 28 insertions(+), 17 deletions(-)
>
> diff --git a
== Series Details ==
Series: drm: Add generic fbdev emulation
URL : https://patchwork.freedesktop.org/series/45488/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4388 -> Patchwork_9445 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.fr
== Series Details ==
Series: drm: Add generic fbdev emulation
URL : https://patchwork.freedesktop.org/series/45488/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm: Begin an API for in-kernel clients
Okay!
Commit: drm/fb-helper: Add generic fbdev emulation .fb_probe func
== Series Details ==
Series: drm: Add generic fbdev emulation
URL : https://patchwork.freedesktop.org/series/45488/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b94e8e78c556 drm: Begin an API for in-kernel clients
-:26: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s
== Series Details ==
Series: series starting with [1/6] drm/i915/execlists: Pull submit after
dequeue under timeline lock
URL : https://patchwork.freedesktop.org/series/45482/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4388 -> Patchwork_9444 =
== Summary - SUCCESS ==
Quoting Michal Wajdeczko (2018-06-27 16:51:42)
> On Wed, 27 Jun 2018 16:41:13 +0200, Jani Nikula
> wrote:
>
> > There's already some BIT() usage here and there, embrace it.
> >
> > Cc: Paulo Zanoni
> > Signed-off-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 9 +
> >
On Wed, 27 Jun 2018 16:41:13 +0200, Jani Nikula
wrote:
There's already some BIT() usage here and there, embrace it.
Cc: Paulo Zanoni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/
Quoting Tvrtko Ursulin (2018-06-27 16:21:24)
>
> On 27/06/2018 14:29, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-06-27 14:15:22)
> >>
> >> On 27/06/2018 11:58, Chris Wilson wrote:
> >>> That tasklets get kicked randomly, I think was the culprit.
> >>
> >> What do you mean? I hope we have
Hi,
On 6/27/2018 8:48 PM, Maarten Lankhorst wrote:
Op 27-06-18 om 16:44 schreef Mahesh Kumar:
This patch implements a callback function "pre_crc_read" which will
be called before crc read. In this function driver can implement and
preparation work required for successfully reading CRC data.
S
Op 27-06-18 om 16:44 schreef Mahesh Kumar:
> This reverts commit e8fa5671183c80342d520ad81d14fa79a9d4a680.
>
> Don't wait for first CRC during crtc_crc_open. It avoids one frame wait
> during open. If application want to wait after read call, it can use
> poll/read blocking read() call.
>
> Suggest
On 27/06/2018 14:29, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-06-27 14:15:22)
On 27/06/2018 11:58, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-06-27 11:40:32)
On 25/06/2018 10:48, Chris Wilson wrote:
Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
botto
Op 27-06-18 om 16:44 schreef Mahesh Kumar:
> This patch implements a callback function "pre_crc_read" which will
> be called before crc read. In this function driver can implement and
> preparation work required for successfully reading CRC data.
>
> Signed-off-by: Mahesh Kumar
> Cc: dri-de...@lis
Lots has happened in the CI front since the first version was added.
Signed-off-by: Jani Nikula
---
drm-intel.rst | 45 -
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drm-intel.rst b/drm-intel.rst
index c68949a41c95..baf48f459dd9 100
As a rule of thumb, don't change patches while committing.
Cc: Imre Deak
Signed-off-by: Jani Nikula
---
drm-intel.rst | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drm-intel.rst b/drm-intel.rst
index baf48f459dd9..ad8ff9739336 100644
--- a/drm-intel.rst
+++ b/drm-intel.rst
@@ -196,
On Wed, Jun 27, 2018 at 11:11:57AM +0200, Daniel Vetter wrote:
> On Wed, Jun 27, 2018 at 11:08:48AM +0200, Daniel Vetter wrote:
> > On Tue, Jun 26, 2018 at 08:47:09PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Add a convenience macro for iterating connector->encoder_ids[].
Chris Wilson writes:
> Avoid calling dma_fence_signal() from inside the interrupt if we haven't
> enabled signaling on the request.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_irq.c | 8 ++--
> drivers/gpu/drm/i915/i915_request.c | 2 +-
> drivers/gpu/drm/i
To exercise the new I915_CONTEXT_PARAM_ENGINES and interactions with
gem_execbuf().
Signed-off-by: Chris Wilson
---
tests/Makefile.sources | 1 +
tests/gem_ctx_engines.c | 236
tests/meson.build | 1 +
3 files changed, 238 insertions(+)
create
Exercise the in-kernel load balancer checking that we can distribute
batches across the set of ctx->engines to avoid load.
Signed-off-by: Chris Wilson
---
tests/Makefile.am | 1 +
tests/Makefile.sources| 1 +
tests/gem_exec_balancer.c | 465 ++
Hi Noralf,
I love your patch! Perhaps something to improve:
[auto build test WARNING on next-20180627]
[cannot apply to drm/drm-next linus/master drm-exynos/exynos-drm/for-next
v4.18-rc2 v4.18-rc1 v4.17 v4.18-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help
Queues are a form of contexts that share vm and enfore a single timeline
across all engines. Test switching between them, just like ordinary
contexts.
Signed-off-by: Chris Wilson
---
tests/gem_ctx_switch.c | 75 +++---
1 file changed, 55 insertions(+), 20 dele
Add a new mode for some more stress, submit the all-engines tests
simultaneously, a stream per engine.
Signed-off-by: Chris Wilson
---
tests/gem_exec_whisper.c | 27 ++-
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/tests/gem_exec_whisper.c b/tests/gem_ex
v2: Test each shared context is its own timeline and allows request
reordering between shared contexts.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Michal Wajdeczko
---
lib/i915/gem_context.c | 66 +++
lib/i915/gem_context.h | 13 +
tests/Ma
Fixes: 0654edaa3690 ("misc/mei/hdcp: Component framework for I915 Interface")
Signed-off-by: kbuild test robot
---
mei_hdcp.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index ba75502..146a4be
Hi Ramalingam,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20180627]
[cannot apply to v4.18-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system
This reverts commit e8fa5671183c80342d520ad81d14fa79a9d4a680.
Don't wait for first CRC during crtc_crc_open. It avoids one frame wait
during open. If application want to wait after read call, it can use
poll/read blocking read() call.
Suggested-by: Ville Syrjälä
Signed-off-by: Mahesh Kumar
Cc:
This patch implements a callback function "get_crc_sources" which
will be called during read of control node. It is an optional
callback function and if driver implements this callback, driver
should print list of available CRC sources in seq_file privided
as an input to the callback.
Changes Sinc
This patch implements "verify_crc_source" callback function for
rcar drm driver.
Signed-off-by: Mahesh Kumar
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 40 ++
1 file changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/rcar
This patch implements "verify_crc_source" callback function for
rockchip drm driver.
Changes since V1:
- simplify the verification (Jani N)
Signed-off-by: Mahesh Kumar
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 20
1 file changed,
This patch make changes to allocate crc-entries buffer before
enabling CRC generation.
It moves all the failure check early in the function before setting
the source or memory allocation.
Now set_crc_source takes only two variable inputs, values_cnt we
already gets as part of verify_crc_source.
Si
This patch implements get_crc_sources callback, which returns list of
all the valid crc sources supported by driver in current platform.
Changes since V1:
- Return array of crc sources
Signed-off-by: Mahesh Kumar
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/i915/intel_display.c | 1
This patch implements "verify_crc_source" callback function for
AMD drm driver.
Signed-off-by: Mahesh Kumar
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4
drivers/gpu/drm/amd/d
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