On 2018.07.27 12:36:46 -0700, Lucas De Marchi wrote:
> The definition on i915_reg.h is going to change to depend on
> dev_priv->gpio_mmio_base being properly initialized. Define our own
> macros since init_generic_mmio_info() is called before than
> gpio_mmio_base being set.
>
Reviewed-by: Zhenyu
On 2018.07.27 12:36:45 -0700, Lucas De Marchi wrote:
> This is the only place that they are being used - the others use the
> GMBUS* macros that rely on dev_priv being already properly initialized.
>
Reviewed-by: Zhenyu Wang
thanks!
> Cc: intel-gvt-...@lists.freedesktop.org
> Cc: Zhenyu Wang
== Series Details ==
Series: Enable Display Stream Compression on eDP/DP
URL : https://patchwork.freedesktop.org/series/47461/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/intel_display.o
DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.
Signed-off-by: Manasi Navare
Cc: dri-de...@lists.freedesktop.org
Cc: Gaurav K Singh
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
From: Gaurav K Singh
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Manasi)
v3 (From Manasi)
* Remove the duplicate define (Suggested By:Harry Wentland)
v2: Define this struct
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP
From: "Srivatsa, Anusha"
Add defines for DSS_CTL registers.
These registers specify the big joiner, splitter,
overlap pixels and info regarding display stream
compression enabled on left or right branch.
v2:
- Add define to conditionally check the buffer target depth (James Ausmus)
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-de...@lists.freedesktop.org
Cc: Manasi
DSC params like the enable, compressed bpp, slice ocunt and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: Manasi Navare
---
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_reg.h |
From: Gaurav K Singh
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4: (From Manasi)
* Rebase on top of revised patches
v3 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
From: Gaurav K Singh
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc:
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state
When DSC is supported we need to validate the modes based on the
maximum supported compressed BPP and maximum supported slice count.
This allows us to allow the modes with pixel clock greater than the
available link BW as long as it meets the compressed BPP
and slice count requirements.
v3:
* Use
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v4(From Gaurav):
* No change.Rebase on drm-tip
v3 (From Gaurav):
* Rebase on top of Manasi's latest
This patch adds inline functions and helpers for obtaining
DP sink's supported DSC parameters like DSC sink support,
eDP compressed BPP supported, maximum slice count supported
by the sink devices, DSC line buffer bit depth supported on DP sink,
DSC sink maximum color depth by parsing
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason
This patch adds helpers for calculating the maximum compressed BPP
supported with small joiner.
This also adds a helper for calculating the slice count in case
of small joiner.
These are inside intel_dp since they take into account hardware
limitations.
v5:
* Get the max slice width from DPCD
*
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Manasi Navare
---
DSC is supported on eDP starting GEN 10 display and on DP starting
GEN 11.
This patch implements the discovery phase of DSC. On hotplug,
source reads the DSC DPCD register set (0x00060 - 0x006F) to
read the decompression capabilities of the sink device.
This entire block of registers is cached in
This patch defines the DP DSC receiver capability size that gives
total number of DP DSC DPCD registers.
This also adds a missing #defines for DP DSC support missed in the
commit id (ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature")
v3:
* MIN_SLICE_WIDTH = 2560 (Anusha)
* Define
Cc: dri-de...@lists.freedesktop.org
VESA has developed an industry standard Display Stream Compression(DSC)
for interoperable, visually lossless compression over display links to
address the needs for higher resolution displays.
This patch series enables DSC on Gen 10 eDP and Gen 11 eDP/DP
== Series Details ==
Series: firmware/dmc/icl: load v1.07 on icelake.
URL : https://patchwork.freedesktop.org/series/47450/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4597_full -> Patchwork_9816_full =
== Summary - SUCCESS ==
No regressions found.
== Known
== Series Details ==
Series: firmware/dmc/icl: load v1.07 on icelake.
URL : https://patchwork.freedesktop.org/series/47450/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4597 -> Patchwork_9816 =
== Summary - SUCCESS ==
No regressions found.
External URL:
Adding Pull request for CI to pick:
The following changes since commit 7b5835fd37630d18ac0c755329172f6a17c1af29:
linux-firmware: add firmware for mt76x2u (2018-07-30 07:20:31 -0400)
are available in the git repository at:
ssh://git.freedesktop.org/git/drm/drm-firmware master
for you to
Add Support to load DMC on Icelake.
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_csr.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index cf9b600..393d419
On Tue, 2018-07-24 at 21:50 +, Bloomfield, Jon wrote:
> Gratuitous top posting to re-kick the thread.
>
> For Gen11 we can't have an on/off switch anyway (media simply won't
> run
> with an oncompatible slice config), so let's agree on an api to allow
> userland
> to select the slice
== Series Details ==
Series: drm/i915/execlists: Terminate the context image with BB_END (rev2)
URL : https://patchwork.freedesktop.org/series/47439/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4595_full -> Patchwork_9814_full =
== Summary - WARNING ==
Minor unknown
Chris Wilson writes:
> Quoting Francisco Jerez (2018-07-29 20:29:42)
>> Chris Wilson writes:
>>
>> > Quoting Francisco Jerez (2018-07-28 21:18:50)
>> >> Chris Wilson writes:
>> >>
>> >> > Quoting Francisco Jerez (2018-07-28 06:20:12)
>> >> >> Chris Wilson writes:
>> >> >>
>> >> >> > A
On Mon, Jul 30, 2018 at 08:23:08PM +0300, Souza, Jose wrote:
> On Sat, 2018-07-28 at 11:40 +0300, Imre Deak wrote:
> > On Fri, Jul 27, 2018 at 10:19:42PM -0700, Rodrigo Vivi wrote:
> > > On Fri, Jul 27, 2018 at 04:36:24PM -0700, José Roberto de Souza
> > > wrote:
> > > > When returning from low
== Series Details ==
Series: series starting with [v4,1/3] drm/i915: make PCH_GMBUS* definitions
private to gvt
URL : https://patchwork.freedesktop.org/series/47367/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4595 -> Patchwork_9815 =
== Summary - FAILURE ==
Serious
== Series Details ==
Series: series starting with [1/3] drm/i915: Limit C-states when waiting for
the active request
URL : https://patchwork.freedesktop.org/series/47435/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4595_full -> Patchwork_9812_full =
== Summary - FAILURE
== Series Details ==
Series: drm/i915/execlists: Terminate the context image with BB_END (rev2)
URL : https://patchwork.freedesktop.org/series/47439/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4595 -> Patchwork_9814 =
== Summary - WARNING ==
Minor unknown changes
On Sat, 2018-07-28 at 11:40 +0300, Imre Deak wrote:
> On Fri, Jul 27, 2018 at 10:19:42PM -0700, Rodrigo Vivi wrote:
> > On Fri, Jul 27, 2018 at 04:36:24PM -0700, José Roberto de Souza
> > wrote:
> > > When returning from low power states the CSR firmware was not
> > > being
> > > loaded again in
== Series Details ==
Series: drm/i915/skl: distribute DDB based on panel resolution
URL : https://patchwork.freedesktop.org/series/47428/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4595_full -> Patchwork_9811_full =
== Summary - SUCCESS ==
No regressions found.
In the aub trace utility, the context images are terminated with a
MI_BATCH_BUFFER_END; the simulator is reported as complaining otherwise.
Do the same for our protocontext image for completeness, and in passing
apply the magic bit for gen10 to mark the end of the context image.
Reported-by:
== Series Details ==
Series: drm/i915/execlists: Terminate the context image with BB_END
URL : https://patchwork.freedesktop.org/series/47439/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M]
In the aub trace utility, the context images are terminated with a
MI_BATCH_BUFFER_END; the simulator is reported as complaining otherwise.
Do the same for our protocontext image for completeness, and in passing
apply the magic bit for gen10 to mark the end of the context image.
Reported-by:
== Series Details ==
Series: series starting with [1/3] drm/i915: Limit C-states when waiting for
the active request
URL : https://patchwork.freedesktop.org/series/47435/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4595 -> Patchwork_9812 =
== Summary - WARNING ==
== Series Details ==
Series: series starting with [1/3] drm/i915: Limit C-states when waiting for
the active request
URL : https://patchwork.freedesktop.org/series/47435/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Limit C-states when waiting for the active
== Series Details ==
Series: drm/i915: Limit C-states when waiting for the active request (rev6)
URL : https://patchwork.freedesktop.org/series/47420/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4594_full -> Patchwork_9810_full =
== Summary - SUCCESS ==
No regressions
== Series Details ==
Series: series starting with [1/3] drm/i915: Limit C-states when waiting for
the active request
URL : https://patchwork.freedesktop.org/series/47435/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
79a7b4257bd9 drm/i915: Limit C-states when waiting for the
Quoting Mahesh Kumar (2018-07-30 15:12:02)
> We distribute DDB equally among all pipes irrespective of display
> buffer requirement of each pipe. This leads to a situation where high
> resolution y-tiled display can not be enabled with 2 low resolution
> displays.
>
> Main contributing factor for
== Series Details ==
Series: drm/i915/skl: distribute DDB based on panel resolution
URL : https://patchwork.freedesktop.org/series/47428/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4595 -> Patchwork_9811 =
== Summary - WARNING ==
Minor unknown changes coming with
If we are waiting for the currently executing request, we have a good
idea that it will be completed in the very near future and so want to
cap the CPU_DMA_LATENCY to ensure that we wake up the client quickly.
v2: Not allowed to block in kmalloc after setting TASK_INTERRUPTIBLE.
v3: Avoid the
Just a couple of bug reports suggesting we should do better with power
distribution...
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
A recent trend for cpufreq is to boost the CPU frequencies for
iowaiters, in particularly to benefit high frequency I/O. We do the same
and boost the GPU clocks to try and minimise time spent waiting for the
GPU. However, as the igfx and CPU share the same TDP, boosting the CPU
frequency will
RPS provides a feedback loop where we use the load during the previous
evaluation interval to decide whether to up or down clock the GPU
frequency. Our responsiveness is split into 3 regimes, a high and low
plateau with the intent to keep the gpu clocked high to cover occasional
stalls under high
== Series Details ==
Series: Revert "drm/i915/icl: WaEnableFloatBlendOptimization"
URL : https://patchwork.freedesktop.org/series/47422/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4594_full -> Patchwork_9807_full =
== Summary - WARNING ==
Minor unknown changes coming
== Series Details ==
Series: drm/i915: Limit C-states when waiting for the active request (rev6)
URL : https://patchwork.freedesktop.org/series/47420/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4594 -> Patchwork_9810 =
== Summary - SUCCESS ==
No regressions found.
Quoting Patchwork (2018-07-30 15:19:10)
> == Series Details ==
>
> Series: drm/i915/gtt: remove px_page
> URL : https://patchwork.freedesktop.org/series/47421/
> State : success
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_4594_full -> Patchwork_9806_full =
>
> == Summary -
== Series Details ==
Series: drm/i915: Limit C-states when waiting for the active request (rev5)
URL : https://patchwork.freedesktop.org/series/47420/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4594 -> Patchwork_9809 =
== Summary - FAILURE ==
Serious unknown changes
== Series Details ==
Series: drm/i915/gtt: remove px_page
URL : https://patchwork.freedesktop.org/series/47421/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4594_full -> Patchwork_9806_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here
Quoting Mika Kuoppala (2018-07-30 14:59:01)
> Chris Wilson writes:
>
> > Quoting Patchwork (2018-07-30 14:23:46)
> >> == Participating hosts (51 -> 47) ==
> >>
> >> Additional (2): fi-icl-u fi-kbl-8809g
> >
> > So checking the fi-icl-u results does indeed confirm that
> > live_workarounds is
We distribute DDB equally among all pipes irrespective of display
buffer requirement of each pipe. This leads to a situation where high
resolution y-tiled display can not be enabled with 2 low resolution
displays.
Main contributing factor for DDB requirement is width of the display.
This patch
Chris Wilson writes:
> Quoting Patchwork (2018-07-30 14:23:46)
>> == Participating hosts (51 -> 47) ==
>>
>> Additional (2): fi-icl-u fi-kbl-8809g
>
> So checking the fi-icl-u results does indeed confirm that
> live_workarounds is fixed.
Hmm, gem_workarounds is fixed?
I looked at
If we are waiting for the currently executing request, we have a good
idea that it will be completed in the very near future and so want to
cap the CPU_DMA_LATENCY to ensure that we wake up the client quickly.
v2: Not allowed to block in kmalloc after setting TASK_INTERRUPTIBLE.
v3: Avoid the
== Series Details ==
Series: drm/i915: Limit C-states when waiting for the active request (rev4)
URL : https://patchwork.freedesktop.org/series/47420/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4594 -> Patchwork_9808 =
== Summary - FAILURE ==
Serious unknown changes
If we are waiting for the currently executing request, we have a good
idea that it will be completed in the very near future and so want to
cap the CPU_DMA_LATENCY to ensure that we wake up the client quickly.
v2: Not allowed to block in kmalloc after setting TASK_INTERRUPTIBLE.
v3: Avoid the
Quoting Patchwork (2018-07-30 14:23:46)
> == Participating hosts (51 -> 47) ==
>
> Additional (2): fi-icl-u fi-kbl-8809g
So checking the fi-icl-u results does indeed confirm that
live_workarounds is fixed.
-Chris
___
Intel-gfx mailing list
Quoting Mika Kuoppala (2018-07-30 14:07:07)
> Chris Wilson writes:
>
> > If we are waiting for the currently executing request, we have a good
> > idea that it will be completed in the very near future and so want to
> > cap the CPU_DMA_LATENCY to ensure that we wake up the client quickly.
> >
>
== Series Details ==
Series: Revert "drm/i915/icl: WaEnableFloatBlendOptimization"
URL : https://patchwork.freedesktop.org/series/47422/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4594 -> Patchwork_9807 =
== Summary - SUCCESS ==
No regressions found.
External URL:
Chris Wilson writes:
> If we are waiting for the currently executing request, we have a good
> idea that it will be completed in the very near future and so want to
> cap the CPU_DMA_LATENCY to ensure that we wake up the client quickly.
>
> v2: Not allowed to block in kmalloc after setting
== Series Details ==
Series: drm/i915/gtt: remove px_page
URL : https://patchwork.freedesktop.org/series/47421/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4594 -> Patchwork_9806 =
== Summary - SUCCESS ==
No regressions found.
External URL:
Quoting Francisco Jerez (2018-07-29 20:29:42)
> Chris Wilson writes:
>
> > Quoting Francisco Jerez (2018-07-28 21:18:50)
> >> Chris Wilson writes:
> >>
> >> > Quoting Francisco Jerez (2018-07-28 06:20:12)
> >> >> Chris Wilson writes:
> >> >>
> >> >> > A recent trend for cpufreq is to boost
If we are waiting for the currently executing request, we have a good
idea that it will be completed in the very near future and so want to
cap the CPU_DMA_LATENCY to ensure that we wake up the client quickly.
v2: Not allowed to block in kmalloc after setting TASK_INTERRUPTIBLE.
v3: Avoid the
Quoting Chris Wilson (2018-07-30 13:25:03)
> Quoting Chris Wilson (2018-07-30 13:14:09)
> > + if (!pm_qos &&
> > + i915_seqno_passed(intel_engine_get_seqno(rq->engine),
> > + wait.seqno - 1)) {
> > + pm_qos =
Quoting Chris Wilson (2018-07-30 13:14:09)
> If we are waiting for the currently executing request, we have a good
> idea that it will be completed in the very near future and so want to
> cap the CPU_DMA_LATENCY to ensure that we wake up the client quickly.
>
> v2: Not allowed to block in
Matthew Auld writes:
> Entries will either be pointing to scratch or real PD, making the
> px_page(pd) check pointless. Also since there are no other users of
> px_page, just remove it.
>
Yup. Callsites return enomem and free the struct so
we should not leak any partially setup structs.
Quoting Matthew Auld (2018-07-30 13:05:44)
> Entries will either be pointing to scratch or real PD, making the
> px_page(pd) check pointless. Also since there are no other users of
> px_page, just remove it.
>
> Signed-off-by: Matthew Auld
> Cc: Chris Wilson
> Cc: Michel Thierry
Reviewed-by:
Quoting Mika Kuoppala (2018-07-30 13:06:36)
> The register for 0xe420 is unable to hold any value, including
> this bit. The documentation is also mixed between having a
> register bit for toggle and having a state command setup
> for it. Apparently the register toggle is deprecated.
>
> Remove
If we are waiting for the currently executing request, we have a good
idea that it will be completed in the very near future and so want to
cap the CPU_DMA_LATENCY to ensure that we wake up the client quickly.
v2: Not allowed to block in kmalloc after setting TASK_INTERRUPTIBLE.
Testcase:
The register for 0xe420 is unable to hold any value, including
this bit. The documentation is also mixed between having a
register bit for toggle and having a state command setup
for it. Apparently the register toggle is deprecated.
Remove the register toggle as evidence shows it's futile.
The
== Series Details ==
Series: drm/i915: Limit C-states when waiting for the active request (rev2)
URL : https://patchwork.freedesktop.org/series/47420/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4592 -> Patchwork_9805 =
== Summary - FAILURE ==
Serious unknown changes
Entries will either be pointing to scratch or real PD, making the
px_page(pd) check pointless. Also since there are no other users of
px_page, just remove it.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ---
If we are waiting for the currently executing request, we have a good
idea that it will be completed in the very near future and so want to
cap the CPU_DMA_LATENCY to ensure that we wake up the client quickly.
Testcase: igt/gem_sync/store-default
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
If we are waiting for the currently executing request, we have a good
idea that it will be completed in the very near future and so want to
cap the CPU_DMA_LATENCY to ensure that we wake up the client quickly.
Testcase: igt/gem_sync/store-default
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
== Series Details ==
Series: series starting with [1/2] drm/i915: Kick waiters on resetting legacy
rings
URL : https://patchwork.freedesktop.org/series/47412/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4591_full -> Patchwork_9804_full =
== Summary - SUCCESS ==
No
Op 28-07-18 om 07:23 schreef Dhinakaran Pandiyan:
> On Fri, 2018-07-27 at 10:41 +0200, Maarten Lankhorst wrote:
>> Op 27-07-18 om 05:27 schreef Dhinakaran Pandiyan:
>>> On Thu, 2018-07-26 at 11:06 +0200, Maarten Lankhorst wrote:
Currently tests modify i915.enable_psr and then do a modeset
Quoting Matthew Auld (2018-07-30 10:27:00)
> On 30 July 2018 at 08:53, Chris Wilson wrote:
> > For reasons unknown, interrupts following a reset do not arrive, but
> > this can be papered over by kicking any waiter and peeking at the
> > breadcrumbs following the reset.
> >
> > Testcase:
On 30 July 2018 at 08:53, Chris Wilson wrote:
> For reasons unknown, interrupts following a reset do not arrive, but
> this can be papered over by kicking any waiter and peeking at the
> breadcrumbs following the reset.
>
> Testcase: igt/gem_eio/reset-stress
> Signed-off-by: Chris Wilson
On 30 July 2018 at 08:53, Chris Wilson wrote:
> We occasionally see that the clflush prior to a read of GPU data is
> returning stale data, reminiscent of much earlier bugs fixed by adding a
> second clflush for serialisation. As drm_clflush_virt_range() already
> supplies the workaround, use it
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Saturday, July 14, 2018 8:45 AM
>To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
>;
== Series Details ==
Series: series starting with [1/2] drm/i915: Kick waiters on resetting legacy
rings
URL : https://patchwork.freedesktop.org/series/47412/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4591 -> Patchwork_9804 =
== Summary - SUCCESS ==
No regressions
== Series Details ==
Series: series starting with [1/2] drm/i915: Kick waiters on resetting legacy
rings
URL : https://patchwork.freedesktop.org/series/47412/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cf9560edd0f1 drm/i915: Kick waiters on resetting legacy rings
Quoting Chris Wilson (2018-07-26 17:15:27)
> According to intel_read_wm_latency() it is perfectly legal for one WM
> and all subsequent levels to be 0 (and the deeper powersaving states
> disabled), so don't shout *ERROR*, over and over again.
>
> Signed-off-by: Chris Wilson
> Cc: Maarten
We occasionally see that the clflush prior to a read of GPU data is
returning stale data, reminiscent of much earlier bugs fixed by adding a
second clflush for serialisation. As drm_clflush_virt_range() already
supplies the workaround, use it rather than open code the clflush
instruction.
For reasons unknown, interrupts following a reset do not arrive, but
this can be papered over by kicking any waiter and peeking at the
breadcrumbs following the reset.
Testcase: igt/gem_eio/reset-stress
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
1 file
Just a pair of bug silencers that should be quite tame,
-Chris
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On Fri, Jul 20, 2018 at 05:14:56PM +0300, Imre Deak wrote:
> intel_power_domains_fini() rolls back what was done in
> intel_power_domains_init_hw(), so rename and move it accordingly. This
> allows us adding a cleanup function later for intel_power_domains_init()
> in a cleaner way.
>
> No
On Fri, Jul 20, 2018 at 05:14:55PM +0300, Imre Deak wrote:
> Similarly to
> 0a445945be6d ("drm/i915: Work around GCC anonymous union initialization bug")
> we need to initialize anonymous unions inside extra braces to work
> around a GCC4.4 build error.
>
> Cc: Chris Wilson
> Cc: Ville Syrjala
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