On Wednesday 01 August 2018 04:15 PM, Shankar, Uma wrote:
-Original Message-
From: C, Ramalingam
Sent: Saturday, July 14, 2018 8:45 AM
To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
; Usyskin, Alexander ;
Sh
On Wednesday 01 August 2018 04:00 PM, Shankar, Uma wrote:
-Original Message-
From: C, Ramalingam
Sent: Saturday, July 14, 2018 8:45 AM
To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
; Usyskin, Alexander ;
Sh
On Wednesday 01 August 2018 03:11 PM, Shankar, Uma wrote:
-Original Message-
From: C, Ramalingam
Sent: Saturday, July 14, 2018 8:45 AM
To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
dan...@ffwll.ch; seanp...@chromium.org; Winkler, Tomas
; Usyskin, Alexander ;
Sh
On Thu, Aug 23, 2018 at 08:16:28AM -0400, Jyoti Yadav wrote:
> From: Jyoti
>
> BIOS programs few of PWM related registers during initial boot.
> But during System suspend those registers are cleared.
> This test aim to check whether display programs those registers properly after
> system resume.
On 29/08/2018 20:58, Michel Thierry wrote:
+Lionel
(please see below as this touches the lrca format & relates to OA
reporting too)
On 8/29/2018 12:10 PM, Michal Wajdeczko wrote:
Until now the GuC and HW engine class has been the same, which allowed
us to use them interchangeable. But it is b
On 29/08/2018 20:16, Michal Wajdeczko wrote:
The new context descriptor format contains two assignable fields:
the SW Context ID (technically 11 bits, but practically limited to 2032
entries due to some being reserved for future use by the GuC) and the
SW Counter (6 bits).
We don't want to limit
On Wed, Aug 29, 2018 at 05:28:23PM -0400, Lyude Paul wrote:
> On Wed, 2018-08-29 at 14:22 -0700, Rodrigo Vivi wrote:
> > On Mon, Aug 27, 2018 at 01:39:02PM -0400, Lyude Paul wrote:
> > > On Mon, 2018-08-27 at 11:43 +0300, Jani Nikula wrote:
> > > > On Sat, 25 Aug 2018, Lyude Paul wrote:
> > > > >
Hi Dave,
Here goes drm-intel-fixes-2018-08-29:
- fix for GLK and CNL watermark workaround
- fix for display affecting NUCs with LSPCON
- freeing an allocated write_buf on hdcp
- audio hook when display is disabled
- vma stop holding ppgtt reference
Thanks,
Rodrigo.
The following changes since c
On 29/08/18 12:18, Michal Wajdeczko wrote:
New GuC stage descriptor stores information about all possible HW contexts
that use it. The idea is that every direct-submission GuC client gets one
SW Context ID and every HW context created by that client gets one SW
Counter (up to 64 entries). The c
== Series Details ==
Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate
URL : https://patchwork.freedesktop.org/series/48906/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/selftests: Add a simple exerciser for suspend/hibernate
+drivers/gpu/dr
== Series Details ==
Series: drm/i915/selftests: Add a simple exerciser for suspend/hibernate
URL : https://patchwork.freedesktop.org/series/48906/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a315eea06821 drm/i915/selftests: Add a simple exerciser for suspend/hibernate
-:31:
On Mon, Aug 27, 2018 at 04:31:49PM +0300, Ville Syrjälä wrote:
> On Fri, Aug 24, 2018 at 06:02:16PM -0700, Radhakrishna Sripada wrote:
> > At times 12bpc HDMI cannot be driven due to faulty cables, dongles
> > level shifters etc. To workaround them we may need to drive the output
> > at a lower bpc
== Series Details ==
Series: New GuC ABI (resend for CI)
URL : https://patchwork.freedesktop.org/series/48896/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/guc: Update GuC power domain states
Okay!
Commit: drm/i915/guc: Don't allow GuC submission on pre-Gen11
Oka
On Wed, 29 Aug 2018 22:57:54 +0200, Daniele Ceraolo Spurio
wrote:
On 29/08/18 12:10, Michal Wajdeczko wrote:
We should update GuC power domain states also when GuC submission
is disabled, otherwise GuC might complain or ignore our requests.
This seems to be required for all currently relea
== Series Details ==
Series: New GuC ABI (resend for CI)
URL : https://patchwork.freedesktop.org/series/48896/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
01e55a38a7a5 drm/i915/guc: Update GuC power domain states
3b815ce8b593 drm/i915/guc: Don't allow GuC submission on pre-Ge
On Wed, 29 Aug 2018 23:52:26 +0200, Daniele Ceraolo Spurio
wrote:
On 29/08/18 12:10, Michal Wajdeczko wrote:
Action ID of this command has been changed in GuC firmware.
the commit message of patch 1 says we need to use this command even if
GuC submission is disabled, which is still a
Although we cannot do a full system-level test of suspend/hibernate from
deep with the kernel selftests, we can exercise the GEM subsystem in
isolation and simulate the external effects (such as losing stolen
contents and trashing the register state).
Signed-off-by: Chris Wilson
Cc: Jakub Bartmiń
On 29/08/18 12:10, Michal Wajdeczko wrote:
Action ID of this command has been changed in GuC firmware.
the commit message of patch 1 says we need to use this command even if
GuC submission is disabled, which is still a supported config on gen9.
However, won't changing the value make the H2
On Wed, 2018-08-29 at 14:22 -0700, Rodrigo Vivi wrote:
> On Mon, Aug 27, 2018 at 01:39:02PM -0400, Lyude Paul wrote:
> > On Mon, 2018-08-27 at 11:43 +0300, Jani Nikula wrote:
> > > On Sat, 25 Aug 2018, Lyude Paul wrote:
> > > > From: Jan-Marek Glogowski
> > > >
> > > > This re-applies the workar
On Mon, Aug 27, 2018 at 01:39:02PM -0400, Lyude Paul wrote:
> On Mon, 2018-08-27 at 11:43 +0300, Jani Nikula wrote:
> > On Sat, 25 Aug 2018, Lyude Paul wrote:
> > > From: Jan-Marek Glogowski
> > >
> > > This re-applies the workaround for "some DP sinks, [which] are a
> > > little nuts" from comm
On 29/08/18 12:10, Michal Wajdeczko wrote:
We should update GuC power domain states also when GuC submission
is disabled, otherwise GuC might complain or ignore our requests.
This seems to be required for all currently released GuC firmwares.
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
Quoting Michal Wajdeczko (2018-08-29 20:36:23)
> In upcoming GuC patch we will require notification per engine context
> allocation/update/free to correctly setup GuC stage descriptors.
I'm cringing at this. I've a plan that is basically to do
ce = engine->context_create(engine, gem_context); or _
+Lionel
(please see below as this touches the lrca format & relates to OA
reporting too)
On 8/29/2018 12:10 PM, Michal Wajdeczko wrote:
Until now the GuC and HW engine class has been the same, which allowed
us to use them interchangeable. But it is better to start doing the
right thing and use
Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.
Bspec: 21043
Signed-off-by: Michal Wajdeczko
Starting from Gen11, the ID to be provided to GuC needs to contain
the engine class in bits [0..2] and the instance in bits [3..6].
NOTE: this patch breaks pointer dereferences in some existing GuC
functions that use the guc_id to dereference arrays but these functions
are not used for now as we h
In upcoming GuC patch we will require notification per engine context
allocation/update/free to correctly setup GuC stage descriptors.
Signed-off-by: Michal Wajdeczko
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Tomasz Lis
Cc: Michal Winiarski
---
drivers/gpu/drm/i9
Work queue items definitions were updated.
To simplify the scheduling logic in the GuC firmware, now only
out-of-order mode of scheduling is supported.
Credits-to: Michel Thierry
Signed-off-by: Michal Wajdeczko
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Michał Winia
Format of the ENGINE_RESET H2G message has been updated. Additionally,
the firmware will send a G2H ENGINE_RESET_COMPLETE message (with the
engine's guc_class in data[2]) to confirm that the reset has been
completed (but this will be handled in a other patch).
Requires GuC fw v25.161+.
Credits-to
Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.
Bspec: 21044
Signed-off-by: Michal W
Gen11 GuC firmware can handle commands over CT buffers.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
BSpec: 19686
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc: Michel Thierry
Cc: John Spotswood
Cc: Anusha Srivatsa
---
driver
New GuC stage descriptor stores information about all possible HW contexts
that use it. The idea is that every direct-submission GuC client gets one
SW Context ID and every HW context created by that client gets one SW
Counter (up to 64 entries). The correct SW Context ID and SW Counter now
get pas
The new context descriptor format contains two assignable fields:
the SW Context ID (technically 11 bits, but practically limited to 2032
entries due to some being reserved for future use by the GuC) and the
SW Counter (6 bits).
We don't want to limit ourselves too much in the maximum number of
co
Upcoming Gen11 GuC firmware requires new interface that is incompatible
with existing pre-Gen11 firmwares. Updated firmwares for pre-Gen11 will
arrive later. In the meantime sanitize the enable_guc option so that we
can enable HuC authentication but nothing else on pre-Gen11.
Signed-off-by: Michal
This series introduces new Gen11 GuC ABI. Unfortunatelly
this new ABI is not backward compatible, so for a while we
will only support HuC authentication for pre-Gen11 GuC until
new firmwares will be released.
Note: To pass CI.BAT on machines with GuC, HAX will modify
forced modparam to disable GuC
Gen11 GuC boot parameter definitions are different than previously
used for Gen9. Try to support both definitions until new firmwares
for pre-Gen11 will be available.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Cc: John Sp
Since fw version 25.161, GuC lets us know when an engine had to be reset
due to a hang in another dependent engine, by setting BIT(engine_class) in
the queue_engine_error field. GuC will ignore any other wq item until this
flag is cleared.
To restart the workqueue processing for that engine, we mu
Until now the GuC and HW engine class has been the same, which allowed
us to use them interchangeable. But it is better to start doing the
right thing and use the GuC definitions for the firmware interface.
We also keep the same class id in the ctx descriptor to be able to have
the same values in
Action ID of this command has been changed in GuC firmware.
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel
This is just to fool CI skl|kbl-guc machines
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_uc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 185b29b..95697c0 100644
--- a/drivers/gpu/drm/i915/intel_
GuC may send notification messages with payload larger than
single u32. Prepare driver to accept those messages.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Cc: Vinay Belgaumkar
Cc: Michal Winiarski
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_guc.c| 1
GuC sends ENGINE_RESET_COMPLETE message as an follow-up answer
to earlier ENGINE_RESET request from the host. Once this message
is received, clear engine reset flag to unblock our reset process.
Credits-to: Michel Thierry
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thi
Definition of the Additional Data Structure (ADS) object and
some of its sub-structs has been updated in the GuC firmware.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_engine_cs.c | 5 ++
dri
Definition of the parameters block passed to GuC is about to change.
Slightly refactor code now to make upcoming patch smaller.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc.c | 38 +++---
1 file change
We should update GuC power domain states also when GuC submission
is disabled, otherwise GuC might complain or ignore our requests.
This seems to be required for all currently released GuC firmwares.
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
Cc: Anusha Srivatsa
Cc: Tomasz Lis
---
dri
Gen11 GuC firmware can handle commands over CT buffers.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i
Starting from Gen11, the ID to be provided to GuC needs to contain
the engine class in bits [0..2] and the instance in bits [3..6].
NOTE: this patch breaks pointer dereferences in some existing GuC
functions that use the guc_id to dereference arrays but these functions
are not used for now as we h
This is just to fool CI skl|kbl-guc machines
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_uc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 185b29b..95697c0 100644
--- a/drivers/gpu/drm/i915/intel_
Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.
Bspec: 21044
Signed-off-by: Michal W
GuC may send notification messages with payload larger than
single u32. Prepare driver to accept those messages.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Cc: Vinay Belgaumkar
Cc: Michal Winiarski
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_guc.c| 1
Since fw version 25.161, GuC lets us know when an engine had to be reset
due to a hang in another dependent engine, by setting BIT(engine_class) in
the queue_engine_error field. GuC will ignore any other wq item until this
flag is cleared.
To restart the workqueue processing for that engine, we mu
GuC sends ENGINE_RESET_COMPLETE message as an follow-up answer
to earlier ENGINE_RESET request from the host. Once this message
is received, clear engine reset flag to unblock our reset process.
Credits-to: Michel Thierry
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thi
Gen11 defines new register for checking HuC authentication status.
Look into the right register and bit.
BSpec: 19686
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc: Michel Thierry
Cc: John Spotswood
Cc: Anusha Srivatsa
---
driver
Format of the ENGINE_RESET H2G message has been updated. Additionally,
the firmware will send a G2H ENGINE_RESET_COMPLETE message (with the
engine's guc_class in data[2]) to confirm that the reset has been
completed (but this will be handled in a other patch).
Requires GuC fw v25.161+.
Credits-to
Work queue items definitions were updated.
To simplify the scheduling logic in the GuC firmware, now only
out-of-order mode of scheduling is supported.
Credits-to: Michel Thierry
Signed-off-by: Michal Wajdeczko
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Michał Winia
Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.
Bspec: 21043
Signed-off-by: Michal Wajdeczko
New GuC stage descriptor stores information about all possible HW contexts
that use it. The idea is that every direct-submission GuC client gets one
SW Context ID and every HW context created by that client gets one SW
Counter (up to 64 entries). The correct SW Context ID and SW Counter now
get pas
In upcoming GuC patch we will require notification per engine context
allocation/update/free to correctly setup GuC stage descriptors.
Signed-off-by: Michal Wajdeczko
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Tomasz Lis
Cc: Michal Winiarski
---
drivers/gpu/drm/i9
On Wed, 2018-08-29 at 21:10 +0300, Ville Syrjälä wrote:
> On Wed, Aug 29, 2018 at 02:28:47PM +0300, Stanislav Lisovskiy wrote:
> > PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> > specification.
> >
> > v2: Edited commit message, removed redundant whitespaces.
> >
> > v3: F
>-Original Message-
>From: Wajdeczko, Michal
>Sent: Wednesday, August 29, 2018 12:11 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Wajdeczko, Michal ; Joonas Lahtinen
>; Vivi, Rodrigo ;
>Ceraolo Spurio, Daniele ; Thierry, Michel
>; Spotswood, John A ;
>Belgaumkar, Vinay ; Ye, Tony
>; Sriva
The new context descriptor format contains two assignable fields:
the SW Context ID (technically 11 bits, but practically limited to 2032
entries due to some being reserved for future use by the GuC) and the
SW Counter (6 bits).
We don't want to limit ourselves too much in the maximum number of
co
Definition of the Additional Data Structure (ADS) object and
some of its sub-structs has been updated in the GuC firmware.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_engine_cs.c | 5 ++
dri
Action ID of this command has been changed in GuC firmware.
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel
Gen11 GuC boot parameter definitions are different than previously
used for Gen9. Try to support both definitions until new firmwares
for pre-Gen11 will be available.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Cc: John Sp
Until now the GuC and HW engine class has been the same, which allowed
us to use them interchangeable. But it is better to start doing the
right thing and use the GuC definitions for the firmware interface.
We also keep the same class id in the ctx descriptor to be able to have
the same values in
Upcoming Gen11 GuC firmware requires new interface that is incompatible
with existing pre-Gen11 firmwares. Updated firmwares for pre-Gen11 will
arrive later. In the meantime sanitize the enable_guc option so that we
can enable HuC authentication but nothing else on pre-Gen11.
Signed-off-by: Michal
Definition of the parameters block passed to GuC is about to change.
Slightly refactor code now to make upcoming patch smaller.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc.c | 38 +++---
1 file change
We should update GuC power domain states also when GuC submission
is disabled, otherwise GuC might complain or ignore our requests.
This seems to be required for all currently released GuC firmwares.
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
Cc: Anusha Srivatsa
Cc: Tomasz Lis
---
dri
This series introduces new Gen11 GuC ABI. Unfortunatelly
this new ABI is not backward compatible, so for a while we
will only support HuC authentication for pre-Gen11 GuC until
new firmwares will be released.
Note: To pass CI.BAT on machines with GuC, HAX will modify
forced modparam to disable GuC
Hi Jyoti,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.19-rc1 next-20180829]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com
On Wed, Aug 29, 2018 at 02:28:47PM +0300, Stanislav Lisovskiy wrote:
> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> specification.
>
> v2: Edited commit message, removed redundant whitespaces.
>
> v3: Fixed fallthrough logic for the format switch cases.
>
> v4: Yet again f
On Wed, Aug 29, 2018 at 11:32:35AM +0100, Chris Wilson wrote:
> Quoting Lucas De Marchi (2018-08-29 01:35:31)
> > The 2 PCI IDs that are used for the command line overrid mechanism
> > were left defined.
>
> What makes them so special? Why not just match on the override devid?
because it's a name
Hi Jyoti,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.19-rc1 next-20180829]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
Quoting Kukanova, Svetlana (2018-08-27 16:37:14)
> > Once there is an actual request to have some metrics from vanilla kernels
> > through some end-user tools (not a developer tool, like here), I'll be glad
> > to discuss about how to provide the information the best for them in a
> > stable manner
Quoting Lucas De Marchi (2018-08-29 01:35:32)
> We don't need to call IS_GEN() for each gen >= 9: we can rather use the
> new intel_is_genx() helper to iterate the pciids array once.
>
> Signed-off-by: Lucas De Marchi
> ---
> intel/intel_bufmgr_gem.c | 8 +---
> intel/intel_decode.c | 8
On Tue 2018-08-21 00:14:35, Dmitry Safonov wrote:
> Hi Petr, thanks for review,
>
> On Wed, 2018-08-15 at 17:10 +0200, Petr Mladek wrote:
> > On Tue 2018-07-03 23:56:28, Dmitry Safonov wrote:
> > > Currently ratelimit_state is protected with spin_lock. If the .lock
> > > is
> > > taken at the mome
Quoting Mika Kuoppala (2018-08-29 13:38:27)
> Chris Wilson writes:
>
> > On finishing the reset, the intention is to restart the GPU before we
> > relinquish the forcewake taken to handle the reset - the goal being the
> > GPU reloads a context before it is allowed to sleep. For this purpose,
> >
Chris Wilson writes:
> On finishing the reset, the intention is to restart the GPU before we
> relinquish the forcewake taken to handle the reset - the goal being the
> GPU reloads a context before it is allowed to sleep. For this purpose,
> we used tasklet_flush() which although it accomplished
On 29/08/2018 13:29, Tvrtko Ursulin wrote:
On 29/08/2018 13:11, Tvrtko Ursulin wrote:
On 29/08/2018 13:09, Tvrtko Ursulin wrote:
On 29/08/2018 13:02, Tvrtko Ursulin wrote:
On 29/08/2018 12:07, Lionel Landwerlin wrote:
On 29/08/2018 11:54, Tvrtko Ursulin wrote:
On 22/08/2018 17:33, Lion
On 29/08/2018 13:11, Tvrtko Ursulin wrote:
On 29/08/2018 13:09, Tvrtko Ursulin wrote:
On 29/08/2018 13:02, Tvrtko Ursulin wrote:
On 29/08/2018 12:07, Lionel Landwerlin wrote:
On 29/08/2018 11:54, Tvrtko Ursulin wrote:
On 22/08/2018 17:33, Lionel Landwerlin wrote:
On 22/08/2018 17:18, T
On 29/08/2018 13:09, Tvrtko Ursulin wrote:
On 29/08/2018 13:02, Tvrtko Ursulin wrote:
On 29/08/2018 12:07, Lionel Landwerlin wrote:
On 29/08/2018 11:54, Tvrtko Ursulin wrote:
On 22/08/2018 17:33, Lionel Landwerlin wrote:
On 22/08/2018 17:18, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
On 29/08/2018 13:02, Tvrtko Ursulin wrote:
On 29/08/2018 12:07, Lionel Landwerlin wrote:
On 29/08/2018 11:54, Tvrtko Ursulin wrote:
On 22/08/2018 17:33, Lionel Landwerlin wrote:
On 22/08/2018 17:18, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Bitfield width for configuring the active slic
On 29/08/2018 12:07, Lionel Landwerlin wrote:
On 29/08/2018 11:54, Tvrtko Ursulin wrote:
On 22/08/2018 17:33, Lionel Landwerlin wrote:
On 22/08/2018 17:18, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Bitfield width for configuring the active slice count has grown in
Gen11
so we need to pr
On Tue, Aug 28, 2018 at 06:19:44PM -0700, Dhinakaran Pandiyan wrote:
>
>
>
> On Fri, 2018-06-01 at 20:00 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Let's try to stick a common naming pattern in all the plane init
> > funcs.
> >
>
> Since you are moving things around, do you
== Series Details ==
Series: Add XYUV format support (rev3)
URL : https://patchwork.freedesktop.org/series/48007/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
015d06e009fe drm: Introduce new DRM_FORMAT_XYUV
-:24: WARNING:LONG_LINE: line over 100 characters
#24: FILE: drivers/g
v5: This is YUV444 packed format same as AYUV, but without alpha,
as supported by i915.
v6: Removed unneeded initializer for new XYUV format.
v7: Added is_yuv field initialization according to latest
drm_fourcc format structure initialization changes.
Signed-off-by: Stanislav Lisovskiy
Introduced new XYUV scan-in format for framebuffer and
added support for it to i915 driver.
Stanislav Lisovskiy (2):
drm: Introduce new DRM_FORMAT_XYUV
drm/i915: Adding YUV444 packed format(DRM_FORMAT_XYUV) support.
drivers/gpu/drm/drm_fourcc.c | 1 +
drivers/gpu/drm/i915/intel_displ
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use
On 29/08/2018 11:54, Tvrtko Ursulin wrote:
On 22/08/2018 17:33, Lionel Landwerlin wrote:
On 22/08/2018 17:18, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Bitfield width for configuring the active slice count has grown in
Gen11
so we need to program the GEN8_R_PWR_CLK_STATE accordingly.
Cur
On 22/08/2018 17:33, Lionel Landwerlin wrote:
On 22/08/2018 17:18, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Bitfield width for configuring the active slice count has grown in Gen11
so we need to program the GEN8_R_PWR_CLK_STATE accordingly.
Current code was always requesting eight times th
On Wed, 29 Aug 2018, vsrini4 wrote:
> GEN11 supports 6 sprite planes. Making the change
> in intel_device_info.c accordingly
>
> Signed-off-by: vsrini4
Please fix your git name. It's supposed to be your real name, not
username.
Thanks,
Jani.
> ---
> drivers/gpu/drm/i915/intel_device_info.c |
On 23/08/2018 09:59, Tvrtko Ursulin wrote:
On 22/08/2018 16:47, Lionel Landwerlin wrote:
On 22/08/2018 16:27, Tvrtko Ursulin wrote:
On 22/08/2018 16:22, Lionel Landwerlin wrote:
On 22/08/2018 16:17, Tvrtko Ursulin wrote:
On 22/08/2018 16:08, Lionel Landwerlin wrote:
On 22/08/2018 15:29, T
Quoting Lucas De Marchi (2018-08-29 01:35:31)
> The 2 PCI IDs that are used for the command line overrid mechanism
> were left defined.
What makes them so special? Why not just match on the override devid?
-Chris
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On Tue, Aug 28, 2018 at 01:49:01PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Don't check power domains state in
> intel_power_domains_init_hw() (rev2)
> URL : https://patchwork.freedesktop.org/series/48794/
> State : success
Pushed to -dinq, thanks for the review.
>
Ping.
This patch was independently verified working (see the linked bug
report) and is essential for Xorg 1.20 using this driver.
On Tue, Aug 14, 2018 at 02:16:07AM +0200, Peter Wu wrote:
> Since xorg-server 1.20, an external monitor would remain blank when used
> in a PRIME output slave setup. O
Hi Imre,
I also checked in Bspec. Good catch:)
FW size = (End address - Start Address) + 1
Will update the patch also. Thanks for quickly reviewing the patch.
Regards
Jyoti
_
On 8/29/2018 2:51 PM, Imre Deak wrote:
On Tue, Aug 28, 2018 at 03:24:19PM -0400, Jyoti Yadav wrote:
From: Jyoti
T
On Tue, Aug 28, 2018 at 03:24:19PM -0400, Jyoti Yadav wrote:
> From: Jyoti
>
> This patch resolves the DMC FW loading issue.
> Earlier DMC FW package have only one DMC FW for one stepping. But as such
> there is no such restriction from Package side.
> For ICL icl_dmc_ver1_07.bin binary package h
== Series Details ==
Series: drm/i915/icl: GEN11 supports 6 sprite planes
URL : https://patchwork.freedesktop.org/series/48859/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4723 -> Patchwork_10039 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_1
GEN11 supports 6 sprite planes. Making the change
in intel_device_info.c accordingly
Signed-off-by: vsrini4
---
drivers/gpu/drm/i915/intel_device_info.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_
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