Hi,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Matt Roper
> Sent: keskiviikko 12. joulukuuta 2018 2.05
> To: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with
> [CI,1/2]
> d
Hi Tvrtko,
On Tue, Dec 11, 2018 at 5:18 PM Tvrtko Ursulin
wrote:
>
>
> On 11/12/2018 10:14, Ankit Navik wrote:
> > drm/i915: Context aware user agnostic EU/Slice/Sub-slice control
> > within kernel
> >
> > Current GPU configuration code for i915 does not allow us to change
> > EU/Slice/Sub-sl
Hi Tvrtko,
> On Tue, Dec 11, 2018 at 6:17 PM Tvrtko Ursulin
> wrote:
>
>
> On 11/12/2018 10:14, Ankit Navik wrote:
> > From: Praveen Diwakar
> >
> > This patch will select optimum eu/slice/sub-slice configuration based
> > on type of load (low, medium, high) as input.
> > Based on our readin
Hi Daniel and Chris,
Could you take a look on all the patches? Can we get your RB or AB on all
patches including igt patch before we submit to drm-misc?
We already fix all existing issues, and also add test case in IGT as your
required.
Btw, the patch set is tested by below tests:
a. vulkan
== Series Details ==
Series: Add gamma/degamma LUT validation helpers
URL : https://patchwork.freedesktop.org/series/53929/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11075_full
Summary
---
== Series Details ==
Series: drm/i915: correct the pitch check for NV12 framebuffer
URL : https://patchwork.freedesktop.org/series/53928/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11074_full
Summa
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev3)
URL : https://patchwork.freedesktop.org/series/25091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11073_full
Su
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: f7fe8bac92bfd7ceef37f46fbeb9a6c1bac66125
commit: 2c6557b1fc4d6cc24938a27742ac396be7b55e70 [5/10] Merge remote-tracking
branch 'drm-misc/drm-misc-next' into drm-tip
config: i386-randconfig-sb0-12120454 (attached as .config)
compiler:
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev4)
URL : https://patchwork.freedesktop.org/series/53340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11072_full
=
== Series Details ==
Series: Add gamma/degamma LUT validation helpers
URL : https://patchwork.freedesktop.org/series/53929/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11075
Summary
---
**SUCCESS*
== Series Details ==
Series: Add gamma/degamma LUT validation helpers
URL : https://patchwork.freedesktop.org/series/53929/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
520a78550419 drm: Add color management LUT validation helpers
-:69: CHECK:SPACING: spaces preferred around t
We currently program userspace-provided gamma and degamma LUT's into our
hardware without really checking to see whether they satisfy our
hardware's rules. We should try to catch tables that are invalid for
our hardware early and reject the atomic transaction.
All of our platforms that accept a d
== Series Details ==
Series: drm/i915: correct the pitch check for NV12 framebuffer
URL : https://patchwork.freedesktop.org/series/53928/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11074
Summary
---
Some hardware may place additional restrictions on the gamma/degamma
curves described by our LUT properties. E.g., that a gamma curve never
decreases or that the red/green/blue channels of a LUT's entries must be
equal. Let's add a couple helpers that drivers can use to test that a
userspace-prov
Some platforms require that gamma or degamma LUT's have certain
characteristics in order to be programmed into the hardware. If a
userspace-provided LUT violates a platform's hardware requirements, we
want to be able to catch this during the atomic check and reject the
transaction rather than just
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: f7fe8bac92bfd7ceef37f46fbeb9a6c1bac66125
commit: 2c6557b1fc4d6cc24938a27742ac396be7b55e70 [5/10] Merge remote-tracking
branch 'drm-misc/drm-misc-next' into drm-tip
config: x86_64-randconfig-s4-12120354 (attached as .config)
compiler
== Series Details ==
Series: drm/i915: DFSM pipe disable is valid from gen9 onwards (rev2)
URL : https://patchwork.freedesktop.org/series/53900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11070_full
framebuffer for NV12 requires the pitch to the multiplier of 4, instead
of the width. This patch corrects it.
For instance, a 480p video, whose width and pitch are 854 and 896
respectively, is excluded for NV12 plane so far.
Signed-off-by: Dongseong Hwang
Cc: Chandra Konduru
Cc: Vidya Srinivas
On Tue, Dec 11, 2018 at 11:25:45AM -0800, Bob Paauwe wrote:
> It's not just GEN9 platforms that allow for pipes to be disabled via
> the DFSM register, but all later platforms as well.
>
> v2: drop pointless parentheses (Ville)
>
> Signed-off-by: Bob Paauwe
Reviewed-by: Matt Roper
Pushed to d
The rc6 pass->skip mentioned below doesn't appear to be related to this
series, so pushing to dinq. Thanks to Ville for reviewing.
I also notice that CI indicates a bunch of pre-existing ICL watermark
failures are no longer happening with my series (or the earlier
revisions of my series), so it's
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method (rev2)
URL : https://patchwork.freedesktop.org/series/53901/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11069_full
=
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev3)
URL : https://patchwork.freedesktop.org/series/25091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11073
Summary
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev3)
URL : https://patchwork.freedesktop.org/series/25091/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9feff89ee8cd drm: Add HDR source metadata property
9274c63b5377 drm: Add CEA extended tag b
On Tue, 2018-12-04 at 15:00 -0800, José Roberto de Souza wrote:
> The value of this registers will be used to test if PSR2 is doing
> selective update and if the number of blocks match with the expected.
>
> Cc: Rodrigo Vivi
> Cc: Dhinakaran Pandiyan
> Signed-off-by: José Roberto de Souza
> ---
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
v2: R
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_hdmi.c | 12 +---
2 files changed, 13 insertions(
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions
supported.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 4 ++--
include/linux/hdmi.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/
From: Ville Syrjälä
This is to limit PORT C on GLK to drive only
HDMI. Not sure if this is mandatory, this is just
to test HDR on GLK HDMI.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_bios.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/
HDR source metadata set and get property implemented in this
patch. The blob data is received from userspace and saved in
connector state, the same is returned as blob in get property
call to userspace.
v2: Rebase and added Ville's POC changes
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic.c | 15 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 4
2 files changed, 18 insertions(+), 1 deletion(-)
di
From: Ville Syrjälä
Function argument for hdmi_drm_infoframe_log is made constant.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/video/hdmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 0937c8c
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 27 +
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 24
include/drm/drm_connector.h | 2 ++
2 files changed, 26 insertions(+)
diff --git
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 45 +
1 file changed, 45 insertion
Hardware may have HDR capability on certain plane
engines. Enabling the same in drm plane structure
so that this can be communicated to user space.
Each drm driver should set this flag to true for planes
which support HDR.
v2: Rebase
Signed-off-by: Uma Shankar
---
include/drm/drm_plane.h | 3 +
Add bit field and macro for extended tag in CEA block. Also,
declare macros for HDR metadata block.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
v2: Rebase and modified the metadata structure elements
as per Ville's POC changes.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_connector.c | 6 ++
in
Attach HDR metadata property to connector object.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 07e803a..8a1e5cb 100644
--- a/drivers/
This patch series enables HDR support in drm. It basically defines
HDR metadata structures, property to pass content (after blending)
metadata from user space compositors to driver.
Dynamic Range and Mastering infoframe creation and sending.
ToDo:
1. We need to get the color framework in place fo
On Mon, 2018-11-12 at 11:17 +0100, Maarten Lankhorst wrote:
> Op 09-11-18 om 21:20 schreef José Roberto de Souza:
> > If panel supports DRRS and PSR and if driver is loaded without PSR
> > enabled, driver will enable DRRS as expected but if PSR is enabled
> > by
> > debugfs latter it will keep PSR
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev4)
URL : https://patchwork.freedesktop.org/series/53340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11072
S
== Series Details ==
Series: Add Colorspace connector property interface (rev5)
URL : https://patchwork.freedesktop.org/series/47132/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11068_full
Summary
-
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev4)
URL : https://patchwork.freedesktop.org/series/53340/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cc1e8bb822a1 drm/i915/icl: combo port vswing programming changes per BSPEC
-:256
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence. Restrict combo phy to
HBR max rate unless eDP panel is connected to port.
v2: remove debug code that Imre found
v3: simplify translation table if-else
v4: e
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method
URL : https://patchwork.freedesktop.org/series/53901/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11067_full
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev2)
URL : https://patchwork.freedesktop.org/series/25091/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/in
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_hdmi.c | 12 +---
2 files changed, 13 insertions(
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions
supported.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 4 ++--
include/linux/hdmi.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic.c | 15 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 4
2 files changed, 18 insertions(+), 1 deletion(-)
di
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
v2: R
From: Ville Syrjälä
This is to limit PORT C on GLK to drive only
HDMI. Not sure if this is mandatory, this is just
to test HDR on GLK HDMI.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_bios.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/
From: Ville Syrjälä
Function argument for hdmi_drm_infoframe_log is made constant.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/video/hdmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 0937c8c
HDR source metadata set and get property implemented in this
patch. The blob data is received from userspace and saved in
connector state, the same is returned as blob in get property
call to userspace.
v2: Rebase and added Ville's POC changes
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 27 +++
1 file ch
Hardware may have HDR capability on certain plane
engines. Enabling the same in drm plane structure
so that this can be communicated to user space.
Each drm driver should set this flag to true for planes
which support HDR.
v2: Rebase
Signed-off-by: Uma Shankar
---
include/drm/drm_plane.h | 3 +
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 24
include/drm/drm_connector.h | 2 ++
2 files changed, 26 insertions(+)
diff --git
Add bit field and macro for extended tag in CEA block. Also,
declare macros for HDR metadata block.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
Attach HDR metadata property to connector object.
v2: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 07e803a..8a1e5cb 100644
--- a/drivers/
This patch series enables HDR support in drm. It basically defines
HDR metadata structures, property to pass content (after blending)
metadata from user space compositors to driver.
Dynamic Range and Mastering infoframe creation and sending.
ToDo:
1. We need to get the color framework in place
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 45 +
1 file changed, 45 insertion
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
v2: Rebase and modified the metadata structure elements
as per Ville's POC changes.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_connector.c | 6 ++
in
== Series Details ==
Series: drm/i915: DFSM pipe disable is valid from gen9 onwards (rev2)
URL : https://patchwork.freedesktop.org/series/53900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11070
Summary
== Series Details ==
Series: drm/i915: DFSM pipe disable is valid from gen9 onwards
URL : https://patchwork.freedesktop.org/series/53900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11066_full
Summa
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method (rev2)
URL : https://patchwork.freedesktop.org/series/53901/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11069
===
It's not just GEN9 platforms that allow for pipes to be disabled via
the DFSM register, but all later platforms as well.
v2: drop pointless parentheses (Ville)
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method (rev2)
URL : https://patchwork.freedesktop.org/series/53901/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Don
The DDB allocation algorithm currently used by the driver grants each
plane a very small minimum allocation of DDB blocks and then divies up
all of the remaining blocks based on the percentage of the total data
rate that the plane makes up. It turns out that this proportional
allocation approach i
On Tue, 2018-12-11 at 10:32 -0800, Dhinakaran Pandiyan wrote:
> On Tue, 2018-12-11 at 04:44 -0800, Souza, Jose wrote:
> > On Mon, 2018-12-10 at 22:51 -0800, Dhinakaran Pandiyan wrote:
> > > On Tue, 2018-12-04 at 15:00 -0800, José Roberto de Souza wrote:
> > > > The old debugfs fields was not follow
== Series Details ==
Series: Add Colorspace connector property interface (rev5)
URL : https://patchwork.freedesktop.org/series/47132/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11068
Summary
---
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method
URL : https://patchwork.freedesktop.org/series/53898/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11065_full
== Series Details ==
Series: Add Colorspace connector property interface (rev5)
URL : https://patchwork.freedesktop.org/series/47132/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm: Add colorspace connector property
Okay!
Commit: drm/i915: Attach
On Tue, 2018-12-11 at 04:44 -0800, Souza, Jose wrote:
> On Mon, 2018-12-10 at 22:51 -0800, Dhinakaran Pandiyan wrote:
> > On Tue, 2018-12-04 at 15:00 -0800, José Roberto de Souza wrote:
> > > The old debugfs fields was not following a naming partern and it
> > > was
> > > a bit confusing.
> > >
>
== Series Details ==
Series: Add Colorspace connector property interface (rev5)
URL : https://patchwork.freedesktop.org/series/47132/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
63b9d3d2f8f9 drm: Add colorspace connector property
48917be04d31 drm/i915: Attach colorspace prope
On Tue, 2018-12-04 at 13:23 -0800, Dhinakaran Pandiyan wrote:
> On Tue, 2018-12-04 at 10:52 -0800, Souza, Jose wrote:
> > On Mon, 2018-12-03 at 18:58 -0800, Dhinakaran Pandiyan wrote:
> > > On Mon, 2018-12-03 at 17:54 -0800, Souza, Jose wrote:
> > > > On Mon, 2018-12-03 at 17:33 -0800, Dhinakaran P
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method
URL : https://patchwork.freedesktop.org/series/53901/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11067
==
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method
URL : https://patchwork.freedesktop.org/series/53901/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Don't use
== Series Details ==
Series: drm/i915: DFSM pipe disable is valid from gen9 onwards
URL : https://patchwork.freedesktop.org/series/53900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11066
Summary
---
This patch attaches the colorspace connector property to the
hdmi connector. Based on colorspace change, modeset will be
triggered to switch to new colorspace.
Based on colorspace property value create an infoframe
with appropriate colorspace. This can be used to send an
infoframe packet with prop
This patch series creates a new connector property to program
colorspace to sink devices. Modern sink devices support more
than 1 type of colorspace like 601, 709, BT2020 etc. This helps
to switch based on content type which is to be displayed. The
decision lies with compositors as to in which scen
This patch adds a colorspace connector property, enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
the colorspace enum to incorporate both HDMI and DP supported
color
On Tue, Dec 11, 2018 at 09:30:43AM -0800, Bob Paauwe wrote:
> It's not just GEN9 platforms that allow for pipes to be disabled via
> the DFSM register, but all later platforms as well.
>
> Signed-off-by: Bob Paauwe
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> 1 file changed, 1 inse
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method
URL : https://patchwork.freedesktop.org/series/53898/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11065
==
The bspec gives an if/else chain for choosing whether to use "method 1"
or "method 2" for calculating the watermark "Selected Result Blocks"
value for a plane. One of the branches of the if chain is:
"Else If ('plane buffer allocation' is known and (plane buffer
allocation / plane
The DDB allocation algorithm currently used by the driver grants each
plane a very small minimum allocation of DDB blocks and then divies up
all of the remaining blocks based on the percentage of the total data
rate that the plane makes up. It turns out that this proportional
allocation approach i
It's not just GEN9 platforms that allow for pipes to be disabled via
the DFSM register, but all later platforms as well.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_in
On Tue, Dec 11, 2018 at 09:03:46AM -0800, Matt Roper wrote:
> The DDB allocation algorithm currently used by the driver grants each
> plane a very small minimum allocation of DDB blocks and then divies up
> all of the remaining blocks based on the percentage of the total data
> rate that the plane
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Don't use DDB allocation when
choosing gen9 watermark method
URL : https://patchwork.freedesktop.org/series/53898/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Don't use
The bspec gives an if/else chain for choosing whether to use "method 1"
or "method 2" for calculating the watermark "Selected Result Blocks"
value for a plane. One of the branches of the if chain is:
"Else If ('plane buffer allocation' is known and (plane buffer
allocation / plane
The DDB allocation algorithm currently used by the driver grants each
plane a very small minimum allocation of DDB blocks and then divies up
all of the remaining blocks based on the percentage of the total data
rate that the plane makes up. It turns out that this proportional
allocation approach i
On Tue, Dec 11, 2018 at 06:21:29PM +0200, Ville Syrjälä wrote:
> On Tue, Dec 11, 2018 at 08:11:16AM -0800, Matt Roper wrote:
> > On Tue, Dec 11, 2018 at 05:59:56PM +0200, Ville Syrjälä wrote:
> > > On Mon, Dec 10, 2018 at 05:05:43PM -0800, Matt Roper wrote:
> > ...snip...
> > > >
> > > > -
On Tue, Dec 11, 2018 at 08:11:16AM -0800, Matt Roper wrote:
> On Tue, Dec 11, 2018 at 05:59:56PM +0200, Ville Syrjälä wrote:
> > On Mon, Dec 10, 2018 at 05:05:43PM -0800, Matt Roper wrote:
> ...snip...
> > >
> > > - alloc_size -= total_min_blocks;
> > > - cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].
On Tue, Dec 11, 2018 at 05:59:56PM +0200, Ville Syrjälä wrote:
> On Mon, Dec 10, 2018 at 05:05:43PM -0800, Matt Roper wrote:
...snip...
> >
> > - alloc_size -= total_min_blocks;
> > - cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start = alloc->end -
> > minimum[PLANE_CURSOR];
> > - cstate->wm.
On Mon, Dec 10, 2018 at 05:05:43PM -0800, Matt Roper wrote:
> The DDB allocation algorithm currently used by the driver grants each
> plane a very small minimum allocation of DDB blocks and then divies up
> all of the remaining blocks based on the percentage of the total data
> rate that the plane
On Tue, Dec 11, 2018 at 10:53 AM Sean Paul wrote:
>
> On Mon, Dec 10, 2018 at 10:58:20AM -0500, Alex Deucher wrote:
> > On Mon, Dec 10, 2018 at 5:04 AM Daniel Vetter
> > wrote:
> > >
> > > It's not a core function, and the matching atomic functions are also
> > > not in the core. Plus the suspen
On Mon, Dec 10, 2018 at 10:58:20AM -0500, Alex Deucher wrote:
> On Mon, Dec 10, 2018 at 5:04 AM Daniel Vetter wrote:
> >
> > It's not a core function, and the matching atomic functions are also
> > not in the core. Plus the suspend/resume helper is also already there.
> >
> > Needs a tiny bit of o
Hi,
Can these changes be merged from branch BXT_HUC to linux_fir,ware.git?
Anusha
From: Srivatsa, Anusha
Sent: Friday, December 7, 2018 2:14 PM
To: jwbo...@kernel.org; k...@kernel.org; b...@decadent.org.uk
Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo
Subject: linux-firmware PR for BXT HUC
On Wed, 05 Dec 2018, Lucas De Marchi wrote:
> Instead of using IS_GEN() for consecutive gen checks, let's pass the
> range to IS_GEN_RANGE(). By code inspection these were the ranges deemed
> necessary for spatch:
>
> @@
> expression e;
> @@
> (
> - IS_GEN(e, 3) || IS_GEN(e, 2)
> + IS_GEN_RANGE(e,
On Wed, 05 Dec 2018, Lucas De Marchi wrote:
> Define IS_GEN() similarly to our IS_GEN_RANGE(). but use gen instead of
> gen_mask to do the comparison. Now callers can pass then gen as a parameter,
> so we don't require one macro for each gen.
>
> The following spatch was used to convert the users
On Mon, Dec 10, 2018 at 02:52:54PM -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests
> HF1-12 and HF1-13 to fail.
>
> V2: Removed "Source Shall" entries to a new patch
> V3: Rebase to drm-tip
> Cc: Ville S
On Tue, Dec 11, 2018 at 04:18:47PM +0200, Ville Syrjälä wrote:
> On Tue, Dec 11, 2018 at 11:40:43AM +0200, Imre Deak wrote:
> > On Wed, Dec 05, 2018 at 06:32:22PM +0200, Imre Deak wrote:
> > > On Tue, Dec 04, 2018 at 03:41:09PM -0800, clinton.a.tay...@intel.com
> > > wrote:
> > > > From: Clint Tay
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