== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Assign genlock CRTC pointer in
all slave CRTC states for tiled displays
URL : https://patchwork.freedesktop.org/series/58393/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5792 -> Patchwork_12567
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Assign genlock CRTC pointer in
all slave CRTC states for tiled displays
URL : https://patchwork.freedesktop.org/series/58393/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d15c48b8741b drm/i915/icl: Assign
== Series Details ==
Series: HDCP2.2 Phase II (rev4)
URL : https://patchwork.freedesktop.org/series/57232/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5792 -> Patchwork_12566
Summary
---
**SUCCESS**
No
== Series Details ==
Series: series starting with [1/3] drm/i915: Split Pineview device info into
desktop and mobile (rev2)
URL : https://patchwork.freedesktop.org/series/58123/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5787_full -> Patchwork_12547_full
== Series Details ==
Series: HDCP2.2 Phase II (rev4)
URL : https://patchwork.freedesktop.org/series/57232/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: debugfs: HDCP2.2 capability read
Okay!
Commit: drm: Add Content protection type
== Series Details ==
Series: HDCP2.2 Phase II (rev4)
URL : https://patchwork.freedesktop.org/series/57232/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e5c335d05858 drm/i915: debugfs: HDCP2.2 capability read
42027b987c97 drm: Add Content protection type property
-:60:
== Series Details ==
Series: drm/i915: Add not fenceable reason to not enable FBC
URL : https://patchwork.freedesktop.org/series/58390/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5792 -> Patchwork_12565
Summary
---
:
https://github.com/0day-ci/linux/commits/Bob-Paauwe/drm-i915-ehl-All-EHL-ports-are-combo-phys-v2/20190321-145619
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x073-201911 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save
== Series Details ==
Series: drm/i915: stop storing the media fuse
URL : https://patchwork.freedesktop.org/series/58387/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791 -> Patchwork_12564
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: stop storing the media fuse
URL : https://patchwork.freedesktop.org/series/58387/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: stop storing the media fuse
== Series Details ==
Series: drm/i915: stop storing the media fuse
URL : https://patchwork.freedesktop.org/series/58387/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
de5dfcc93c76 drm/i915: stop storing the media fuse
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'first' -
== Series Details ==
Series: Do not re-read dpll registers
URL : https://patchwork.freedesktop.org/series/58382/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791 -> Patchwork_12562
Summary
---
**SUCCESS**
No
== Series Details ==
Series: series starting with drm/i915/ehl: Add EHL platform info and PCI IDs
(rev2)
URL : https://patchwork.freedesktop.org/series/58386/
State : failure
== Summary ==
Applying: drm/i915/ehl: Add EHL platform info and PCI IDs
Applying: drm/i915/ehl: Add ElkhartLake
In case of tiled displays where different tiles are displayed across
different ports, we need to synchronize the transcoders involved.
This patch implements the transcoder port sync feature for
synchronizing one master transcoder with one or more slave
transcoders. This is only enbaled in slave
In case of tiled displays when the two tiles are sent across two CRTCs
over two separate DP SST connectors, we need a mechanism to synchronize
the two CRTCs and their corresponding transcoders.
So use the master-slave mode where there is one master corresponding
to last horizontal and vertical
== Series Details ==
Series: Do not re-read dpll registers
URL : https://patchwork.freedesktop.org/series/58382/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b8b9a3a6bb07 drm/i915/skl: use previous pll hw readout
8b862f77d44e drm/i915/cnl: use previous pll hw readout
-:41:
== Series Details ==
Series: drm/i915: set vdbox/vebox enable masks on all gens
URL : https://patchwork.freedesktop.org/series/58381/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791 -> Patchwork_12561
Summary
---
== Series Details ==
Series: drm/i915: Skip object locking around a no-op set-domain ioctl (rev4)
URL : https://patchwork.freedesktop.org/series/58325/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5787_full -> Patchwork_12546_full
== Series Details ==
Series: drm/i915/icl: Fix clockgating issue when using scalars (rev3)
URL : https://patchwork.freedesktop.org/series/58081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791 -> Patchwork_12560
Summary
== Series Details ==
Series: drm/i915: Pass intel_context to i915_request_create()
URL : https://patchwork.freedesktop.org/series/58380/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791 -> Patchwork_12559
Summary
---
After sent I notice that the commit descriptions feels strange to read,
maybe changing to "drm/i915: Add 'not fenceable' reason to not enable
FBC" makes it better, any tips?
On Thu, 2019-03-21 at 17:42 -0700, José Roberto de Souza wrote:
> There is some kms_frontbuffer_tracking failures due FBC
Attaches the content type property for HDCP2.2 capable connectors.
Implements the update of content type from property and apply the
restriction on HDCP version selection.
v2:
s/cp_content_type/content_protection_type [daniel]
disable at hdcp_atomic_check to avoid check at
Implements drm blob property content_protection_downstream_info
property on HDCP capable connectors.
Downstream topology info is gathered across authentication stages
and stored in intel_hdcp. When HDCP authentication is complete,
new blob with latest downstream topology information is updated to
This patch adds a optional CP downstream info blob property to the
connectors. This enables the Userspace to read the information of HDCP
authenticated downstream topology.
Driver will updated this blob with all downstream information at the
end of the authentication.
In case userspace
Adding the HDCP2.2 capability of HDCP src and sink info into debugfs
entry "i915_hdcp_sink_capability"
This helps the userspace tests to skip the HDCP2.2 test on non HDCP2.2
sinks.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 +++--
Populates the downstream info for HDCP2.2 encryption also. On success
of encryption Blob is updated.
Additional two variable are added to downstream info blob. Such as
ver_in_force and content type.
v2:
s/cp_downstream/content_protection_downstream [daniel]
v3:
This patch adds a DRM ENUM property to the selected connectors.
This property is used for mentioning the protected content's type
from userspace to kernel HDCP authentication.
Type of the stream is decided by the protected content providers.
Type 0 content can be rendered on any HDCP protected
DRM API for generating uevent for a status changes of connector's
property.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/drm_sysfs.c | 28
include/drm/drm_sysfs.h | 5 -
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git
Invoking the uevent generator for the content protection property state
change of a connector. This helps the userspace to detect the new state
change without polling the property val.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 11 +++
1 file changed, 11
Implements the SRM table parsing for HDCP 1.4 and 2.2.
And also revocation check is added at authentication of HDCP1.4
and 2.2
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/intel_drv.h | 2 +
There is some kms_frontbuffer_tracking failures due FBC being
disabled with the reason "framebuffer not tiled or fenced".
Although the test is setting up everything correctly to have
FBC enabled sporadically it is failing, due the alignment and size
restrictions in
Binary Sysfs entry is created to pass the HDCP SRM table into
kerel for the HDCP authentication purpose.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_sysfs.c | 32 +++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
HDCP2.2 phase-II introduces below features:
Addition of three connector properties
HDCP Content Type
HDCP Topology
Addition of binary sysfs "hdcp_srm"
parsing for HDCP1.4 and 2.2 SRM table
Once HDCP1.4/2.2 authentication is completed
== Series Details ==
Series: drm/i915/guc: GuC suspend path cleanup (rev2)
URL : https://patchwork.freedesktop.org/series/58370/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791 -> Patchwork_12558
Summary
---
== Series Details ==
Series: drm/i915/selftests: fix NULL vs IS_ERR() check in
mock_context_barrier() (rev2)
URL : https://patchwork.freedesktop.org/series/58337/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5787_full -> Patchwork_12545_full
We're already updating the engine_mask to reflect what's in the HW, so
we can just get the info from there. A couple of macros have been added
to facilitate this.
Suggested-by: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
---
Hi Stephen,
On Fri, Mar 22, 2019 at 10:57:28AM +1100, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the drm-intel tree got a conflict in:
>
> drivers/gpu/drm/i915/gvt/mmio_context.c
>
> between commit:
>
> 1e8b15a1988e ("drm/i915/gvt: Add in context mmio 0x20D8 to gen9
From: James Ausmus
Add known EHL PCI IDs.
v2 (Rodrigo): Removed x86 early quirk. To be sent in a separated
patch cc'ing the appropriated list and maintainers for
proper ack.
v3: (Rodrigo): - Removed .num_pipes = 3 that is coming since GEN&_FEATURES.
-
From: James Ausmus
Add known EHL PCI IDs.
v2 (Rodrigo): Removed x86 early quirk. To be sent in a separated
patch cc'ing the appropriated list and maintainers for
proper ack.
v3: (Rodrigo): - Removed .num_pipes = 3 that is coming since GEN&_FEATURES.
-
From: Anusha Srivatsa
EHL uses the same firmware as ICL.
Cc: Bob Paauwe
Signed-off-by: Anusha Srivatsa
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: Bob Paauwe
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_csr.c | 2 +-
1 file changed, 1
From: Bob Paauwe
EHL has a different number of subslices.
Cc: Lucas De Marchi
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_device_info.c | 12 +---
1 file changed, 9
From: Bob Paauwe
Add ElkhartLake as a unique platform as there are some differences
between it and Icelake.
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
From: Bob Paauwe
Configure the correct set of outputs for EHL. EHL has three DDI's
plus MIPI.
Cc: Lucas De Marchi
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
Reviewed-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_display.c | 7 ++-
1
From: Lucas De Marchi
Elkhart Lake has a different set of PLLs as compared to Ice Lake,
although programming them is very similar.
v2: Rebase on top of s/icl_pll_funcs/combo_pll_funcs
Signed-off-by: Lucas De Marchi
Signed-off-by: Rodrigo Vivi
Reviewed-by: José Roberto de Souza
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/gvt/mmio_context.c
between commit:
1e8b15a1988e ("drm/i915/gvt: Add in context mmio 0x20D8 to gen9 mmio list")
from the drm-intel-fixes tree and commit:
8a68d464366e ("drm/i915: Store the
== Series Details ==
Series: series starting with [1/2] drm/i915: Add missing scanline case for 8
cpp watermarks.
URL : https://patchwork.freedesktop.org/series/58342/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5787_full -> Patchwork_12544_full
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/selftests: Calculate maximum
ring size for preemption chain
URL : https://patchwork.freedesktop.org/series/58376/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791 -> Patchwork_12557
On 3/20/19 6:54 AM, Imre Deak wrote:
From: Ville Syrjälä
If we have only a single active pipe and the cdclk change only requires
the cd2x divider to be updated bxt+ can do the update with forcing a full
modeset on the pipe. Try to hook that up.
v2:
- Wait for vblank after an optimized CDCLK
On 3/21/19 3:39 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-03-21 22:14:20)
On 3/21/19 3:11 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-03-21 22:02:06)
The upcoming unified GuC FW will require us to send video engine enable
masks to GuC for its
Quoting Daniele Ceraolo Spurio (2019-03-21 22:14:20)
>
>
> On 3/21/19 3:11 PM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2019-03-21 22:02:06)
> >> The upcoming unified GuC FW will require us to send video engine enable
> >> masks to GuC for its initialization.
> >>
> >> For
== Series Details ==
Series: series starting with [1/8] drm/i915/psr: Remove partial PSR support on
multiple transcoders
URL : https://patchwork.freedesktop.org/series/58373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791 -> Patchwork_12556
On 3/20/19 6:54 AM, Imre Deak wrote:
From: Ville Syrjälä
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use atomic refcount for get_power, put_power so that we can
call
On 3/21/19 3:11 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-03-21 22:02:06)
The upcoming unified GuC FW will require us to send video engine enable
masks to GuC for its initialization.
For consistency, just set the runtime_info enable masks for all gens.
We'll then be able
Quoting Daniele Ceraolo Spurio (2019-03-21 22:02:06)
> The upcoming unified GuC FW will require us to send video engine enable
> masks to GuC for its initialization.
>
> For consistency, just set the runtime_info enable masks for all gens.
> We'll then be able to directly use those in the GuC
Quoting Daniele Ceraolo Spurio (2019-03-21 22:02:06)
> The upcoming unified GuC FW will require us to send video engine enable
> masks to GuC for its initialization.
>
> For consistency, just set the runtime_info enable masks for all gens.
> We'll then be able to directly use those in the GuC
This should be sent to igt-...@lists.freedesktop.org
On Thu, 2019-03-21 at 11:02 -0700, Anusha wrote:
> From: Anusha Srivatsa
>
> Add CML IDS and additional CNL ID.
>
> v2: Copy header from kernel (Jose)
> - Change commit message (Lucas)
>
> Cc: José Roberto de Souza
> Cc: Lucas De Marchi
>
On Tue, Mar 19, 2019 at 02:00:18PM +0530, Uma Shankar wrote:
> Added support for ICL platform multi segment gamma
> capabilties and attached the property, exposing the
> same to userspace.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_color.c | 22 +-
> 1
This should be sent to dri-de...@lists.freedesktop.org
On Thu, 2019-03-21 at 10:58 -0700, Anusha wrote:
> Straight copy from the kernel file.
>
> Add PCI IDs for CML, add additional PCI ID
> for CNL.
>
> v2: Do a copy from kernel header (Jose)
> - Change commit message (Lucas)
>
> Cc: José
By the time icl_ddi_clock_get() is called we've just got the hw state
from the pll registers. We don't need to read them again: we can rather
reuse what was cached in the dpll_hw_state.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_ddi.c | 39 +++-
1
Instead of re-reading the registers we just read on the hw state
readout, use the values saved on intel_shared_dpll. Besides not doing
the MMIO, this helps on sharing code since we don't have to
differentiate e.g. ICL and CNL because they have different registers for
the same thing.
I'm a little
By the time cnl_ddi_clock_get() is called we've just got the hw state
from the pll registers. We don't need to read them again: we can rather
reuse what was cached in the dpll_hw_state.
This also affects the code for ICL since it partially reuses the CNL
code. However the more intricate part on
By the time skl_ddi_clock_get() is called - and thus
skl_calc_wrpll_link() - we've just got the hw state from the pll
registers. We don't need to read them again: we can rather reuse what
was cached in the dpll_hw_state.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_ddi.c | 49
The upcoming unified GuC FW will require us to send video engine enable
masks to GuC for its initialization.
For consistency, just set the runtime_info enable masks for all gens.
We'll then be able to directly use those in the GuC setup
Cc: Michal Wajdeczko
Cc: John Spotswood
Cc: Eric
== Series Details ==
Series: series starting with [1/8] drm/i915/psr: Remove partial PSR support on
multiple transcoders
URL : https://patchwork.freedesktop.org/series/58373/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/psr: Remove partial
== Series Details ==
Series: series starting with [1/8] drm/i915/psr: Remove partial PSR support on
multiple transcoders
URL : https://patchwork.freedesktop.org/series/58373/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
95c7ad172d42 drm/i915/psr: Remove partial PSR support
On Wed, Mar 20, 2019 at 10:03:16AM -0700, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Syrjala, Ville
> >Sent: Tuesday, March 19, 2019 10:29 PM
> >To: Lankhorst, Maarten
> >Cc: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
> >Sharma, Shashank ; Roper, Matthew D
> >
>
== Series Details ==
Series: drm/i915: Really calculate the cursor ddb based on the highest enabled
wm level
URL : https://patchwork.freedesktop.org/series/58372/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5791 -> Patchwork_12555
Fixes the clock-gating issue when pipe scaling is enabled.
(Lineage #2006604312)
V2: Fix typo in headline(Chris)
Handle the non double buffered nature of the register(Ville)
V3: Fix checkpatch warning. BAT failure for V2 on gen3 looks unrelated.
Cc: Chris Wilson
Cc: Ville Syrjala
Cc:
Start acquiring the logical intel_context and using that as our primary
means for request allocation. This is the initial step to allow us to
avoid requiring struct_mutex for request allocation along the
perma-pinned kernel context, but it also provides a foundation for
breaking up the complex
On Tue, Mar 19, 2019 at 02:00:12PM +0530, Uma Shankar wrote:
> Gen platforms support multiple gamma modes, currently
> it's hard coded to operate only in 1 specific mode.
> This patch adds a property to make gamma mode programmable.
> User can select which mode should be used for a particular
>
On 21/03/19 11:02, Anusha wrote:
From: Anusha Srivatsa
Add CML IDS and additional CNL ID.
Please add the kernel commits to be consistent with the previous updates.
Acked-by: Antonio Argenziano
v2: Copy header from kernel (Jose)
- Change commit message (Lucas)
Cc: José Roberto de
Adding a call to intel_uc_suspend in i915_gem_suspend, which
is a common point for the suspend/resume and hibernate paths.
This fixes an unbalanced call that causes issues with the CTB
register/deregister.
v2: Making the call unconditional (Daniele)
Moving the call to after the GEM_BUG_ON
On 3/21/19 1:23 PM, Chris Wilson wrote:
Quoting Sujaritha (2019-03-21 20:02:36)
On 3/21/19 1:08 PM, Chris Wilson wrote:
Quoting Sujaritha (2019-03-21 19:41:17)
On 3/21/19 12:37 PM, Chris Wilson wrote:
Quoting Patchwork (2019-03-21 19:26:27)
== Series Details ==
Series: drm/i915/guc: GuC
Quoting Sujaritha (2019-03-21 20:02:36)
>
> On 3/21/19 1:08 PM, Chris Wilson wrote:
> > Quoting Sujaritha (2019-03-21 19:41:17)
> >> On 3/21/19 12:37 PM, Chris Wilson wrote:
> >>> Quoting Patchwork (2019-03-21 19:26:27)
> == Series Details ==
>
> Series: drm/i915/guc: GuC suspend
On 3/21/19 1:08 PM, Chris Wilson wrote:
Quoting Sujaritha (2019-03-21 19:41:17)
On 3/21/19 12:37 PM, Chris Wilson wrote:
Quoting Patchwork (2019-03-21 19:26:27)
== Series Details ==
Series: drm/i915/guc: GuC suspend path cleanup
URL : https://patchwork.freedesktop.org/series/58370/
State
On Thu, Mar 21, 2019 at 07:51:28PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> I added the loop but neglected to actually pass the level to the
> function. So we were just looping 8 times calculating the exact
> same thing every time.
>
> Fixes: df331de3f8aa ("drm/i915: Allocate
== Series Details ==
Series: series starting with [v1,1/1] drm/i915/sleftests: live_execlists
subtest faster
URL : https://patchwork.freedesktop.org/series/58371/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5789 -> Patchwork_12554
Quoting Sujaritha (2019-03-21 19:41:17)
>
> On 3/21/19 12:37 PM, Chris Wilson wrote:
> > Quoting Patchwork (2019-03-21 19:26:27)
> >> == Series Details ==
> >>
> >> Series: drm/i915/guc: GuC suspend path cleanup
> >> URL : https://patchwork.freedesktop.org/series/58370/
> >> State : failure
>
On 3/21/19 10:54 AM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-03-21 17:49:55)
On 3/21/19 10:14 AM, Sujaritha Sundaresan wrote:
Adding a call to intel_uc_suspend in i915_gem_suspend, which
is a common point for the suspend/resume and hibernate paths.
This fixes an unbalanced
On Thu, Mar 21, 2019 at 11:50:18AM +0800, Zhenyu Wang wrote:
>
> Hi,
>
> Sorry that I might miss 5.1-rc1 window as I was in full day event
> during this week.
hmm... my bad. I should had remembered that you had stuff queued for
-fixes that we didn't put in -next-fixes
I'm sorry.
> Here's
On 3/21/19 12:37 PM, Chris Wilson wrote:
Quoting Patchwork (2019-03-21 19:26:27)
== Series Details ==
Series: drm/i915/guc: GuC suspend path cleanup
URL : https://patchwork.freedesktop.org/series/58370/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5789 -> Patchwork_12553
Use the igt_live_test framework for detecting whether an unwanted hang
occurred during test execution, and report failure if it does.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/selftests/intel_lrc.c | 38 --
1 file changed, 35
32 is too many for the likes of kbl, and in order to insert that many
requests into the ring requires us to declare the first few hung --
understandably a slow and unexpected process. Instead, measure the size
of a singe requests and use that to estimate the upper bound on the
chain length we can
== Series Details ==
Series: series starting with [v1,1/1] drm/i915/sleftests: live_execlists
subtest faster
URL : https://patchwork.freedesktop.org/series/58371/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
317b9648fbbb drm/i915/sleftests: live_execlists subtest faster
Quoting Patchwork (2019-03-21 19:26:27)
> == Series Details ==
>
> Series: drm/i915/guc: GuC suspend path cleanup
> URL : https://patchwork.freedesktop.org/series/58370/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5789 -> Patchwork_12553
>
== Series Details ==
Series: drm/i915/guc: GuC suspend path cleanup
URL : https://patchwork.freedesktop.org/series/58370/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5789 -> Patchwork_12553
Summary
---
**FAILURE**
== Series Details ==
Series: lib: sync with the newer i915_pciids.h from the Kernel
URL : https://patchwork.freedesktop.org/series/58375/
State : success
== Summary ==
CI Bug Log - changes from IGT_4897 -> IGTPW_2686
Summary
---
Quoting Chris Wilson (2019-03-21 18:38:53)
> Quoting Caz Yokoyama (2019-03-21 18:41:10)
> > inline
> > -caz
> > On Thu, 2019-03-21 at 07:37 +, Chris Wilson wrote:
> > > +
> > > + rq = i915_request_alloc(engine, lo.ctx);
> > > + if (IS_ERR(rq))
> > > +
Reviewed-by: Yokoyama, Caz
-caz
On Thu, 2019-03-21 at 18:42 +, Chris Wilson wrote:
> Quoting Chris Wilson (2019-03-21 18:38:53)
> > Quoting Caz Yokoyama (2019-03-21 18:41:10)
> > > inline
> > > -caz
> > > On Thu, 2019-03-21 at 07:37 +, Chris Wilson wrote:
> > > > 32 is too many for the
Quoting Chris Wilson (2019-03-21 18:38:53)
> Quoting Caz Yokoyama (2019-03-21 18:41:10)
> > inline
> > -caz
> > On Thu, 2019-03-21 at 07:37 +, Chris Wilson wrote:
> > > 32 is too many for the likes of kbl, and in order to insert that many
> > Not only kbl. ring_size is 25 on my cfl.
> >
> > >
Quoting Caz Yokoyama (2019-03-21 18:41:10)
> inline
> -caz
> On Thu, 2019-03-21 at 07:37 +, Chris Wilson wrote:
> > 32 is too many for the likes of kbl, and in order to insert that many
> Not only kbl. ring_size is 25 on my cfl.
>
> > requests into the ring requires us to declare the first
inline
-caz
On Thu, 2019-03-21 at 07:37 +, Chris Wilson wrote:
> 32 is too many for the likes of kbl, and in order to insert that many
Not only kbl. ring_size is 25 on my cfl.
> requests into the ring requires us to declare the first few hung --
The hung is not caused by 32. It is caused by
== Series Details ==
Series: series starting with [1/2] drm/i915: Flush pages on acquisition
URL : https://patchwork.freedesktop.org/series/58367/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5789 -> Patchwork_12552
On Thu, Mar 21, 2019 at 11:01:36AM -0700, José Roberto de Souza wrote:
> PSR is only support in eDP transcoder and there is only one instance
> of it, so lets drop all of this code.
One instance? Are you talking about PSR2?
Also the EDP transcoder is already doomed is it not?
>
> Cc:
From: Anusha Srivatsa
Add CML IDS and additional CNL ID.
v2: Copy header from kernel (Jose)
- Change commit message (Lucas)
Cc: José Roberto de Souza
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
lib/i915_pciids.h | 31 +--
1 file changed, 29
Straight copy from the kernel file.
Add PCI IDs for CML, add additional PCI ID
for CNL.
v2: Do a copy from kernel header (Jose)
- Change commit message (Lucas)
Cc: José Roberto de Souza
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
intel/i915_pciids.h | 31
Right now it have a mix of PSR registers that are relative to PSR
mmio base and other register with a hardcoded address, lets keep it
consistented and have it all relative to mmio base.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
From BDW+ most of the PSR registers is relative to eDP transcoder
offset just PSR_IMR/IIR that have a fixed address, so lets set
mmio_base with the transcoder offset and adjust all the others
macros to the registers.
Also removing BDW_EDP_PSR_BASE from GVT because it is not used as
the only PSR
Even when driver is reload and hits this scenario the PSR mutex
should be initialized, otherwise reading PSR debugfs status will
execute mutex_lock() over a mutex that was not initialized.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
Just moving it to reduce the tabs and avoid break code lines into
several lines.
No behavior changes intended here.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_irq.c | 63 +++--
1 file changed, 36 insertions(+), 27 deletions(-)
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