Currently input csc for YCbCR to RGB conversion handles only
BT601 and Bt709. Extending it to support BT2020 as well.
v2: Fixed the co-efficients for LR to FR conversion,
as suggested by Ville.
v3: Fixed Y Pre-offset in case of Full Range YCbCr as suggested
by Ville.
v4: Split the v2 and v3 chan
Fixed Y Pre-offset in case of Full Range YCbCr.
v2: Rebase
Reviewed-by: Ville Syrjälä
Suggested-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_sprite.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/
Input CSC Co-efficients for BT601 and BT709 YCbCR to RGB
conversion were slightly off. Fixed the same.
v2: Fixed the co-eficients as there was issue with reference
matrix, spotted by Ville.
v3: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_sprite.c | 24 ++---
This series adds support for BT2020 YCbCr to RGB conversion
using input CSC. This also fixes issues with BT601 and BT709
coefficients.
v2: Fixed Ville's review comments.
v3: Rebase.
v4: Rebase.
v5: Fix a rebase fumble.
Uma Shankar (3):
drm/i915/icl: Handle YCbCr to RGB conversion for BT2020
== Series Details ==
Series: series starting with drm/i915: Fix memleak in runtime wakeref tracking
(rev2)
URL : https://patchwork.freedesktop.org/series/62871/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6375 -> Patchwork_13457
=
Quoting Matthew Auld (2019-06-27 21:55:58)
> @@ -0,0 +1,107 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#ifndef __INTEL_MEMORY_REGION_H__
> +#define __INTEL_MEMORY_REGION_H__
> +
> +#include
> +#include
> +#include
> +
> +#include "i915_b
This series introduce to drm a way to determine if something else
except connection_status had changed during probing, which
can be used by other drivers as well. Another i915 specific part
uses this approach to determine if edid had changed without
changing the connection status and send a hotplug
Many drivers would benefit from using
drm helper to compare edid, rather
than bothering with own implementation.
v2: Added documentation for this function.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/drm_edid.c | 33 +
include/drm/drm_edid.h | 9 +
Added edid checking to dp and hdmi edid setting functions, which
are called from detect hooks. The result currently is propagated
to calling layer using drm_connector->change_counter(proposed by Daniel Vetter).
drm_helper_hpd_irq_event and intel_encoder_hotplug are currently both
responsible for ch
This counter will be used by drm_helper_probe_detect caller to determine
if something else had changed except connection status,
like for example edid. Hardware specific drivers are responsible
for updating this counter when some change is detected to notify
the drm part, which can trigger for exam
== Series Details ==
Series: Send a hotplug when edid changes (rev2)
URL : https://patchwork.freedesktop.org/series/62816/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4a0b026f1681 drm: Add helper to compare edids.
-:32: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be wr
Get rid of all instances of drm_crtc_state, and rename cstate to
crtc_state for more clarity.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/g
To prepare for a hw and uapi state split in intel_crtc_state, we need
to start replacing all internal usage of drm_crtc_state with intel_crtc_state.
This makes it easier to convert to split state later, and cleans up the code
slightly.
Maarten Lankhorst (6):
drm/i915: Pass intel_crtc_state to ne
Instead of passing along drm_crtc_state and drm_atomic_state, pass
along more intel_atomic_state and intel_crtc_state. This will
make the code more readable by not casting between drm state
and intel state all the time.
While at it, rename old_state to state, with the get_new/old helpers
there is
Instead of directly referencing drm_crtc_state, convert to
intel_ctc_state and use the base struct. This is useful when we're
making the split between uapi and hw state, and also makes the
code slightly more readable.
A lot of places also use cstate, instead of the more common crtc_state.
Clean th
In i915 we should use intel_crtc_state as much as possible, pass
intel_crtc_state to needs_modeset, before we clean up all other uses
of drm_crtc_state.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 68 ++--
1 file
Like the rest of the intel atomic functions we should pass along
intel_crtc_state, and dereference drm_crtc_state only through
intel_crtc_state->base
While at it, rename old/new_state to old/new_crtc_state. (Ville)
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm
Pass along the correct state as much as possible, instead of relying
on the drm state internally. This is required to rely on hw state
internally soon.
While at it, clean up intel_plane_atomic_check slightly, by using a
helper function to get the intel_crtc. (Ville)
Signed-off-by: Maarten Lankhor
== Series Details ==
Series: drm/i915: Use intel_crtc_state everywhere!
URL : https://patchwork.freedesktop.org/series/62920/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
86e398aa0e65 drm/i915: Pass intel_crtc_state to needs_modeset()
83682e1854bb drm/i915: Convert most of ato
== Series Details ==
Series: drm/i915: Use intel_crtc_state everywhere!
URL : https://patchwork.freedesktop.org/series/62920/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Pass intel_crtc_state to needs_modeset()
Okay!
Commit: drm/i915: Con
Quoting Matthew Auld (2019-06-27 21:55:57)
> +static void __i915_buddy_free(struct i915_buddy_mm *mm,
> + struct i915_buddy_block *block)
> +{
> + list_del_init(&block->link); /* We have ownership now */
That is an important observation. Even more important is tha
== Series Details ==
Series: drm/i915: Add icl mipi dsi properties (rev2)
URL : https://patchwork.freedesktop.org/series/62770/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6376 -> Patchwork_13458
Summary
---
**SUCC
== Series Details ==
Series: drm/i915: CTS fixes (rev6)
URL : https://patchwork.freedesktop.org/series/62437/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6373_full -> Patchwork_13451_full
Summary
---
**SUCCESS**
On Tue, Jun 25, 2019 at 10:54:21AM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> On TGL the special EDP transcoder is gone and it should be handled by
> transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
> distinction clear and update vdsc code path.
>
> Cc: Imre Dea
== Series Details ==
Series: drm/i915/tgl: Gen12 csb support
URL : https://patchwork.freedesktop.org/series/62890/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6376 -> Patchwork_13459
Summary
---
**SUCCESS**
No r
== Series Details ==
Series: Introduce memory region concept (including device local memory) (rev2)
URL : https://patchwork.freedesktop.org/series/56683/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6376 -> Patchwork_13460
== Series Details ==
Series: Set correct values for N in deep color mode
URL : https://patchwork.freedesktop.org/series/62894/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6376 -> Patchwork_13461
Summary
---
**SUCCE
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Use port clock to set correct N
value
URL : https://patchwork.freedesktop.org/series/62895/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6376 -> Patchwork_13462
=
A puzzle for you...
---
drivers/gpu/drm/i915/i915_buddy.c | 17 +-
drivers/gpu/drm/i915/selftests/i915_buddy.c | 230 +++-
2 files changed, 234 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_buddy.c
b/drivers/gpu/drm/i915/i915_buddy.c
index c0ac
== Series Details ==
Series: Enable Transcoder Port Sync feature for Tiled displays (rev4)
URL : https://patchwork.freedesktop.org/series/59837/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6377 -> Patchwork_13463
Summary
On 2019-06-28 at 11:24:52 +0300, Stanislav Lisovskiy wrote:
> Many drivers would benefit from using
> drm helper to compare edid, rather
> than bothering with own implementation.
>
> v2: Added documentation for this function.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/drm_ed
On 2019-06-28 at 11:24:53 +0300, Stanislav Lisovskiy wrote:
> This counter will be used by drm_helper_probe_detect caller to determine
> if something else had changed except connection status,
> like for example edid. Hardware specific drivers are responsible
> for updating this counter when some c
> > > +gem_eb_flags_to_engine(unsigned int flags)
> > > +{
> > > + const struct intel_execution_engine2 *e2;
> > > +
> > > + __for_each_static_engine(e2) {
> > > + if (e2->flags == flags)
> > > + return e2;
> > > + }
> > > +
> > > + return NULL;
> > > +}
> >
> > the amount
On 2019-06-28 at 11:24:54 +0300, Stanislav Lisovskiy wrote:
> Added edid checking to dp and hdmi edid setting functions, which
> are called from detect hooks. The result currently is propagated
> to calling layer using drm_connector->change_counter(proposed by Daniel
> Vetter).
> drm_helper_hpd_ir
== Series Details ==
Series: drm/i915/ehl: Add support for DPLL4 (v5) (rev4)
URL : https://patchwork.freedesktop.org/series/61684/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6377 -> Patchwork_13464
Summary
---
**S
On Fri, 2019-06-28 at 09:54 +0530, Ramalingam C wrote:
> On 2019-06-28 at 11:24:54 +0300, Stanislav Lisovskiy wrote:
> > Added edid checking to dp and hdmi edid setting functions, which
> > are called from detect hooks. The result currently is propagated
> > to calling layer using drm_connector->ch
On 2019-06-28 at 17:06:09 +0530, Lisovskiy, Stanislav wrote:
> On Fri, 2019-06-28 at 09:54 +0530, Ramalingam C wrote:
> > On 2019-06-28 at 11:24:54 +0300, Stanislav Lisovskiy wrote:
> > > Added edid checking to dp and hdmi edid setting functions, which
> > > are called from detect hooks. The result
CFL:C0+ changed the status of those registers which are now
blacklisted by default.
This is breaking a number of CTS tests on GL & Vulkan :
KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations
(GL)
dEQP-VK.query_pool.statistics_query.fragment_shader_invocatio
When a register is readonly there is not much we can tell about its
value (apart from its default value?). This can be covered by tests
exercising the value of the register from userspace.
For PS_INVOCATION_COUNT we've got the following piglit tests :
KHR-GL45.pipeline_statistics_query_tests_
The same tests failing on CFL+ platforms are also failing on ICL.
Documentation doesn't list the
WaAllowPMDepthAndInvocationCountAccessFromUMD workaround for ICL but
applying it fixes the same tests as CFL.
v2: Use only one whitelist entry (Lionel)
Signed-off-by: Lionel Landwerlin
Tested-by: An
Anuj tested the update to the ICL whitelist. We need a good soul to
either Rb/Ack the rest.
Thanks,
Lionel Landwerlin (3):
drm/i915: fix whitelist selftests with readonly registers
drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT
drm/i915/icl: whitelist PS_(DEPTH|INVOCATION)_COUNT
drivers/
== Series Details ==
Series: drm/i915: CTS fixes (rev7)
URL : https://patchwork.freedesktop.org/series/62437/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2d3e1d83dab1 drm/i915: fix whitelist selftests with readonly registers
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrap
Added POWER_DOMAIN_VIDEO power domain and added its helper stuff.
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well.
which can disallow DC5/6 in order to allow dc3co.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/dr
This patch adds following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
v2: Commit log typo fixing.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gup
This patch enables dc3co state in enable_dc module param
and adds dc3co enable mask to allowed_dc_mask and gen9_dc_mask.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_params.c | 3 ++-
drivers/gpu/d
This patch adds a new "DC3CO Off" power well and adds
its power domain which are inherits from "DC Off" power well.
These power domains will disallow DC3CO when any external
display are connected and at time of modeset and aux
programming.
This patch also changes "DC Off" power well to "DC5 Off" po
This patch check if it is only edp display connected and
crtc has psr2 capability, then it sets the prefer_dc3co flag to
true. It also enable DC3CO PSR2 transcoder early exitline event
in haswell_crtc_enable() function.
TODO: B. Specs says dc3co should be allow only in video playback
case, current
As per B.Spces DC5 and DC6 not allowed when DC3CO is enabled.
and DC3CO should be enabled only during VIDEO playback.
Which essentially means both can DC5 and DC3CO can not be
enabled at same time.
This patch makes DC3CO and DC5 mutual exclusive.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
C
Addressed few review comment provided by Imre on internal mailing
list.
This series requires Tigerlake platform enablement patches and
TGL PSR patches to be merged first, so few patches has commented
out original code, which has commented out in order to build the
series.
DC3CO DMC f/w entry/ex
This patch exposes DC3CO counter in i915_dmc_info debugfs.
Which will be useful for DC3CO validation.
DMC firmware is using DMC_DEBUG3 register as DC3CO counter.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i
DC5 and DC6 not allowed when DC3CO feature is enabled.
DC5 and DC6 saves more power, but cannot be entered during video
playback because there are not enough idle frames in a row to meet.
Most PSR2 panel deep sleep entry requirements typically 4 frames.
This patch switch to DC3CO when there is an
This patch adds dc3co helper function to enable/disable
psr2 deep sleep.
This patch make sure DC3CO disallowed before PSR2 exit,
it does that essentially by putting a reference to
POWER_DOMAIN_VIDEO before PSR2 exit.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: jose.so...@intel.com
Cc: an
TGL onwards we have new DC5 and DC6 counter
DMC_DEBUG1 and DMC_DEBUG2 these counter will retain
there values upon DMC reset.
Currently using IS_GEN() macro instead of IS_TIGERLAKE()
to avoid compilation error and flot the pacthes.
Will be using IS_TIGERLAKE() once TGL platform
enabling pacthes merg
== Series Details ==
Series: drm/i915: use wildcard to ensure all headers stay self-contained
URL : https://patchwork.freedesktop.org/series/62840/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6375_full -> Patchwork_13452_full
=
== Series Details ==
Series: series starting with [1/8] drm/i915/selftests: Lock the drm_mm while
modifying
URL : https://patchwork.freedesktop.org/series/62851/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6375_full -> Patchwork_13455_full
==
This is v3 of [1] addressing the comments from Ville and adding the R-b
lines everywhere.
[1] https://patchwork.freedesktop.org/series/61590/#rev3
Cc: Manasi Navare
Cc: José Roberto de Souza
Cc: Rodrigo Vivi
Cc: Animesh Manna
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: Daniel Vetter
Cc: Lucas D
Add support to read out the TBT PLL HW state.
Cc: Vandita Kulkarni
Cc: Paulo Zanoni
Cc: Lucas De Marchi
Signed-off-by: Imre Deak
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a
The HW completion flag for the TBT AUX power well enabling/disabling
gets stuck if the firmware tears down the TBT DP tunnel before the
completion.
We shouldn't complain about the timeout, since it's expected to happen
and doesn't cause further issues. We suppress the disabling timeout
already, do
Move the TypeC port handling functions to a new file for clarity.
While at it:
- s/icl_tc_port_connected()/intel_tc_port_connected()/
icl_tc_phy_disconnect(), will be unexported later.
- s/intel_dp_get_fia_supported_lane_count()/
intel_tc_port_fia_max_lane_count()/
It's used for HDMI lega
Fix the mapping from a TBT AUX power well index to the DP_AUX_CH_CTL
register.
Fixes: c7375d9542f1 ("drm/i915: Configure AUX_CH_CTL when enabling the AUX
power domain")
Cc: José Roberto de Souza
Cc: Rodrigo Vivi
Signed-off-by: Imre Deak
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/
According to the spec we should not enable the DDI-IO power domain if
the TypeC port is in the TBT-alt mode, so do that only in the other
TypeC modes or for non-TypeC ports. See the internal BSpec Index/22243.
v2:
- Add the internal BSpec reference to the log message. (José)
Cc: Manasi Navare
Cc
The TypeC port mode can switch dynamically, to reflect that better call
the port's mode as 'mode' rather than 'type'.
While at it:
- s/TC_PORT_TBT/TC_PORT_TBT_ALT/ and s/TC_PORT_TYPEC/TC_PORT_DP_ALT/.
'TYPEC' is ambiguous, TBT_ALT and DP_ALT better match the reality.
- Remove the 'unknown' Type
Unify the TypeC port notation in log messages, so that it matches the
spec. For instance the first ICL TypeC port will read as 'Port C/TC#1'.
v2:
- Format print the name only once. (José)
Cc: José Roberto de Souza
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Signed-off-by: Imre Deak
Reviewed-by: José Ro
Factor out helpers reading/parsing the TypeC specific registers, making
current users of them clearer and letting us use them later.
While at it also:
- Simplify icl_tc_phy_connect() with an early return in legacy mode.
- Simplify the live status check using one bitmask for all HPD bits.
- Remove
Based on a recent BSpec update (Index/21750) we must handle the TCCOLD
event associated with the DP-alt mode. We can detect this event by
reading an invalid all-1s value from FIA registers.
After detecting TCCOLD we will:
- fall back to TBT-alt mode when attempting to switch to DP-alt mode
- concl
Make the order during detection more consistent: first reset the TypeC
port mode if needed (adding new helpers for this), then detect any
connected sink.
To check if a port mode reset is needed determine first the target port
mode based on the live status if a sink is already connected or the
PHY
In the TypeC TBT-alt port mode we must use the TBT AUX power domain,
fix that.
Cc: Manasi Navare
Cc: Anusha Srivatsa
Cc: José Roberto de Souza
Signed-off-by: Imre Deak
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 19 +++
1 file changed
The TypeC port mode needs to stay fixed whenever the port is active. Do
that by introducing a tc_link_refcount to account for active ports,
avoiding changing the port mode if a reference is held.
During the modeset commit phase we also have to reset the port mode and
update the active PLL reflecti
For consistency s/intel_get_shared_dpll()/intel_reserve_shared_dplls()/
to better match intel_release_shared_dplls(). Also, pass to the
reserve/release and get_dplls/put_dplls hooks the intel_atomic_state and
CRTC object, that way these functions can look up the old or new state
as needed.
Also re
We must keep the TypeC port mode fixed for the duration of the connector
detection and each AUX transfers. Add a new TypeC lock holding it around
these two sequences. For consistency also hold the lock during the port
mode sanitization.
Whenever resetting the port mode (only during the detection f
The PHY status complete flag normally clears when disconnecting the PHY
in DP-alt mode (achieved by switching to safe mode), so wait for the
flag to clear.
v2:
- Use DRM_DEBUG_KMS instead of DRM_DEBUG_DRIVER. (José)
Cc: José Roberto de Souza
Cc: Rodrigo Vivi
Signed-off-by: Imre Deak
Reviewed-b
For using the correct AUX power domains we have to sanitize the TypeC
port mode early, so move that before encoder sanitization. To do this
properly read out the actual port mode instead of just relying on the
VBT legacy port flag (which can be incorrect).
We also verify that the PHY is connected
When enabling a TypeC port we need to reserve all the required PLLs for
it, the TBT PLL for TBT-alt and the MG PHY PLL for DP-alt/legacy sinks.
We can select the proper PLL for the current port mode from the reserved
PLLs only once we selected and locked down the port mode for the whole
duration of
Lane reversal happens only in the FIA module for TBT-alt/DP-alt mode, so
WARN if lane reversal is attempted at a different level. See the
BSpec DDI_BUF_CTL register description.
Cc: Manasi Navare
Cc: José Roberto de Souza
Cc: Rodrigo Vivi
Signed-off-by: Imre Deak
Reviewed-by: José Roberto de S
For clarity factor out the combo PHY and TypeC PHY specific code from
icl_get_dplls() into their own functions.
No functional changes.
Cc: Ville Syrjälä
Cc: Daniel Vetter
Cc: Maarten Lankhorst
Signed-off-by: Imre Deak
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dpll_mg
Disconnecting the TypeC PHY when the port is in legacy mode is not
necessary:
- BSpec doesn't specify a disconnect sequence for legacy mode.
- The use of the PHY is dedicated for the display in legacy mode.
- We keep the PHY always connected during runtime as well in legacy
mode.
We disconnect t
Add state verification for the TypeC port mode wrt. the port's AUX power
well enabling/disabling. Also check the correctness of changing the port
mode:
- When enabling/disabling the AUX power well for a TypeC port we must hold
the TypeC port lock - the case for AUX transfers - or hold a Type C
Use hex numbers, since that makes more sense when decoding a bit pattern.
No functional change.
Suggested-by: Ville Syrjälä
Cc: Animesh Manna
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_tc.c | 15 ---
1 fil
Pass the PLL HW state to the PLL find/reference functions making it
clearer what is their input. Also pass to these the atomic state and the
CRTC object instead of the CRTC state, since they don't require the
latter.
Move setting the PLL in the crtc_state to the get_dpll() hook, which
is the more
== Series Details ==
Series: drm/i915/execlists: Hesitate before slicing
URL : https://patchwork.freedesktop.org/series/62867/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6375_full -> Patchwork_13456_full
Summary
---
== Series Details ==
Series: drm/i915: Fix TypeC port mode switching (rev8)
URL : https://patchwork.freedesktop.org/series/61590/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dcb79cfddbf2 drm/i915/icl: Add support to read out the TBT PLL HW state
0dc2581f9c78 drm/i915: Tune do
== Series Details ==
Series: drm/i915: Fix TypeC port mode switching (rev8)
URL : https://patchwork.freedesktop.org/series/61590/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Add support to read out the TBT PLL HW state
Okay!
Commit: d
== Series Details ==
Series: Extend BT2020 support in iCSC and fixes (rev5)
URL : https://patchwork.freedesktop.org/series/60480/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6379 -> Patchwork_13466
Summary
---
**FA
>-Original Message-
>From: Patchwork [mailto:patchw...@emeril.freedesktop.org]
>Sent: Friday, June 28, 2019 8:34 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org
>Subject: ✗ Fi.CI.BAT: failure for Extend BT2020 support in iCSC and fixes
>(rev5)
>
>== Series Details ==
>
>Series
== Series Details ==
Series: Send a hotplug when edid changes (rev2)
URL : https://patchwork.freedesktop.org/series/62816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6379 -> Patchwork_13467
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Use intel_crtc_state everywhere!
URL : https://patchwork.freedesktop.org/series/62920/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6379 -> Patchwork_13468
Summary
---
**SUCCES
Hi Matt,
Thanks for the enlightening input :-)
On 2019/06/25, Matt Roper wrote:
> PLANE_CURSOR is basically just an indication that that specific plane is
> the one that's also hooked up to the legacy cursor ioctls; like Ville
> says, it shouldn't directly indicate that the plane is less
> featu
For the series:
Tested-by: Anuj Phogat
On Fri, Jun 28, 2019 at 5:07 AM Lionel Landwerlin
wrote:
>
> When a register is readonly there is not much we can tell about its
> value (apart from its default value?). This can be covered by tests
> exercising the value of the register from userspace.
>
On Fri, Jun 28, 2019 at 12:55:17PM +0300, Ville Syrjälä wrote:
On Tue, Jun 25, 2019 at 10:54:21AM -0700, Lucas De Marchi wrote:
From: José Roberto de Souza
On TGL the special EDP transcoder is gone and it should be handled by
transcoder A. Add POWER_DOMAIN_TRANSCODER_A_VDSC to make this
distin
== Series Details ==
Series: drm/i915: Add icl mipi dsi properties (rev2)
URL : https://patchwork.freedesktop.org/series/62770/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6376_full -> Patchwork_13458_full
Summary
---
On Fri, Jun 14, 2019 at 08:17:23AM +0200, Daniel Vetter wrote:
> Only dynamic mode objects, i.e. those which are refcounted and have a free
> callback, can be added while the overall drm_device is visible to
> userspace. All others must be added before drm_dev_register and
> removed after drm_dev_u
On Fri, Jun 28, 2019 at 05:14:51PM +0100, Emil Velikov wrote:
> Hi Matt,
>
> Thanks for the enlightening input :-)
>
> On 2019/06/25, Matt Roper wrote:
>
> > PLANE_CURSOR is basically just an indication that that specific plane is
> > the one that's also hooked up to the legacy cursor ioctls; li
== Series Details ==
Series: drm/i915: CTS fixes (rev7)
URL : https://patchwork.freedesktop.org/series/62437/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6380 -> Patchwork_13469
Summary
---
**SUCCESS**
No regres
== Series Details ==
Series: drm/i915/tgl: Gen12 csb support
URL : https://patchwork.freedesktop.org/series/62890/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6376_full -> Patchwork_13459_full
Summary
---
**SUCCESS
== Series Details ==
Series: Set correct values for N in deep color mode
URL : https://patchwork.freedesktop.org/series/62894/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6376_full -> Patchwork_13461_full
Summary
---
On 2019/06/28, Matt Roper wrote:
> On Fri, Jun 28, 2019 at 05:14:51PM +0100, Emil Velikov wrote:
> > Hi Matt,
> >
> > Thanks for the enlightening input :-)
> >
> > On 2019/06/25, Matt Roper wrote:
> >
> > > PLANE_CURSOR is basically just an indication that that specific plane is
> > > the one th
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Use port clock to set correct N
value
URL : https://patchwork.freedesktop.org/series/62895/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6376_full -> Patchwork_13462_full
===
== Series Details ==
Series: drm/i915: Fix TypeC port mode switching (rev8)
URL : https://patchwork.freedesktop.org/series/61590/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6381 -> Patchwork_13470
Summary
---
**WA
== Series Details ==
Series: drm/i915/ehl: Add support for DPLL4 (v5) (rev4)
URL : https://patchwork.freedesktop.org/series/61684/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6377_full -> Patchwork_13464_full
Summary
From: Imre Deak
There is some scenarios that we are aware that sink probe can fail,
so lets add the infrastructure to let hotplug() hook to request
another probe after some time.
v2: Handle shared HPD pins (Imre)
v3: Rebased
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Signed-off-by
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