We cannot let the request be retired and freed while we are trying to
dump it during error capture. It is not sufficient just to grab a
reference to the request, as during retirement we may free the ring
which we are also dumping. So take the engine lock to prevent retiring
and freeing of the reque
Quoting Janusz Krzysztofik (2019-07-11 07:50:01)
> Follow dim checkpatch recommendation so it doesn't complain on that now
> and again on header file modifications.
>
> v2: Drop testing leftover
>
> Signed-off-by: Janusz Krzysztofik
I'm not sure the entire cc wants to see extern header churn.
R
Specify that we do want a 64b value for sizeof(u32) as we want to
compute the mask of the upper 62bits.
v2: Use round_down() for automatic type promotion
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +-
Remove the raw i915_active_request tracking in favour of the higher
level i915_active tracking for the sole purpose of making the lockless
transition easier in later patches.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_overlay.c | 129 +--
drivers/gpu/drm/i
Modifying a remote context requires careful serialisation with requests
on that context, and that serialisation requires us to take their
timeline->mutex. Make it so.
Note that while struct_mutex rules, we can't create more than one
request in parallel, but that age is soon coming to an end.
v2:
We were using the last_fence to track the last request that used this
vma that might be interpreted by a fence register and forced ourselves
to wait for this request before modifying any fence register that
overlapped our vma. Due to requirement that we need to track any XY_BLT
command, linear or t
Right idea, wrong lock. We already drop struct_mutex before we free the
mmap_offset when freeing the object, so we need to take the vma manager
lock when manipulating the mmap_offset address space for our selftests.
Fixes: 8221d21b0664 ("drm/i915/selftests: Lock the drm_mm while modifying")
Signed
We use timeline->mutex to protect modifications to
context->active_count, and the associated enable/disable callbacks.
Due to complications with engine-pm barrier there is a path where we used
a "superlock" to provide serialised protect and so could not
unconditionally assert with lockdep that it w
Switch to tracking activity via i915_active on individual nodes, only
keeping a list of retired objects in the cache, and reaping the cache
when the engine itself idles.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 2 +-
.../gpu/drm
Lift moving the timeline to/from the active_list on enter/exit in order
to shorten the active tracking span in comparison to the existing
pin/unpin.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 1 -
drivers/gpu/drm/i915/gt/intel_context.c | 2 +
drivers
Avoid a global idle barrier by reconfiguring each context by rewriting
them with MI_STORE_DWORD from the kernel context.
v2: We only need to determine the desired register values once, they are
the same for all contexts.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
Cc: Tvrtko Ursulin
Revi
As every i915_active_request should be serialised by a dedicated lock,
i915_active consists of a tree of locks; one for each node. Markup up
the i915_active_request with what lock is supposed to be guarding it so
that we can verify that the serialised updated are indeed serialised.
Signed-off-by:
Trust that we now have adequate protection over the low level structures
via the engine->active.lock to allow ourselves to capture the GPU error
state without the heavy hammer of stop_machine(). Sadly this does mean
that we have to forgo some of the lesser used information (not derived
from the act
Move the active tracking for the frontbuffer operations out of the
i915_gem_object and into its own first class (refcounted) object. In the
process of detangling, we switch from low level request tracking to the
easier i915_active -- with the plan that this avoids any potential
atomic callbacks as
Follow dim checkpatch recommendation so it doesn't complain on that now
and again on header file modifications.
v2: Drop testing leftover
Signed-off-by: Janusz Krzysztofik
---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 2 +-
drivers/gpu/drm/i915/gvt/gtt.h | 13 +++---
drivers/gpu
Hi, Derek:
On Tue, 2019-07-09 at 19:16 -0700, Derek Basehore wrote:
> This inits the panel orientation property for the mediatek dsi driver
> if the panel orientation (connector.display_info.panel_orientation) is
> not DRM_MODE_PANEL_ORIENTATION_UNKNOWN.
>
Reviewed-by: CK Hu
> Signed-off-by: D
Quoting Umesh Nerlige Ramappa (2019-07-11 00:43:21)
> On Tue, Jul 09, 2019 at 03:33:44PM +0300, Lionel Landwerlin wrote:
> >+static u32 *save_register(struct drm_i915_private *i915, u32 *cs,
> >+i915_reg_t reg, u32 offset, u32 dword_count)
> >+{
> >+ uint32_t d;
> >+
>
Hi Chris,
On Wednesday, July 10, 2019 5:01:04 PM CEST Chris Wilson wrote:
> Quoting Janusz Krzysztofik (2019-07-10 15:52:39)
> > Follow dim checkpatch recommendation so it doesn't complain on that now
> > and again on header file modifications.
> >
> > Signed-off-by: Janusz Krzysztofik
>
> > --
On 7/10/2019 10:27 PM, Michal Wajdeczko wrote:
On Tue, 09 Jul 2019 16:17:02 +0200, Joonas Lahtinen
wrote:
Better subject would be: "Enable HuC (through GuC) on supported
platforms"
Such subject sounds better, but on one hand it does not reflect real
code change (since we are not explicitly
On Wed, Jul 10, 2019 at 11:29:40AM +, Patchwork wrote:
> == Series Details ==
>
> Series: EHL port programming (rev7)
> URL : https://patchwork.freedesktop.org/series/62492/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6444_full -> Patchwork_13589_full
> ===
== Series Details ==
Series: series starting with [CI,01/21] drm/i915: Add 4th pipe and transcoder
URL : https://patchwork.freedesktop.org/series/63528/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8c5d9599c135 drm/i915: Add 4th pipe and transcoder
e6e0cc3b8702 drm/i915/tgl: a
On Wed, Jul 10, 2019 at 09:04:28PM +0100, Chris Wilson wrote:
> The workarounds was revived in the backmerge that was meant to fix it!
>
> Fixes: 88c90e800675 ("Merge drm/drm-next into drm-intel-next-queued")
> Signed-off-by: Chris Wilson
> Cc: Rodrigo Vivi
Duh! Sorry about that and thanks for
From: Mika Kahola
Add power well 5 to support 4th pipe and transcoder on TGL.
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Lucas De Marchi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-11-lucas.demar...@intel.com
Reviewed-by: Rodrigo Viv
Add port C to workaround to cover Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-22-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display_power.c | 11 ---
From: Vandita Kulkarni
There are 2 new additional typeC ports in Tiger Lake and PORT-C is now a
combophy port. This results in 6 typeC ports and 3 combophy ports.
These 6 TC ports can be DP alternate mode, DP over thunderbolt, native
DP on legacy DP connector or native HDMI on legacy connector.
From: Mahesh Kumar
This patch initializes DDI PORT A, B & C for Tiger lake. Other
TC ports need to be initialized later once corresponding code is there.
Cc: Madhav Chauhan
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.
Current list of PCI IDs for Tiger Lake.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-6-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
include/dr
From: Mahesh Kumar
TGL has 3 combophy ports, so extend check for tigerlake in
intel_port_is_combophy/tc function.
Cc: Mika Kahola
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.
From: Vandita Kulkarni
Add a new pll array for Tiger Lake. The TC pll functions for type C will
be covered in later patches after its phy is implemented.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link:
https
From: Radhakrishna Sripada
Add the enum additions to TGP.
Cc: Rodrigo Vivi
Cc: Joonas Lahtinen
Cc: David Weinehall
Cc: James Ausmus
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231
From: José Roberto de Souza
This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296
From: Vandita Kulkarni
Add 2 new PLLs for additional TC ports. The names for the PLLs on TGL
changed, but most registers remained the same, like MGPLL5_ENABLE,
MGPLL6_ENABLE. So continue to use the name from ICL.
Cc: Madhav Chauhan
Cc: Rodrigo Vivi
Signed-off-by: Vandita Kulkarni
Signed-off-b
From: Mahesh Kumar
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are
mapped to TC ports.
Cc: Anusha Srivatsa
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: Jos
From: Mahesh Kumar
Add VBT-value to DDC bus pin mapping for the same.
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: José Roberto de Souza
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-21-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/di
On TGL the port programming for combophy is very similar to ICL, so
adapt the callers to possibly use the different register values.
v2 (Lucas): Add TODO with about DPLL4 (requested by Ville)
Cc: Vandita Kulkarni
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
From: Daniele Ceraolo Spurio
Tiger Lake is a Intel® Processor containing Intel® HD Graphics.
This is just an initial Tiger Lake definition. PCI IDs, generic support
and new features coming in following patches.
v2 (Lucas):
- Remove modular FIA - feature will be re-introduced in future
Cc: Jo
From: José Roberto de Souza
On Tiger Lake there is one more pipe - check if it's fused.
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-8-lucas.demar...@intel.com
---
drivers
From: Rodrigo Vivi
Previously, the recommended B credit for all platforms was 24 / number
of pipes, which would give 6 for newer platforms with 4 pipes. However 6
is not enough and we need 12 on these cases.
We also need a different BW credit for these platforms.
Cc: Arthur J Runyan
Signed-off
Make the icl function generic so it is based on phy type and can be
applied to tgl as well.
I checked if this could not apply to EHL as well, but unfortunately
there the HPD and DDC/GMBUS pins for DDI C are mapped to TypeC Port 1
even though it doesn't have TC phy.
v2: don't add a separate functi
From: Imre Deak
The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are the following:
- Transcoder#EDP removed from power well#1 (Transcoder#A used in
low-power mode instead)
- Transcoder#A is now bac
From: José Roberto de Souza
On TGL the special EDP transcoder is gone and it should be handled by
transcoder A.
v2 (Lucas):
- Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
- Use crtc->dev since new_crtc_state->state may be NULL on atomic
commit (suggested by Maarten)
v3 (Lu
From: Mahesh Kumar
Assume PCH_TGP when platform is TGL.
Cc: Rodrigo Vivi
Signed-off-by: Mahesh Kumar
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-5-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/i915_
Add pipe D and transcoder D to prepare for platforms having them.
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
Reviewed-by: Ville Syrjälä
Link:
https://patchwork.freedesktop.org/patch/msgid/20190708231629.9296-2-lucas.demar...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 3
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> Add VBT-value to DDC bus pin mapping for the same.
We have almost the same information in 3 different places as per patch
15, 16 and this one =/
Anyways lets not block TGL to do refactors:
Reviewed-by: José Rober
On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
> ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14
> are
> mapped to TC ports.
Reviewed-by: José Roberto de Souza
>
> Cc:
On Tue, Jul 09, 2019 at 03:33:44PM +0300, Lionel Landwerlin wrote:
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indica
On Wed, 2019-07-10 at 12:49 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> On TGL the special EDP transcoder is gone and it should be handled by
> transcoder A.
>
> v2 (Lucas):
> - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
> - Use crtc->dev since new_crtc_s
== Series Details ==
Series: drm/dp/dsc: Add Support for all BPCs supported by TGL
URL : https://patchwork.freedesktop.org/series/63526/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/dp/dsc: Add Support for all BPCs supported by TGL
-O:drivers/gpu
On Thu, 2019-05-23 at 16:17 -0700, Rodrigo Vivi wrote:
> Suspend resume is broken if we try to enable/disable dc9 on
> cases with disabled displays.
>
> v2: Make checkpatch happy:
> - braces {} are not necessary for single statement blocks
>
> v3: Also move hsw/bdw PC8 sequences since they ar
DSC engine on ICL supports only 8 and 10 BPC as the input
BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
Add 12 BPC support for DSC while calculating compression
configuration.
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 +++--
1 f
Load GuC for Comet Lake. Depending on the REVID,
we load either the KBL firmware or the CML firmware.
v2: Use CFL for CML platform check.(Michal)
v3: Use >=5 for future proofing(Michal, Daniele)
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm
On Wed, Jul 10, 2019 at 09:40:05PM +0300, Ville Syrjälä wrote:
On Mon, Jul 08, 2019 at 04:16:21PM -0700, Lucas De Marchi wrote:
From: Mahesh Kumar
Bit definitions for port-select got changed for TRANS_CLK_SEL &
TRANS_DDI_FUNC_CTL registers in TGL.
Signed-off-by: Mahesh Kumar
Signed-off-by: L
(adding sunpeng...@amd.com to the thread here, since this is relevant to the DP
aux device work)
I mentioned this in IRC, but figured I should mention it on the ML as well so it
can be discussed further. Honestly: I don't like the way we implement the path
prop for MST. Mainly because
* It looks
On Tue, Jul 02, 2019 at 09:42:05PM +0200, Maarten Lankhorst wrote:
> This can be useful when calling the vdsc enable functions
> directly without encoder.
Would this be the case on the slave pipe where we need to enable DSC but there
is no transcoder enabled for that pipe?
Manasi
>
> Signed-off
On Wed, 2019-07-10 at 23:59 +0200, Paul Bolle wrote:
> James Bottomley schreef op wo 10-07-2019 om 10:35 [-0700]:
> > I can get back to it this afternoon, when I'm done with the meeting
> > requirements and doing other dev stuff.
>
> I've started bisecting using your suggestion of that drm merge:
On Wed, 2019-07-10 at 04:20 -0700, Rodrigo Vivi wrote:
> On Fri, Jun 28, 2019 at 02:39:20PM -0700, José Roberto de Souza
> wrote:
> > From: Imre Deak
> >
> > There is some scenarios that we are aware that sink probe can fail,
> > so lets add the infrastructure to let hotplug() hook to request
> >
From: Imre Deak
There is some scenarios that we are aware that sink probe can fail,
so lets add the infrastructure to let hotplug() hook to request
another probe after some time.
v2: Handle shared HPD pins (Imre)
v3: Rebased
v4: Renamed INTEL_HOTPLUG_NOCHANGE to INTEL_HOTPLUG_UNCHANGED to keep
i
Right now we are aware of two cases that needs another hotplug retry:
- Unpowered type-c dongles
- HDMI slow unplug
Both have a complete explanation in the code to schedule another run
of the hotplug handler.
It could have more checks to just trigger the retry in those two
specific cases but why
James Bottomley schreef op wo 10-07-2019 om 10:35 [-0700]:
> I can get back to it this afternoon, when I'm done with the meeting
> requirements and doing other dev stuff.
I've started bisecting using your suggestion of that drm merge:
$ git bisect log
git bisect start
# good: [89c3b37a
On 7/10/19 9:57 AM, Michal Wajdeczko wrote:
On Wed, 10 Jul 2019 02:54:29 +0200, Daniele Ceraolo Spurio
wrote:
Instead of always checking in the device config is GuC and HuC are
s/is/if
supported or not, we can save the state in the uc_fw structure and
avoid going through i915 every time
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/display/icl: Bump up the
vdisplay to reflect higher transcoder vertical limits
URL : https://patchwork.freedesktop.org/series/63522/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
60f52512f495 drm/i915/display/
On ICL+, the max supported plane height is 4320, so bump it up
To support 4320, we need to increase the number of bits used to
read plane_height to 13 as opposed to older 12 bits.
v2:
* ICL plane height supported is 4320 (Ville)
* Add a new line between max width and max height (Jose)
Cc: Maarten
On ICL+, the vertical limits for the transcoders are increased to 8192 so bump
up
limits in intel_mode_valid()
v3:
* Supported starting ICL (Ville)
* Use the higher limits from TRANS_VTOTAL register (Ville)
v2:
* Checkpatch warning (Manasi)
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by
== Series Details ==
Series: Initial support for Tiger Lake (rev6)
URL : https://patchwork.freedesktop.org/series/62726/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
84393d3db7c9 drm/i915: Add 4th pipe and transcoder
a755f8c87f85 drm/i915/tgl: add initial Tiger Lake definition
The workarounds was revived in the backmerge that was meant to fix it!
Fixes: 88c90e800675 ("Merge drm/drm-next into drm-intel-next-queued")
Signed-off-by: Chris Wilson
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/driv
From: Mika Kahola
Add power well 5 to support 4th pipe and transcoder on TGL.
v2: remove parts that should be squashed on the generic power well
support patch
Cc: James Ausmus
Cc: Imre Deak
Signed-off-by: Mika Kahola
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
.../drm
From: Imre Deak
The patch adds the new power wells introduced by TGL (GEN 12) and
maps these to existing/new power domains. The changes for GEN 12 wrt
to GEN 11 are the following:
- Transcoder#EDP removed from power well#1 (Transcoder#A used in
low-power mode instead)
- Transcoder#A is now bac
From: José Roberto de Souza
On TGL the special EDP transcoder is gone and it should be handled by
transcoder A.
v2 (Lucas):
- Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
- Use crtc->dev since new_crtc_state->state may be NULL on atomic
commit (suggested by Maarten)
v3 (Lu
On Wed, Jul 10, 2019 at 10:18:38PM +0300, Ville Syrjälä wrote:
> On Tue, Jul 09, 2019 at 02:47:35PM -0700, Manasi Navare wrote:
> > On TGL+, the plane height for 8K planes can be 4320, so bump it up
> > To support 4320, we need to increase the number of bits used to
> > read plane_height to 13 as o
On Wed, Jul 10, 2019 at 12:22:51PM -0700, Lucas De Marchi wrote:
> On Wed, Jul 10, 2019 at 09:33:39PM +0300, Ville Syrjälä wrote:
> >On Mon, Jul 08, 2019 at 10:28:15AM -0700, Lucas De Marchi wrote:
> >> From: Anusha Srivatsa
> >>
> >> Some platforms may have Modular FIA. If Modular FIA is used in
On Wed, Jul 10, 2019 at 12:24:15PM -0700, Manasi Navare wrote:
> On Wed, Jul 10, 2019 at 10:15:05PM +0300, Ville Syrjälä wrote:
> > On Tue, Jul 09, 2019 at 05:06:13PM -0700, Manasi Navare wrote:
> > > On TGL+ we support 8K display resolution, hence bump up the vertical
> > > active limits to 4320 i
On Wed, Jul 10, 2019 at 09:33:39PM +0300, Ville Syrjälä wrote:
On Mon, Jul 08, 2019 at 10:28:15AM -0700, Lucas De Marchi wrote:
From: Anusha Srivatsa
Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
then Display Driver will access the additional instances of
FIA based on
On Wed, Jul 10, 2019 at 10:15:05PM +0300, Ville Syrjälä wrote:
> On Tue, Jul 09, 2019 at 05:06:13PM -0700, Manasi Navare wrote:
> > On TGL+ we support 8K display resolution, hence bump up the vertical
> > active limits to 4320 in intel_mode_valid()
> >
> > v2:
> > * Checkpatch warning (Manasi)
> >
On Tue, Jul 09, 2019 at 02:47:35PM -0700, Manasi Navare wrote:
> On TGL+, the plane height for 8K planes can be 4320, so bump it up
> To support 4320, we need to increase the number of bits used to
> read plane_height to 13 as opposed to older 12 bits.
>
> Cc: Maarten Lankhorst
> Cc: Ville Syrjäl
On Tue, Jul 09, 2019 at 05:06:13PM -0700, Manasi Navare wrote:
> On TGL+ we support 8K display resolution, hence bump up the vertical
> active limits to 4320 in intel_mode_valid()
>
> v2:
> * Checkpatch warning (Manasi)
>
> Cc: Maarten Lankhorst
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navar
Hi Kyle, Ben, Josh,
Can these i915 changes be merged to linux-firmware.git?
Thanks,
Anusha
From: Srivatsa, Anusha
Sent: Monday, July 8, 2019 2:54 PM
To: linux-firmw...@kernel.org
Cc: intel-gfx@lists.freedesktop.org
Subject: PR- GUC v33 (BXT,SKL,GLK.KBL,ICL)
Hi,
Can these i915 changes be merged
On Tue, Jul 09, 2019 at 04:04:58PM -0700, Souza, Jose wrote:
> On Tue, 2019-07-09 at 14:47 -0700, Manasi Navare wrote:
> > On TGL+ we support 8K display resolution, hence bump up the vertical
> > active limits to 4320 in intel_mode_valid()
> >
> > Cc: Maarten Lankhorst
> > Cc: Ville Syrjälä
> >
On Tue, Jul 09, 2019 at 04:07:23PM -0700, Souza, Jose wrote:
> On Tue, 2019-07-09 at 14:47 -0700, Manasi Navare wrote:
> > On TGL+, the plane height for 8K planes can be 4320, so bump it up
> > To support 4320, we need to increase the number of bits used to
> > read plane_height to 13 as opposed to
On Wed, Jul 03, 2019 at 04:03:53PM -0700, Vivek Kasireddy wrote:
> This patch adds support for DPLL4 on EHL that include the
> following restrictions:
>
> - DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
> DPLL4 can be used with other DDIs, including DDID
> (combo port A ext
On Tue, Jul 09, 2019 at 08:58:32AM -0700, Lucas De Marchi wrote:
> On Tue, Jul 09, 2019 at 03:56:51PM +0300, Ville Syrjälä wrote:
> >On Mon, Jul 08, 2019 at 04:16:28PM -0700, Lucas De Marchi wrote:
> >> On TGL the port programming for combophy is very similar to ICL, so
> >> adapt the callers to po
On Mon, Jul 08, 2019 at 04:16:21PM -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> Bit definitions for port-select got changed for TRANS_CLK_SEL &
> TRANS_DDI_FUNC_CTL registers in TGL.
>
> Signed-off-by: Mahesh Kumar
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/displa
On Wed, 10 Jul 2019 02:54:37 +0200, Daniele Ceraolo Spurio
wrote:
Get rid of them to avoid more users being added while the guc code
transitions to use gt more than i915.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
Acked-by: Michal Wajdeczko
drivers/gpu/drm/i915/gt
On Wed, 10 Jul 2019 02:54:35 +0200, Daniele Ceraolo Spurio
wrote:
With our HW interface logic moving from i915 to gt and with GuC and HuC
being part of the gt HW, it makes sense to use the intel_gt structure
instead of i915 as our reference object in GuC/HuC paths.
Signed-off-by: Daniele Cer
On Mon, Jul 08, 2019 at 10:28:15AM -0700, Lucas De Marchi wrote:
> From: Anusha Srivatsa
>
> Some platforms may have Modular FIA. If Modular FIA is used in the SOC,
> then Display Driver will access the additional instances of
> FIA based on pre-assigned offset in GTTMADDR space.
>
> Each Modula
On Wed, 10 Jul 2019 02:54:34 +0200, Daniele Ceraolo Spurio
wrote:
All the intel_uc_* can now be moved to work on the intel_uc structure
for better encapsulation of uc-related actions.
Note: I've introduced uc_to_gt instead of uc_to_i915 because the aim is
to move everything to be gt-focused
On Wed, 10 Jul 2019 02:54:33 +0200, Daniele Ceraolo Spurio
wrote:
Being part of the GT HW, it make sense to keep the guc/huc structures
inside the GT structure. To help with the encapsulation work done by the
following patches, both structures are placed inside a new intel_uc
container. Altho
On Wed, 10 Jul 2019 02:54:32 +0200, Daniele Ceraolo Spurio
wrote:
Both microcontrollers are part of the GT HW and are closely related to
GT operations. To keep all the files cleanly together, they've been
placed in their own subdir inside the gt/ folder
Signed-off-by: Daniele Ceraolo Spurio
>-Original Message-
>From: Wajdeczko, Michal
>Sent: Wednesday, July 10, 2019 7:27 AM
>To: intel-gfx@lists.freedesktop.org; Joonas Lahtinen
>; Srivatsa, Anusha
>; Ye, Tony
>Cc: Ceraolo Spurio, Daniele ; Chris Wilson
>
>Subject: Re: [PATCH 2/2] drm/i915/guc: Turn on GuC/HuC auto mode
>
>On
On Wed, 2019-07-10 at 18:45 +0200, Paul Bolle wrote:
> James Bottomley schreef op wo 10-07-2019 om 09:32 [-0700]:
> > You seem to be getting it to happen much more often than I can.
> > Last
> > night, on the below pull request it took me a good hour to see the
> > freeze.
>
> Yes. Sometimes withi
Quoting Mika Kuoppala (2019-07-10 17:21:15)
> Chris Wilson writes:
> > + pd = alloc_pd(vm);
> > + if (IS_ERR(pd))
> > return pd;
> > - }
> > -
> > - /* 3lvl */
> > - pd = __alloc_pd();
> > - if (!pd)
> > - return ERR_PTR(-ENOMEM);
> > -
> > - p
From: "Steven Rostedt (VMware)"
Currently the intel_update_plane and intel_disable_plane tracepoints record
the address of plane->name in the ring buffer, and then when reading the
ring buffer uses %s to get the name. The issue with this, is that those two
events can be minutes, hours or even day
On Wed, 10 Jul 2019 02:54:31 +0200, Daniele Ceraolo Spurio
wrote:
The 16-bit guc irq vector is unchanged across gens, the only thing that
moved is its position (from the upper 16 bits of the PM regs to its own
register). Instead of duplicating all defines and functions to handle
the 2 differe
On Wed, 10 Jul 2019 02:54:29 +0200, Daniele Ceraolo Spurio
wrote:
Instead of always checking in the device config is GuC and HuC are
s/is/if
supported or not, we can save the state in the uc_fw structure and
avoid going through i915 every time from the low-level uc management
code. while
James Bottomley schreef op wo 10-07-2019 om 09:32 [-0700]:
> You seem to be getting it to happen much more often than I can. Last
> night, on the below pull request it took me a good hour to see the
> freeze.
Yes. Sometimes within a minute of resuming. Typing stuff into evolution seems
to help wit
== Series Details ==
Series: drm/i915: Copy name string into ring buffer for
intel_update/disable_plane tracepoints
URL : https://patchwork.freedesktop.org/series/63516/
State : failure
== Summary ==
Applying: drm/i915: Copy name string into ring buffer for
intel_update/disable_plane tracepo
== Series Details ==
Series: Need to remove char pointers from trace events
URL : https://patchwork.freedesktop.org/series/63513/
State : failure
== Summary ==
Applying: Need to remove char pointers from trace events
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i
On Wed, Jul 10, 2019 at 09:02:22AM -0700, Lucas De Marchi wrote:
> On Wed, Jul 10, 2019 at 04:04:29AM -0700, Rodrigo Vivi wrote:
> > On Tue, Jul 09, 2019 at 09:20:42AM -0700, Lucas De Marchi wrote:
> > > On Tue, Jul 09, 2019 at 04:57:32AM -0700, Rodrigo Vivi wrote:
> > > > On Mon, Jul 08, 2019 at 0
On Wed, Jul 10, 2019 at 03:38:13PM +, Vasilev, Oleg wrote:
> On Wed, 2019-07-10 at 18:35 +0300, Oleg Vasilev wrote:
> > On Wed, 2019-07-10 at 17:31 +0200, Daniel Vetter wrote:
> > > On Thu, Jul 04, 2019 at 11:54:10AM +0300, Oleg Vasilev wrote:
> > > > Bring dmabuf sharing through implementing p
On Wed, 2019-07-10 at 18:16 +0200, Paul Bolle wrote:
> Hi James,
>
> James Bottomley schreef op wo 10-07-2019 om 08:01 [-0700]:
> > I've confirmed that 5.1 doesn't have the regression and I'm now
> > trying to bisect the 5.2 merge window, but since the problem takes
> > quite a while to manifest t
Chris Wilson writes:
> We can simplify our gtt walking code by comparing against NULL for
> scratch entries as opposed to looking up the distinct per-level scratch
> pointer.
>
> The only caveat is to remember to protect external parties and map the
> NULL to the scratch top pd.
>
> Signed-off-by
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