Hi Lionel,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.3-rc7 next-20190904]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux
== Series Details ==
Series: HuC updates (rev2)
URL : https://patchwork.freedesktop.org/series/66361/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6848_full -> Patchwork_14306_full
Summary
---
**SUCCESS**
No regr
Hi Lionel,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.3-rc7]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Lione
Hi Gaurav,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.3-rc7 next-20190904]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL
URL : https://patchwork.freedesktop.org/series/66365/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6848 -> Patchwork_14308
Summary
---
**FAILUR
On Fri, Sep 06, 2019 at 03:46:42PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 9/6/19 3:41 PM, Radhakrishna Sripada wrote:
> > Disable CPS aware color pipe by setting chicken bit.
> >
> > BSpec: 52890
> > HSDES: 1409142259
> >
> > Cc: Stuart Summers
> > Cc: Matt Roper
> > Signed-off-by: Rad
On Fri, Sep 06, 2019 at 03:41:42PM -0700, Radhakrishna Sripada wrote:
> Disable CPS aware color pipe by setting chicken bit.
>
> BSpec: 52890
BSpec: 45829
as well ("This bit must be programmed to 1").
Reviewed-by: Matt Roper
> HSDES: 1409142259
>
> Cc: Stuart Summers
> Cc: Matt Roper
> S
== Series Details ==
Series: cdclk consolidation and rework for BXT-TGL
URL : https://patchwork.freedesktop.org/series/66365/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
637dedda4030 drm/i915: Consolidate bxt/cnl/icl cdclk readout
-:72: CHECK:CAMELCASE: Avoid CamelCase:
#72:
Aside from a few minor register changes and some different clock values,
cdclk design hasn't changed much since gen9lp. Let's consolidate the
handlers for bxt, cnl, and icl to keep the codeflow consistent.
Also, while we're at it, s/bxt_de_pll_update/bxt_de_pll_readout/ since
"update" makes me th
We'd previously combined ICL/TGL logic into the cnl_set_cdclk function,
but BXT is pretty similar as well. Roll the cnl/icl/tgl logic back into
the bxt function; the only things we really need to handle separately
are punit notification and calling different functions to enable/disable
the cdclk P
With all of the cdclk function consolidation, we can cut down on a lot
of platform if/else logic by creating a vfunc that's initialized at
startup.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 76 --
drivers/gpu/drm/i915/i915_d
cdclk design hasn't changed much from BXT onward, but we still have
a lot of different codepaths to handle the different platforms and in
some cases they've evolved in different directions. Let's try to
consolidate some of the common logic where it makes sense.
We also have some functions that ar
The uninitialize flow is the same on all of these platforms, aside from
calculating a different frequency level.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 48 +++---
1 file changed, 14 insertions(+), 34 deletions(-)
diff --git
The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X
dividers in an easy-to-read table for most recent platforms. We've been
translating the data from that table into platform-specific code logic,
but it's easy to overlook an area we need to update when adding new
cdclk values or enabl
The CNL variant of this function is identical to the BXT variant aside
from not needing to handle SSA precharge.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +-
1 file changed, 2 insertions(+), 44 deletions(-)
diff --git a
When reading out the BIOS-programmed cdclk state, let's make sure that
the cdclk value is on the valid list for the platform, ensure that the
VCO matches the cdclk, and ensure that the CD2X divider was set
properly.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/in
The BXT and CNL functions were already basically identical, whereas
ICL's function tried to do its own sanitization rather than calling
bxt_sanitize_cdclk.
This should actually fix a bug in our ICL initialization where it would
consider the /2 CD2X divider invalid and force an unnecessary
sanitiza
Hi Lionel,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to v5.3-rc7 next-20190904]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
== Series Details ==
Series: drm/i915/tgl: Implement Wa_1409142259
URL : https://patchwork.freedesktop.org/series/66364/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6848 -> Patchwork_14307
Summary
---
**SUCCESS**
On 9/6/19 3:41 PM, Radhakrishna Sripada wrote:
Disable CPS aware color pipe by setting chicken bit.
BSpec: 52890
HSDES: 1409142259
Cc: Stuart Summers
Cc: Matt Roper
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_r
Disable CPS aware color pipe by setting chicken bit.
BSpec: 52890
HSDES: 1409142259
Cc: Stuart Summers
Cc: Matt Roper
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 6 insertions
On 9/5/19 2:09 AM, Janusz Krzysztofik wrote:
When trying to reset a device with reset capability disabled or not
supported while rings are full of requests, it has been observed when
running in execlists submission mode that command stream buffer tail
tends to be incremented by apparently still
== Series Details ==
Series: drm/i915: Add more debug information to dp aux code
URL : https://patchwork.freedesktop.org/series/66343/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6844_full -> Patchwork_14305_full
Summary
== Series Details ==
Series: series starting with [1/2] drm/i915: Use engine relative LRIs on
context setup (rev3)
URL : https://patchwork.freedesktop.org/series/66335/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6844_full -> Patchwork_14304_full
===
== Series Details ==
Series: HuC updates (rev2)
URL : https://patchwork.freedesktop.org/series/66361/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6848 -> Patchwork_14306
Summary
---
**SUCCESS**
No regressions fo
On 9/6/19 12:47 PM, Anusha Srivatsa wrote:
Update MAKE_HUC_FW_PATH macro to follow the same convention
as the MAKE_GUC_FW_PATH with the separator changing from "_" to "."
and removing "ver".
The current convention being:
_uc_..patch.bin
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Anush
On 9/6/19 12:47 PM, Anusha Srivatsa wrote:
Updating HuC versions for gen9 and ICL platforms.
Also updating MAKE_HUC_FW_PATH.
The whole series needs to be squashed in a single patch, otherwise it
won't work in the middle. Also, need to add a renamed EHL blob in the FW
repo as well.
I'm assu
== Series Details ==
Series: HuC updates (rev2)
URL : https://patchwork.freedesktop.org/series/66361/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1d66bb74507d drm/i915/uc: Update MAKE_HUC_FW_PATH macro
b5c155bdb7e8 drm/i915/firmware: Load v2.0.0 HuC for SKL
449762fd3f47 drm/i
Updating HuC versions for gen9 and ICL platforms.
Also updating MAKE_HUC_FW_PATH.
From now on we can have same firmware name formats
for both guC and HuC.
Adding the new PR for the same:
The following changes since commit 6ddb9d9704e2171d91439c9c42c5965bf3863de8:
Merge branch 'for-upstream' of
Add support to load the latest version of HuC on ICL.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc
Update MAKE_HUC_FW_PATH macro to follow the same convention
as the MAKE_GUC_FW_PATH with the separator changing from "_" to "."
and removing "ver".
The current convention being:
_uc_..patch.bin
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/i
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b
Add support to load the latest version of HuC on CFL.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc
Add support to load the latest version of HuC on KBL.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc
Add support to load the latest version of HuC on BXT.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc
Add support to load the latest version of HuC on SKL.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc
Add support to load HuC on CML.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 5994a41f47a8..6b8
Add support to load the latest version of HuC on GLK.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc
Quoting Tvrtko Ursulin (2019-09-02 14:59:16)
>
> On 05/08/2019 18:08, Andi Shyti wrote:
> > Hi Chris,
> >
> > On Tue, Jul 30, 2019 at 02:30:27PM +0100, Chris Wilson wrote:
> >> Push the ring creation flags from the outer GEM context to the inner
> >> intel_cotnext to avoid an unsightly back-refer
Quoting Tvrtko Ursulin (2019-09-02 14:42:44)
>
> On 24/07/2019 14:05, Tvrtko Ursulin wrote:
> >
> > On 23/07/2019 16:49, Stuart Summers wrote:
> >> +u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
> >> +{
> >> + int i, offset = slice * sseu->ss_stride;
> >> + u32 ma
On Fri, 2019-09-06 at 14:27 +0300, Ville Syrjälä wrote:
> On Thu, Sep 05, 2019 at 02:09:27PM -0700, José Roberto de Souza
> wrote:
> > From: Dhinakaran Pandiyan
> >
> > Currently we restrict the number of encoders that can be linked to
> > a connector to 3, increase it to match the maximum number
== Series Details ==
Series: drm/i915: Add more debug information to dp aux code
URL : https://patchwork.freedesktop.org/series/66343/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6844 -> Patchwork_14305
Summary
---
On Fri, Sep 06, 2019 at 01:42:55PM +0800, Zhenyu Wang wrote:
>
> Hi,
>
> Here's gvt-next-fixes with two recent fixes, one for recent
> guest hang regression and another for guest reset fix.
>
> Thanks.
> --
> The following changes since commit c36beba6b296b3c05a0f29753b04775e5ae23886:
>
> d
Quoting Daniele Ceraolo Spurio (2019-09-06 16:42:50)
>
> > +static void gen12_init_reg_state(u32 * const regs,
> > + struct intel_context *ce,
> > + struct intel_engine_cs *engine,
> > + struct intel_ring *ring)
== Series Details ==
Series: series starting with [1/2] drm/i915: Use engine relative LRIs on
context setup (rev3)
URL : https://patchwork.freedesktop.org/series/66335/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6844 -> Patchwork_14304
=
Quoting Daniele Ceraolo Spurio (2019-09-06 16:42:50)
>
> On 9/6/19 5:23 AM, Mika Kuoppala wrote:
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -808,8 +808,11 @@ static void virtual_update_register_offsets(u32 *regs,
> > {
> > u32 base =
== Series Details ==
Series: series starting with [1/2] drm/i915: Use engine relative LRIs on
context setup (rev3)
URL : https://patchwork.freedesktop.org/series/66335/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
49f66db7db65 drm/i915: Use engine relative LRIs on context set
Peter, Thomas,
If you could spare a moment for some brainstorming on the topic of
uncore PMU and multiple providers it would be appreciated.
So from i915 we export some metrics as uncore PMU, which shows up under
/sys/devices/i915. Shortsightedness or what, we did not realize that one
day w
On Fri, Sep 06, 2019 at 02:36:49PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 05, 2019 at 11:13:37AM -0700, Matt Roper wrote:
> > Unlike gen11, which always ran at 50MHz when the cdclk PLL was disabled,
> > TGL runs at refclk/2. The 50MHz croclk/2 is only used by hardware
> > during some power stat
On 9/6/19 5:23 AM, Mika Kuoppala wrote:
From: Michel Thierry
Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.
The simplest approach seems to be keeping Gen12 (and future platform)
changes apart from
== Series Details ==
Series: series starting with [1/2] drm/i915: Use engine relative LRIs on
context setup
URL : https://patchwork.freedesktop.org/series/66335/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6841_full -> Patchwork_14302_full
==
Quite many issues currently happen during intel_dp_detect
during dpcd read. Sometimes we can only see that it had failed
in the logs, while no actual reason is available.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 -
1 file changed, 8 insertions(+)
== Series Details ==
Series: series starting with [1/2] drm/i915: Use engine relative LRIs on
context setup (rev2)
URL : https://patchwork.freedesktop.org/series/66335/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6842 -> Patchwork_14303
=
== Series Details ==
Series: series starting with [1/2] drm/i915: Use engine relative LRIs on
context setup (rev2)
URL : https://patchwork.freedesktop.org/series/66335/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
319509655960 drm/i915: Use engine relative LRIs on context set
Daniele pointed out that relative mmio works differently in
on context restore. Instead of adding the engine mmio base to offset,
it masks out the base and adds bits [12:2] to current engine base.
This should allow us to construct context register state to be
applicable to all instances, including
Quoting Mika Kuoppala (2019-09-06 14:31:45)
> @@ -2939,6 +2942,10 @@ void intel_execlists_set_default_submission(struct
> intel_engine_cs *engine)
> if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
> engine->flags |= I915_ENGINE_HAS_PREEMPTION;
> }
> +
Daniele pointed out that relative mmio works differently in
on context restore. Instead of adding the engine mmio base to offset,
it masks out the base and adds bits [12:2] to current engine base.
This should allow us to construct context register state to be
applicable to all instances, including
Patchwork writes:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915: Use engine relative LRIs on
> context setup
> URL : https://patchwork.freedesktop.org/series/66335/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6841 -> Patchwork_14302
> =
On Fri, Sep 6, 2019 at 7:43 AM Ville Syrjälä
wrote:
>
> On Fri, Sep 06, 2019 at 11:31:55AM +, Shankar, Uma wrote:
> >
> >
> > >-Original Message-
> > >From: Ilia Mirkin
> > >Sent: Tuesday, September 3, 2019 6:12 PM
> > >To: Mun, Gwan-gyeong
> > >Cc: Intel Graphics Development ; Shank
== Series Details ==
Series: drm/i915: List modes, regardless of encoder presence (rev2)
URL : https://patchwork.freedesktop.org/series/66330/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6841_full -> Patchwork_14301_full
== Series Details ==
Series: series starting with [1/2] drm/i915: Use engine relative LRIs on
context setup
URL : https://patchwork.freedesktop.org/series/66335/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6841 -> Patchwork_14302
== Series Details ==
Series: series starting with [1/2] drm/i915: Use engine relative LRIs on
context setup
URL : https://patchwork.freedesktop.org/series/66335/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0441c15504e2 drm/i915: Use engine relative LRIs on context setup
-:58
From: Michel Thierry
Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.
The simplest approach seems to be keeping Gen12 (and future platform)
changes apart from the previous gens, while keeping the regist
Daniele pointed out that relative mmio works differently in
on context restore. Instead of adding the engine mmio base to offset,
it masks out the base and adds bits [12:2] to current engine base.
This should allow us to construct context register state to be
applicable to all instances, including
On Fri, 06 Sep 2019, Swati Sharma wrote:
> For cherryview, add hw read out to create hw blob of gamma
> lut values.
>
> Review comments from previous series:
> https://patchwork.freedesktop.org/patch/328252
>
> v4: -No need to initialize *blob [Jani]
> -Removed right shifts [Jani]
> -Dropp
On Fri, 06 Sep 2019, Swati Sharma wrote:
> intel_color_get_gamma_bit_precision() is extended for
> cherryview by adding chv_gamma_precision(), i965 will use existing
> i9xx_gamma_precision() func only.
>
> Signed-off-by: Swati Sharma
Could be part of patch 3/3, but no big deal,
Reviewed-by: Jan
On Fri, 06 Sep 2019, Swati Sharma wrote:
> For i965, add hw read out to create hw blob of gamma
> lut values.
>
> Review comments from old series:
> https://patchwork.freedesktop.org/series/58039/
>
> v4: -No need to initialize *blob [Jani]
> -Removed right shifts [Jani]
> -Dropped dev
== Series Details ==
Series: drm/i915: List modes, regardless of encoder presence (rev2)
URL : https://patchwork.freedesktop.org/series/66330/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6841 -> Patchwork_14301
Summary
--
On Fri, Sep 06, 2019 at 11:31:55AM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ilia Mirkin
> >Sent: Tuesday, September 3, 2019 6:12 PM
> >To: Mun, Gwan-gyeong
> >Cc: Intel Graphics Development ; Shankar,
> >Uma
> >; dri-devel
> >Subject: Re: [PATCH v4 3/7] drm: Add D
== Series Details ==
Series: drm/i915: List modes, regardless of encoder presence (rev2)
URL : https://patchwork.freedesktop.org/series/66330/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
81686dafe104 drm/i915: List modes, regardless of encoder presence
-:22: WARNING:PREFER_SE
On Thu, Sep 05, 2019 at 11:13:37AM -0700, Matt Roper wrote:
> Unlike gen11, which always ran at 50MHz when the cdclk PLL was disabled,
> TGL runs at refclk/2. The 50MHz croclk/2 is only used by hardware
> during some power state transitions.
>
> Bspec: 49201
> Cc: José Roberto de Souza
> Signed-
>-Original Message-
>From: Ilia Mirkin
>Sent: Tuesday, September 3, 2019 6:12 PM
>To: Mun, Gwan-gyeong
>Cc: Intel Graphics Development ; Shankar, Uma
>; dri-devel
>Subject: Re: [PATCH v4 3/7] drm: Add DisplayPort colorspace property
>
>So how would this work with a DP++ connector? Shou
In certain situations encoder might be not present for connector,
however might be useful to display probed modes for the connector,
if any.
v2: Fixed typo in the commit message
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/i915_debugfs.c | 8
1 file changed, 4 insertions
On Thu, Sep 05, 2019 at 02:09:27PM -0700, José Roberto de Souza wrote:
> From: Dhinakaran Pandiyan
>
> Currently we restrict the number of encoders that can be linked to
> a connector to 3, increase it to match the maximum number of encoders
> that can be initialized(32).
>
> To more effiently d
On Fri, 2019-09-06 at 14:23 +0300, Lionel Landwerlin wrote:
> On 06/09/2019 14:14, Stanislav Lisovskiy wrote:
> > In certain situations encoder might be not present for connector,
> > however might be useful to displat probed modes for the connector,
>
> s/displat/display/
Thanks! :)
- Stanislav
On 06/09/2019 14:14, Stanislav Lisovskiy wrote:
In certain situations encoder might be not present for connector,
however might be useful to displat probed modes for the connector,
s/displat/display/
if any.
Signed-off-by: Stanislav Lisovskiy
Tested-by: Lionel Landwerlin
---
drivers/g
On Thu, Sep 05, 2019 at 02:38:24PM -0700, Matt Roper wrote:
> When calculating the PLL ratio we were still assuming that the CD2X
> divider is always /1. For the new frequencies that use a /2 divider
> that needs to be accounted for, otherwise our VCO result will be twice
> as large as it should b
In certain situations encoder might be not present for connector,
however might be useful to displat probed modes for the connector,
if any.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/i915_debugfs.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/driv
== Series Details ==
Series: Send a hotplug when edid changes (rev7)
URL : https://patchwork.freedesktop.org/series/62816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6841_full -> Patchwork_14299_full
Summary
---
*
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev16)
URL : https://patchwork.freedesktop.org/series/60916/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as default for now which should
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer. On TGL in particular
one of the clock domain in which some of that programming goes might
not be powered when we poke thin
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
buffer. In OpenGL, the lack of
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
v
We want the ability to dispatch a set of command buffer to the
hardware, each with a different OA configuration. To achieve this, we
reuse a couple of fields from the execbuf2 struct (I CAN HAZ
execbuf3?) to notify what OA configuration should be used for a batch
buffer. This requires the process m
An upcoming change needs not to be interrupted.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_active.c | 4 +++-
drivers/gpu/drm/i915/i915_active.h | 5 ++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i91
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace commands so that a particu
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
v3: Check that the chained extension is only present once (Chris)
v4: Check that dma_fence_chain_find_seqno returns a non NULL fence (Lionel)
v5: Use BIT_UL
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
v2: Check for invalid flags in execbuffer2 (Lionel)
v3: Rename I915_EXEC_EXT -> I915_EXEC_USE_EXTENSIONS (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v1)
---
At some point in time there was the idea that we could have multiple
stream from the same piece of HW but that never materialized and given
the hard time we already have making everything work with the
submission side, there is no real point having this list of 1 element
around.
Signed-off-by: Lio
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_getparam.c | 4
drivers/gpu/drm/i915/i915_perf
Following a pattern used throughout the driver.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h| 300 +--
drivers/gpu/drm/i915/i915_perf.h | 2 +
drivers/gpu/drm/i915/i915_perf_types.h | 318 +
3 files changed, 321
Hi all,
The series is gaining one patch, splitting away the i915_perf types
into their own header file. The CI reported compilation issues and I
figured as well as fixing them, we could reduce the size of i915_drv.h
a bit more.
No other change apart from the rippling changes from the moving the
t
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_perf.c | 7 +++
2 files changed, 12 insertions(+)
diff --git a/dr
== Series Details ==
Series: Send a hotplug when edid changes (rev7)
URL : https://patchwork.freedesktop.org/series/62816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6841 -> Patchwork_14299
Summary
---
**SUCCESS**
== Series Details ==
Series: Send a hotplug when edid changes (rev7)
URL : https://patchwork.freedesktop.org/series/62816/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c2072e1d23ff drm: Add helper to compare edids.
-:32: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be wr
This series introduce to drm a way to determine if something else
except connection_status had changed during probing, which
can be used by other drivers as well. Another i915 specific part
uses this approach to determine if edid had changed without
changing the connection status and send a hotplug
This counter will be used by drm_helper_probe_detect caller to determine
if anything had changed(including edid, connection status and etc).
Hardware specific driver detect hooks are responsible for updating this
counter when some change is detected to notify the drm part,
which can trigger for exa
Added epoch counter checking to intel_encoder_hotplug
in order to be able process all the connector changes,
besides connection status. Also now any change in connector
would result in epoch counter change, so no multiple checks
are needed.
v2: Renamed change counter to epoch counter. Fixed type n
Many drivers would benefit from using
drm helper to compare edid, rather
than bothering with own implementation.
v2: Added documentation for this function.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/drm_edid.c | 33 +
include/drm/drm_edid.h | 9 +
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