We do not require to register the sysctl paths per instance,
so making registration global.
v2: make sysctl path register and unregister function driver
specific (Tvrtko and Lucas).
Cc: Sudeep Dutt
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Jani Nikula
Signed-off-by:
Adding device name to trace makes debugging easier,
when dealing with multiple gpus.
Cc: Sudeep Dutt
Cc: Rodrigo Vivi
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Jani Nikula
Signed-off-by: Venkata Sandeep Dhanalakota
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 4 +-
On Wed, 11 Dec 2019, Joonas Lahtinen wrote:
> Quoting Jani Nikula (2019-12-11 12:36:10)
>> On Fri, 15 Nov 2019, Chris Wilson wrote:
>> > Quoting Jani Nikula (2019-11-15 11:04:28)
>> >> On Fri, 15 Nov 2019, Chris Wilson wrote:
>> >> > Quoting Jani Nikula (2019-11-15 10:18:40)
>> >> >> Get rid of
> On Dec 11, 2019, at 7:25 AM, Joonas Lahtinen
> wrote:
>
> Quoting Jani Nikula (2019-12-11 12:36:10)
>> On Fri, 15 Nov 2019, Chris Wilson wrote:
>>> Quoting Jani Nikula (2019-11-15 11:04:28)
On Fri, 15 Nov 2019, Chris Wilson wrote:
> Quoting Jani Nikula (2019-11-15 10:18:40)
An oversight in that we use rc6->ctl_enable to disable rc6 on gen9 and
so it does not simply indicate indirect control via a PCU. Switch the
rc6->ctl_enable check for a platform check.
Fixes: 972745fd5770 ("drm/i915/gt: Disable manual rc6 for Braswell/Baytrail")
Signed-off-by: Chris Wilson
---
As the i915 local in __force_fw_fetch_failures() may not be used in a
non-debug build, tell the compiler to ignore it and not throw waarning.
Signed-off-by: Chris Wilson
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
On Wed, 11 Dec 2019, Manasi Navare wrote:
> On Wed, Dec 11, 2019 at 06:23:47PM +0200, Jani Nikula wrote:
>> The check for cpu_transcoder != TRANSCODER_A is more magic than
>> necessary, and potentially misleading. Before TGL, DSC is supported on
>> pipe A if, and only if, it's used with eDP or
On Wed, 11 Dec 2019, Manasi Navare wrote:
> On Wed, Dec 11, 2019 at 06:23:46PM +0200, Jani Nikula wrote:
>> ICL eDP and DSI transcoders have a DSC engine separate from the
>> pipe. Abstract the register selection and fix it for ICL.
>>
>> Add a warning for pipe A DSC on ICL; it does not exist.
== Series Details ==
Series: series starting with [1/3] drm/i915: Use EAGAIN for trylock failures
URL : https://patchwork.freedesktop.org/series/70797/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7547 -> Patchwork_15707
== Series Details ==
Series: series starting with [1/3] drm/i915: Use EAGAIN for trylock failures
URL : https://patchwork.freedesktop.org/series/70797/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3b91b31e1dd2 drm/i915: Use EAGAIN for trylock failures
5a9b3b6fb2d6
== Series Details ==
Series: drm/i915/gt: Pull intel_timeline.requests list under a spinlock
URL : https://patchwork.freedesktop.org/series/70796/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7547 -> Patchwork_15706
== Series Details ==
Series: drm/i915: Some cleanup near the SKL wm/ddb area (rev4)
URL : https://patchwork.freedesktop.org/series/67930/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7543_full -> Patchwork_15693_full
== Series Details ==
Series: drm/i915/gt: Pull intel_timeline.requests list under a spinlock
URL : https://patchwork.freedesktop.org/series/70796/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6ae8510dc6d5 drm/i915/gt: Pull intel_timeline.requests list under a spinlock
-:44:
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Fix cmdparser drm.debug (rev2)
URL : https://patchwork.freedesktop.org/series/70751/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7543_full -> Patchwork_15692_full
== Series Details ==
Series: drm/i915/gt: Only ignore rc6 parking for PCU on byt/bsw
URL : https://patchwork.freedesktop.org/series/70795/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7546 -> Patchwork_15705
Summary
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gem: Prepare gen7 cmdparser for
async execution
URL : https://patchwork.freedesktop.org/series/70793/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7546 -> Patchwork_15704
== Series Details ==
Series: Drop some explicit params in uc_fw functions
URL : https://patchwork.freedesktop.org/series/70758/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7543_full -> Patchwork_15690_full
Summary
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gem: Prepare gen7 cmdparser for
async execution
URL : https://patchwork.freedesktop.org/series/70793/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
518b2b4fa5e0 drm/i915/gem: Prepare gen7 cmdparser for async
== Series Details ==
Series: drm/i915/gt: Mark up ips_mchdev pointer access
URL : https://patchwork.freedesktop.org/series/70792/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7545 -> Patchwork_15703
Summary
---
== Series Details ==
Series: drm/i915/gt: Mark up ips_mchdev pointer access
URL : https://patchwork.freedesktop.org/series/70792/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/gt: Mark up ips_mchdev pointer access
== Series Details ==
Series: drm/i915/uc: Ignore maybe-unused debug-only i915 local
URL : https://patchwork.freedesktop.org/series/70791/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7545 -> Patchwork_15702
Summary
== Series Details ==
Series: series starting with [1/2] drm: Handle connector tile support only for
modes that match tile size
URL : https://patchwork.freedesktop.org/series/70790/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7545 -> Patchwork_15701
== Series Details ==
Series: i915 fixes to handle hotplug cases on 8K tiled monitor
URL : https://patchwork.freedesktop.org/series/70788/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7545 -> Patchwork_15700
Summary
== Series Details ==
Series: i915 fixes to handle hotplug cases on 8K tiled monitor
URL : https://patchwork.freedesktop.org/series/70788/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8279f374e563 drm/i915/dp: Make sure all tiled connectors get added to the state
with full
== Series Details ==
Series: Split up intel_lrc.c
URL : https://patchwork.freedesktop.org/series/70787/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7545 -> Patchwork_15699
Summary
---
**SUCCESS**
No regressions
Currently we use the intel_timeline.mutex to guard constructing and
retiring requests in the timeline, including the adding and removing of
the request from the list of requests (intel_timeline.requests).
However, we want to peek at neighbouring elements in the request list
while constructing a
As we stash a pointer to the HWSP cacheline on the request, when reading
it we only need confirm that the cacheline is still valid by checking
that the request and timeline are still intact.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_timeline.c | 38
While not good behaviour, it is, however, established behaviour that we
can punt EAGAIN to userspace if we need to retry the ioctl. When trying
to acquire a mutex, prefer to use EAGAIN to propagate losing the race
so that if it does end up back in userspace, we try again.
Signed-off-by: Chris
== Series Details ==
Series: series starting with [v2,rebased,01/11] drm: Add
__drm_atomic_helper_crtc_state_reset() & co.
URL : https://patchwork.freedesktop.org/series/70775/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7545 -> Patchwork_15698
== Series Details ==
Series: Split up intel_lrc.c
URL : https://patchwork.freedesktop.org/series/70787/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4fa85f63db3e drm/i915: introduce logical_ring and lr_context naming
e25d3a53a30a drm/i915: Move struct intel_virtual_engine to
Currently we use the intel_timeline.mutex to guard constructing and
retiring requests in the timeline, including the adding and removing of
the request from the list of requests (intel_timeline.requests).
However, we want to peek at neighbouring elements in the request list
while constructing a
== Series Details ==
Series: drm/i915/dsc: fixes for ICL DSI DSC
URL : https://patchwork.freedesktop.org/series/70770/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7545 -> Patchwork_15697
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915/dsi: fix pipe D readout for DSI transcoders (rev2)
URL : https://patchwork.freedesktop.org/series/70752/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7545 -> Patchwork_15696
Summary
On Thu, Nov 14, 2019 at 05:05:12PM +0100, Maarten Lankhorst wrote:
> DSC is available on the display emulator, but not set in DPCD.
> Override the entries to allow bigjoiner testing.
In general for these hacks for specific emulator, can we base it on certain
i915 parameter like
dsc_emaulator or
On Wed, Dec 11, 2019 at 12:10:41PM +0530, Bharadiya,Pankaj wrote:
On Tue, Dec 10, 2019 at 09:57:39PM -0800, Lucas De Marchi wrote:
On Mon, Dec 09, 2019 at 08:09:02PM +0530, Pankaj Bharadiya wrote:
>intel_bw_state allocated memory is not getting freed even after
>module removal.
>
>kmemleak
On 12/10/19 12:47 PM, Michal Wajdeczko wrote:
Instead of spreading multiple conditionals across the uC code
to find out current mode of uC operation, start using predefined
set of function pointers that reflect that mode.
Begin with pair of init_hw/fini_hw functions that are responsible
for
On 12/10/19 1:00 PM, Chris Wilson wrote:
Quoting Michal Wajdeczko (2019-12-10 20:47:44)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
index 2bd8326130f1..3410d35f8b0c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
+++
An oversight in that we use rc6->ctl_enable to disable rc6 on gen9 and
so it does not simply indicate indirect control via a PCU. Switch the
rc6->ctl_enable check for a platform check.
Fixes: 972745fd5770 ("drm/i915/gt: Disable manual rc6 for Braswell/Baytrail")
Signed-off-by: Chris Wilson
---
Hi Animesh/Jani,
Is this the right way to force a full modeset by adding new
dev_priv->dp_phy_comp?
Also its still not clear to me how this will work without actualling using the
phy link rate
and lane count stored in the phy test pattern params to compute the pipe config?
Currently those only
On Wed, Dec 11, 2019 at 02:04:48PM -0800, Daniele Ceraolo Spurio wrote:
On 12/11/19 1:20 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-12-11 21:12:40)
Ahead of splitting out the code specific to execlists submission to its
own file, we can re-organize the code within the
Hi Animesh,
I dont see the patch revision with these fixes, have you sent it to the M-L?
Manasi
On Tue, Nov 19, 2019 at 12:17:03AM +0530, Animesh Manna wrote:
>
>
> On 11/18/2019 12:11 PM, Manasi Navare wrote:
> >On Fri, Nov 15, 2019 at 08:55:48PM +0530, Animesh Manna wrote:
> >>set pattern
On Wed, Dec 11, 2019 at 01:34:20PM -0800, Daniele Ceraolo Spurio wrote:
On 12/11/19 1:22 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-12-11 21:12:42)
Having the virtual engine handling in its own file will make it easier
call it from or modify for the GuC implementation
The gen7 cmdparser is primarily a promotion-based system to allow access
to additional registers beyond the HW validation, and allows fallback to
normal execution of the user batch buffer if valid and requires
chaining. In the next patch, we will do the cmdparser validation in the
pipeline
---
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index bba6b50e6beb..da3e9b5752ac 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@
Execute the cmdparser asynchronously as part of the submission pipeline.
Using our dma-fences, we can schedule execution after an asynchronous
piece of work, so we move the cmdparser out from under the struct_mutex
inside execbuf as run it as part of the submission pipeline. The same
security
drivers/gpu/drm/i915/gt/intel_rps.c:1726:24: error: incompatible types in
comparison expression (different address spaces):
drivers/gpu/drm/i915/gt/intel_rps.c:1726:24:struct drm_i915_private
[noderef] *
drivers/gpu/drm/i915/gt/intel_rps.c:1726:24:struct drm_i915_private *
== Series Details ==
Series: series starting with [1/2] drm/i915/perf: Register sysctl path globally
URL : https://patchwork.freedesktop.org/series/70768/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7543 -> Patchwork_15695
As the i915 local in __force_fw_fetch_failures() may not be used in a
non-debug build, tell the compiler to ignore it and not throw waarning.
Signed-off-by: Chris Wilson
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
+
+struct i915_request *
+execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
There should be no exports from this file... Did you not also make
guc_submission standalone?
The new GuC submission code will have its own
_unwind_incomplete_requests function, just
Quoting Lucas De Marchi (2019-12-11 22:20:13)
> On Wed, Dec 11, 2019 at 04:19:58PM +, Chris Wilson wrote:
> >Quoting Chris Wilson (2019-12-11 16:17:23)
> >> Quoting Venkata Sandeep Dhanalakota (2019-12-11 16:07:24)
> >> > Make each instance to report the hang only once.
> >> >
> >> > Cc:
On Wed, Dec 11, 2019 at 04:19:58PM +, Chris Wilson wrote:
Quoting Chris Wilson (2019-12-11 16:17:23)
Quoting Venkata Sandeep Dhanalakota (2019-12-11 16:07:24)
> Make each instance to report the hang only once.
>
> Cc: Sudeep Dutt
> Cc: Rodrigo Vivi
> Cc: Daniel Vetter
> Cc: Chris Wilson
On Wed, Dec 11, 2019 at 09:13:18AM -0800, Venkata Sandeep Dhanalakota wrote:
On 19/12/11 04:39, Tvrtko Ursulin wrote:
On 11/12/2019 16:31, Tvrtko Ursulin wrote:
> On 11/12/2019 16:07, Venkata Sandeep Dhanalakota wrote:
> > We do not require to register the sysctl paths per instance,
> > so
On Wed, Dec 11, 2019 at 06:23:46PM +0200, Jani Nikula wrote:
> ICL eDP and DSI transcoders have a DSC engine separate from the
> pipe. Abstract the register selection and fix it for ICL.
>
> Add a warning for pipe A DSC on ICL; it does not exist.
>
> Cc: Manasi Navare
> Cc: Vandita Kulkarni
>
On 12/11/19 1:26 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-12-11 21:12:43)
Done ahead of splitting the lrc file as well, to keep that patch
smaller. Just a straight copy, with the exception of create_scratch()
that has been made common to avoid having 3 instances of it.
On 12/11/19 1:20 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-12-11 21:12:40)
Ahead of splitting out the code specific to execlists submission to its
own file, we can re-organize the code within the intel_lrc file to make
that separation clearer. To achieve this, a number of
== Series Details ==
Series: drm/i915: Use the i915_device name for identifying our request fences
URL : https://patchwork.freedesktop.org/series/70761/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7543 -> Patchwork_15694
On Wed, Dec 11, 2019 at 06:23:47PM +0200, Jani Nikula wrote:
> The check for cpu_transcoder != TRANSCODER_A is more magic than
> necessary, and potentially misleading. Before TGL, DSC is supported on
> pipe A if, and only if, it's used with eDP or DSI transcoders. No
> functional changes.
>
Hmm,
Quoting Andi Shyti (2019-12-11 21:25:59)
> Hi Chris,
>
> > The initial investigated showed that while the PCU on Braswell/Baytrail
> > controlled RC6 itself. setting the software RC6 request made no
> > difference. Further testing reveals though that it causes a delay in the
> > PCU on enabling
On 12/11/19 1:22 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-12-11 21:12:42)
Having the virtual engine handling in its own file will make it easier
call it from or modify for the GuC implementation without leaking the
changes in the context management or execlists submission
Quoting Chris Wilson (2019-12-11 21:20:52)
> Quoting Daniele Ceraolo Spurio (2019-12-11 21:12:40)
> > +static void lr_context_init_reg_state(u32 *reg_state,
> > + const struct intel_context *ce,
> > + const struct
Hi Chris,
> The initial investigated showed that while the PCU on Braswell/Baytrail
> controlled RC6 itself. setting the software RC6 request made no
> difference. Further testing reveals though that it causes a delay in the
> PCU on enabling RC6.
>
> Closes:
Quoting Daniele Ceraolo Spurio (2019-12-11 21:12:44)
> Split out all the code related to the execlists submission flow to its
> own file to keep it separate from the general context management,
> because the latter will be re-used by the GuC submission flow.
>
> Signed-off-by: Daniele Ceraolo
Quoting Daniele Ceraolo Spurio (2019-12-11 21:12:43)
> Done ahead of splitting the lrc file as well, to keep that patch
> smaller. Just a straight copy, with the exception of create_scratch()
> that has been made common to avoid having 3 instances of it.
>
> Signed-off-by: Daniele Ceraolo Spurio
Quoting Daniele Ceraolo Spurio (2019-12-11 21:12:42)
> Having the virtual engine handling in its own file will make it easier
> call it from or modify for the GuC implementation without leaking the
> changes in the context management or execlists submission paths.
No. The virtual engine is
DRM Fb driver expects multiple CRTCs if it sees connector->has_tile
is set, but we need to handle tile support and look for multiple CRTCs
only for the modes that match the tile size. The other modes should
be able to be displayed without tile support or uisng single CRTC.
This patch adds the
In case of tiled displays, if we hotplug just one connector,
fbcon currently just selects the preferred mode and if it is
tiled mode then that becomes a problem if rest of the tiles are
not present.
So in the fbdev driver on hotplug when we probe the client modeset,
if we dont find all the
Quoting Daniele Ceraolo Spurio (2019-12-11 21:12:41)
> From: Matthew Brost
>
> The upcoming GuC submission code will need to use the structure, so
> split it to its own file.
There is no way this struct belongs anywhere else.
You want to add a few vfuncs to the context_ops so we can
abstract
Quoting Daniele Ceraolo Spurio (2019-12-11 21:12:40)
> Ahead of splitting out the code specific to execlists submission to its
> own file, we can re-organize the code within the intel_lrc file to make
> that separation clearer. To achieve this, a number of functions have
> been split/renamed using
Hi Dave and Daniel,
A couple patches from -misc-fixes.
drm-misc-fixes-2019-12-11:
- Expand dma-buf MAINTAINER scope
- Fix mode matching for drivers not using picture_aspect_ratio
Cheers, Sean
The following changes since commit 6645d42d79d33e8a9fe262660a75d5f4556bbea9:
dma-buf: Fix memory
== Series Details ==
Series: drm/i915: Use the i915_device name for identifying our request fences
URL : https://patchwork.freedesktop.org/series/70761/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
856e7af5a09b drm/i915: Use the i915_device name for identifying our request
Add an extra check before making master slave assignments for tiled
displays to make sure we make these assignments only if all tiled
connectors are present. If not then initialize the state to defaults
so it does a normal non tiled modeset without transcoder port sync.
Bugzilla:
In case of tiled displays, all the tiles are linke dto each other
for transcoder port sync. So in intel_atomic_check() we need to make
sure that we add all the tiles to the modeset and if one of the
tiles needs a full modeset then mark all other tiles for a full modeset.
Suggested-by: Ville
While clearing the Ports ync mode enable and master select bits
we need to make sure that we perform a RMW for disable else
it sets the other bits casuing unwanted sideeffects.
Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
Cc: Ville Syrjälä
Cc: Jani Nikula
Fixes: 51528afe7c5e
This has some fixes in the transcoder port sync teardown sequence which
ensures now that the hotplug/unplug is handled gracefully
Manasi Navare (3):
drm/i915/dp: Make sure all tiled connectors get added to the state
with full modeset
drm/i915/dp: Make port sync mode assignments only if
The new GuC submission code will get rid of the execlists emulation and
move towards being a more independent submission flow. However, given
that the HW underneath is still the same, the generic engine HW setup
and context handling can be shared between the GuC and execlists
submission paths.
Having the virtual engine handling in its own file will make it easier
call it from or modify for the GuC implementation without leaking the
changes in the context management or execlists submission paths.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Matthew
From: Matthew Brost
The upcoming GuC submission code will need to use the structure, so
split it to its own file.
Signed-off-by: Matthew Brost
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c |
Ahead of splitting out the code specific to execlists submission to its
own file, we can re-organize the code within the intel_lrc file to make
that separation clearer. To achieve this, a number of functions have
been split/renamed using the "logical_ring" and "lr_context" naming,
respectively for
On 12/5/19 11:14 PM, Lucas De Marchi wrote:
This allows us to isolate reading and writing to the
ICL_DPCLKA_CFGCR0 during the sanitize phase.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 57 +---
1 file changed, 32 insertions(+), 25
On 12/5/19 11:14 PM, Lucas De Marchi wrote:
Instead of "ungated" use the same name for the variable as the bitfield,
making it clearer what's the intent of the checks.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++-
1 file changed, 3
== Series Details ==
Series: drm/i915: Some cleanup near the SKL wm/ddb area (rev4)
URL : https://patchwork.freedesktop.org/series/67930/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7543 -> Patchwork_15693
Summary
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Fix cmdparser drm.debug (rev2)
URL : https://patchwork.freedesktop.org/series/70751/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7543 -> Patchwork_15692
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Fix cmdparser drm.debug (rev2)
URL : https://patchwork.freedesktop.org/series/70751/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e2943a8b9e49 drm/i915: Fix cmdparser drm.debug
da0dfb8ec55a drm/i915: Remove
From: Ville Syrjälä
We have a few places where we want to reset a crtc state to its
default values. Let's add a helper for that. We'll need the new
__drm_atomic_helper_crtc_state_reset() helper for this to allow
us to just reset the state itself without clobbering the
crtc->state pointer.
And
From: Ville Syrjälä
We already have alloc/free helpers for planes, add the same for
crtcs. The main benefit is we get to move all the annoying state
initialization out of the main crtc_init() flow.
Reviewed-by: José Roberto de Souza
Signed-off-by: Ville Syrjälä
---
This function is only called from port sync and it is identical to
what will be executed again in intel_update_crtc() over port sync
pipes.
If it is really necessary it at least deserves a better name and a
comment, leaving it to people working on port sync.
Cc: Ville Syrjälä
Cc: Maarten
Due to DDB overlaps the pipe enabling sequence is not always crescent.
As the previous patch selects the smallest pipe/transcoder in the MST
stream to be master and it needs to be enabled first this changes
were needed to guarantee that.
So first lets enable all pipes that did not needed a
From: Ville Syrjälä
Annoyingly __drm_atomic_helper_crtc_reset() does two
totally separate things:
a) reset the state to defaults values
b) assign the crtc->state pointer
I just want a) without the b) so let's split out part
a) into __drm_atomic_helper_crtc_state_reset(). And
of course we'll do
On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.
So here adding all the CRTCs that shares the same MST stream if
The disable sequence after wait for transcoder off was not correctly
implemented.
The MST disable sequence is basically the same for HSW, SKL, ICL and
TGL, with just minor changes for TGL.
So here calling a new MST function to do the MST sequences, most of
the steps just moved from the post
Check if fastset is allowed by external dependencies like other pipes
and transcoders.
Right now it only forces a fullmodeset when the MST master transcoder
did not changed but the pipe of the master transcoder needs a
fullmodeset so all slaves also needs to do a fullmodeset.
But it will probably
From: Ville Syrjälä
For the sake of symmetry with the crtc stuff let's add
a helper to reset the plane state to sane default values.
For the moment this only gets caller from the plane init.
Reviewed-by: José Roberto de Souza
Signed-off-by: Ville Syrjälä
---
intel_connector_needs_modeset() will be used outside of
intel_display.c in a future patch so it would only be necessary to
remove the state and add the prototype to the header file.
But while at it, I simplified the arguments and changed to intel
types and moved it to a better place
From: Ville Syrjälä
Let's get rid of the redundant intel_ prefix on our variables.
Reviewed-by: José Roberto de Souza
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 32 ++--
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git
== Series Details ==
Series: Drop some explicit params in uc_fw functions
URL : https://patchwork.freedesktop.org/series/70758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7543 -> Patchwork_15690
Summary
---
On 12/11/19 6:04 AM, Michal Wajdeczko wrote:
On Tue, 10 Dec 2019 22:09:17 +0100, Daniele Ceraolo Spurio
wrote:
Since we started using CT buffers on all gens, the function pointers can
only be set to either the _nop() or the _ct() functions. Since the
_nop() case applies to when the CT are
On Wed, 2019-12-11 at 13:08 +0200, Jani Nikula wrote:
> Commit 4d89adc7b56f ("drm/i915/display/dsi: Add support to pipe D")
> added pipe D support for DSI, but failed to update the state readout.
>
Reviewed-by: José Roberto de Souza
> Fixes: 4d89adc7b56f ("drm/i915/display/dsi: Add support to
On 12/11/19 5:43 AM, Michal Wajdeczko wrote:
On Tue, 10 Dec 2019 22:09:16 +0100, Daniele Ceraolo Spurio
wrote:
The GuC supports having multiple CT buffer pairs and we designed our
implementation with that in mind. However, the different channels are not
processed in parallel within the
Hi,
On 11-12-2019 01:24, Linus Walleij wrote:
On Mon, Dec 2, 2019 at 4:49 PM Hans de Goede wrote:
There is only one problem, currently is is not possible to
unregister a mapping added with pinctrl_register_mappings
and the i915 driver is typically a module which can be unloaded
and I believe
Hi Lee,
On 10-12-2019 09:51, Lee Jones wrote:
On Tue, 19 Nov 2019, Hans de Goede wrote:
At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2
different PWM controllers for controlling the LCD's backlight brightness.
Either the one integrated into the PMIC or the one
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