May I know any specific timelines?
> -Original Message-
> From: Navik, Ankit P
> Sent: Saturday, March 14, 2020 10:03 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: S, Srinivasan ; Ursulin, Tvrtko
> ; Kumar, Purushotam
> ; Chelladurai, Paul S
>
> Subject: RE: ✗ Fi.CI.SPARSE: warning for
Hi Srinivas,
This will break OA counter.
I am already working with Tvrtko to make patch scalable
and to make it as per the flow.
Kindly wait for upcoming patch.
PS: Coding guideline:
https://www.kernel.org/doc/html/v4.17/process/submitting-patches.html
Regards,
Ankit
> -Original
On Wed, Mar 11, 2020 at 12:57:32PM +0200, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > The residual w/a batch is casing system instablity on Ivybridge and
little typo here^ ?
> > Baytrail under some workloads, so disable until resolved.
> >
> > Closes:
: Update DRIVER_DATE to 20200225 (2020-02-25 10:41:22 -0800)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2020-03-13
for you to fetch changes up to 217a485c8399634abacd2f138b3524d2e78e8aad:
drm/i915: Update DRIVER_DATE to 20200313
Hi Chris,
> We [will] expose various per-engine scheduling controls. One of which,
> 'preempt_timeout_ms', defines how we wait for a preemption request to be
> honoured by the currently executing context. If it fails to relieve the
> GPU within the required timeout, the engine is reset and the
Hi Chris,
On Wed, Mar 11, 2020 at 09:34:44AM +, Chris Wilson wrote:
> Quite frequently we want to execute on one precise engine, so add a
> convenience routine to create a context that contains only that engine
> in the default [0] slot.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Andi
Hi Chris,
> + lseek(engines, 0, SEEK_SET);
> + while ((len = syscall(SYS_getdents64, engines, buf, sizeof(buf))) > 0) {
> + void *ptr = buf;
> +
> + while (len) {
> + struct linux_dirent64 {
> + ino64_td_ino;
== Series Details ==
Series: series starting with [v5,1/3] drm/i915/perf: remove generated code
URL : https://patchwork.freedesktop.org/series/74681/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8134_full -> Patchwork_16965_full
On Thu, 2020-02-20 at 19:03 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Remove require_force_probe protection
> URL : https://patchwork.freedesktop.org/series/73613/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7963_full ->
On Fri, Mar 13, 2020 at 12:21 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Make the topology id const since we don't want to change it.
>
> Signed-off-by: Ville Syrjälä
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/drm_connector.c | 4 ++--
>
When we can control the preempt_timeout_ms property on an engine, we can
specify a much faster timeout and so expect our tests to run much
faster.
Then we can also avoid the embarrassment if the preempt reset is disabled
and the tests start failing because we are not waiting 10+s for the
Make setting engine tunables easier!
Signed-off-by: Chris Wilson
---
lib/i915/gem_engine_topology.c | 49 +++---
lib/i915/gem_engine_topology.h | 4 +++
2 files changed, 44 insertions(+), 9 deletions(-)
diff --git a/lib/i915/gem_engine_topology.c
On Fri, Mar 13, 2020 at 08:45:35AM +, Laxminarayan Bharadiya, Pankaj wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: 12 March 2020 19:25
> > To: Laxminarayan Bharadiya, Pankaj
> >
> > Cc: jani.nik...@linux.intel.com; dan...@ffwll.ch; intel-
> >
Few edp panels like Sharp is triggering short and long
hpd pulse after panel is getting powered off.
Currently driver is already ignoring long pulse for eDP
panel but in order to process the short pulse, it turns on
the VDD which requires panel power_cycle_delay + panel_power_on_delay
these delay
On 2020-03-04 at 20:45:20 +0200, Ville Syrjälä wrote:
> On Wed, Mar 04, 2020 at 03:33:03PM +0200, Jani Nikula wrote:
> > On Wed, 04 Mar 2020, Anshuman Gupta wrote:
> > > Few edp panels like Sharp is triggering short and long
> > > hpd pulse after panel is getting powered off.
> > > Currently
Hey,
On Fri, 13 Mar 2020, Ville Syrjälä wrote:
> On Fri, Mar 13, 2020 at 04:48:21PM +0200, Kai Vehmanen wrote:
>> This patch moves modifying the min_cdclk at audio component bind
>> phase and extends coverage to all gen9+ platforms. This effectively
>
> So this will now force BXT to never use
== Series Details ==
Series: series starting with [1/2] drm/i915: use effective iDisp BCLK value for
CDCLK calculation
URL : https://patchwork.freedesktop.org/series/74682/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8135 -> Patchwork_16966
> -Original Message-
> From: Tvrtko Ursulin
> Sent: Friday, March 13, 2020 10:48 PM
> To: S, Srinivasan ; intel-gfx@lists.freedesktop.org;
> ch...@chris-wilson.co.uk; Francisco Jerez
> Subject: Re: [Intel-gfx] [PATCH v7 0/3] Dynamic EU configuration of Slice/Sub-
> slice/EU
>
>
>
== Series Details ==
Series: Per client engine busyness (rev7)
URL : https://patchwork.freedesktop.org/series/70977/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8132_full -> Patchwork_16961_full
Summary
---
Hi,
On 13/03/2020 11:12, srinivasa...@intel.com wrote:
From: Srinivasan S
drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within
kernel
This patch sets improves GPU power consumption on Linux kernel based OS such as
Chromium OS, Ubuntu, etc. Following are the power
From: Ville Syrjälä
We're going to want access to the atomic state for iterating
the slave crtcs when enabling the port sync master crtc. Pass
the atomic state all the way down.
The alternative would be yet another encoder hook which we'll
have to call after all the normal modeset stuff is
From: Ville Syrjälä
Don't assume there is just one port sync slave. We might have several.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 98 ++--
1 file changed, 49 insertions(+), 49 deletions(-)
diff --git
From: Ville Syrjälä
Move the final DP_TP_CTL frobbing of port sync to the master
encoder's enable hook. Now neatly out of sight from the high level
modeset code.
And thus we've eliminated all the special casing of port sync
in the high level modeset code.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Transcoder port sync was introduced to the hardware in BDW. We
can trivially enable it for SKL+ since the same codepaths are
already used for ICL+ port sync. The only difference is the actual
location of the bits we need to poke.
We leave BDW out (at least for now) since it
From: Ville Syrjälä
Dump the port sync stat in intel_dump_pipe_config().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
From: Ville Syrjälä
Clean up the TRANS_DDI_FUNC_CTL2 programming/readout by
using REG_FIELD_PREP() & co.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 10 --
2 files changed, 6 insertions(+), 10
From: Ville Syrjälä
Remove the copy pasted port sync crtc enable functions and instead
just split the normal function into the two parts we need.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 128 +++
1 file changed, 45 insertions(+), 83
From: Ville Syrjälä
We have a bunch of code that would like to know which
CPU transcoders are actually present in the hardware. Rather than
use various ad-hoc methods let's just include a full bitmask in
the device info, alongside pipe_mask.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Currently only port sync pipes do the sequence such that
we first do the modeset part for every pipe and then do
the plane/etc. updates. Let's follow that apporach for
all pipes in skl+ so that we can properly integrate the
port sync into the normal modeset flow.
From: Ville Syrjälä
Move the port sync readout into the DDI code where it belongs.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 54 ++
drivers/gpu/drm/i915/display/intel_display.c | 59
2 files changed, 54 insertions(+),
From: Ville Syrjälä
This port sync enable/disable stuff is misplaced. It's just another step
of the normal TRANS_DDI_FUNC_CTL enable. Move it to its natural place.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 71 +++-
From: Ville Syrjälä
Use the recently introduced encoder .compute_config_late() hook to
do the MST master transcoder assignment. Avoids having to do it
in a funny way before we know the CPU transcoder of each pipe.
And now we can also properly use hw.active instead of uapi.active
since it too
From: Ville Syrjälä
The entire crtc state has been reset before readout so
master_transcoder is already set to INVALID.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 2 --
1 file changed, 2 deletions(-)
diff --git
From: Ville Syrjälä
I got tired of waiting for the skl+ port sync to materialize so I
went ahead and did it myself. Now we can maybe get this is into
the hands of actual users.
In the process I also cleared out all the copy pasta that was
added for port sync. LOC still went up though, but I
From: Ville Syrjälä
As with the byte offset (idx) drm_find_displayid_extension() is
the only one who actually knows how much data the resulting DispID
block can contain. So return the length from therein instead of
assuming it's the EDID block length all over.
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
A+B on the previous line, B+A on the next line. Brain hurts.
Signed-off-by: Ville Syrjälä
---
include/drm/drm_displayid.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index
From: Ville Syrjälä
I was playing around with the tile stuff a bit and noticed a bunch of
issues in the DisplayID parser. This series aims to fix what I found.
Ville Syrjälä (9):
drm: Constify topology id
drm/edid: Swap some operands in for_each_displayid_db()
drm/edid: Remove idx==1
From: Ville Syrjälä
Make the topology id const since we don't want to change it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_connector.c | 4 ++--
include/drm/drm_connector.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c
From: Ville Syrjälä
The fact that the DispID starts at byte offset 1 is due to
the DispID coming from and EDID extension block (the first byte
being the extesion block tag). Instead of hadrdocoding that idx==1
assumptions all over let's just have drm_find_displayid_extension()
return it since it
From: Ville Syrjälä
Throw out the magic '5' from validate_displayid() and replace with
the actual thing we mean sizeof(header)+checksum. Also rewrite the
checksum loop to be less hard to parse for mere mortals.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 13 -
1
From: Ville Syrjälä
The EDID extension block checksum byte is not part of the
actual DispID data, so don't use it in validate_displayid().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Ville Syrjälä
Currently the DispID tile block gets parsed in drm_get_edid(), which
is an odd place for it considering we parse nothing else there. Also
this doesn't work for override EDIDs since
drm_connector_update_edid_property() refuses to do its job twice
in such cases. Thus we never
From: Ville Syrjälä
Currently the code assumes that the entire EDID extesion block
can be taken up by the DispID blocks. That is not true. There
is at least always the DispID checksum, and potentially fill
bytes if the extension block uses the interior fill scheme
to pad out to fill EDID block
From: Ville Syrjälä
Instead of everyone having to call validate_displayid() let's just
have drm_find_displayid_extension() do it for them.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git
On Fri, Mar 13, 2020 at 08:37:20AM +, Patchwork wrote:
> == Series Details ==
>
> Series: Gen11 workarounds (rev5)
> URL : https://patchwork.freedesktop.org/series/74475/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8127_full -> Patchwork_16956_full
>
== Series Details ==
Series: drm/i915: do AUD_FREQ_CNTRL state save on all gen9+ platforms
URL : https://patchwork.freedesktop.org/series/74664/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8132_full -> Patchwork_16960_full
== Series Details ==
Series: series starting with [v5,1/3] drm/i915/perf: remove generated code
URL : https://patchwork.freedesktop.org/series/74681/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8134 -> Patchwork_16965
Hi Daniele,
> void debugfs_gt_register(struct intel_gt *gt)
> @@ -24,6 +25,8 @@ void debugfs_gt_register(struct intel_gt *gt)
>
> debugfs_engines_register(gt, root);
> debugfs_gt_pm_register(gt, root);
> +
> + intel_uc_debugfs_register(>uc, root);
> }
>
> void
== Series Details ==
Series: series starting with [v5,1/3] drm/i915/perf: remove generated code
URL : https://patchwork.freedesktop.org/series/74681/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3d2548e48f90 drm/i915/perf: remove generated code
-:24:
On 13/03/2020 14:34, Lionel Landwerlin wrote:
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly with the NOA requirements. NOA
requires a stable
On Fri, Mar 13, 2020 at 04:48:21PM +0200, Kai Vehmanen wrote:
> When the iDisp HDA interface between display and audio is brought
> out from reset, the link parameters must be correctly set before
> reset. This requires the audio driver to call i915 get_power()
> whenever it brings the HDA audio
Hi Daniele,
On Wed, Mar 11, 2020 at 06:16:28PM -0700, Daniele Ceraolo Spurio wrote:
> We currently initialize HuC support based on GuC being enabled in
> modparam; this means that huc_is_supported() can return false on HW that
> does have a HuC when enable_guc=0. The rationale for this behavior
Hey,
On Thu, 12 Mar 2020, Ville Syrjälä wrote:
> On Thu, Mar 12, 2020 at 07:27:58PM +0200, Kai Vehmanen wrote:
>> So I think this starts to look that we should move calling glk_force_audio
>> to bind/unbind pair. I can make a patch for this.
>
> That would stop us from doing dynamic cdclk
When the iDisp HDA interface between display and audio is brought
out from reset, the link parameters must be correctly set before
reset. This requires the audio driver to call i915 get_power()
whenever it brings the HDA audio controller from reset. This is
e.g. done every time audio controller is
Instead of assuming maximum value of BCLK (96Mhz), use the actual value
as configured by BIOS.
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 13 -
drivers/gpu/drm/i915/display/intel_audio.h | 1 +
drivers/gpu/drm/i915/display/intel_cdclk.c | 6 --
A little bit of history :
Back when i915-perf was introduced (4.13), there was no way to
dynamically add new OA configurations to i915. Only the generated
configs baked in at build time were allowed.
It quickly became obvious that we would need to allow applications
to upload
The caller of i915_oa_init_reg_state() already sets this.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_perf.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly with the NOA requirements. NOA
requires a stable power configuration to maintain its configuration.
As
== Series Details ==
Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev6)
URL : https://patchwork.freedesktop.org/series/69980/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8133 -> Patchwork_16964
Summary
---
== Series Details ==
Series: drm/i915/perf: add OA interrupt support (rev6)
URL : https://patchwork.freedesktop.org/series/54280/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8131_full -> Patchwork_16958_full
Summary
On Fri, Mar 13, 2020 at 01:57:58PM +, Lisovskiy, Stanislav wrote:
> >> >> Add correspondent helpers to be able to get old/new bandwidth
> >> >> global state object.
> >> >>
> >> >> v2: - Fixed typo in function call
> >> >> v3: - Changed new functions naming to use convention proposed
> >> >>
== Series Details ==
Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev6)
URL : https://patchwork.freedesktop.org/series/69980/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Get active pending request for given context
== Series Details ==
Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev6)
URL : https://patchwork.freedesktop.org/series/69980/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9df798d37b3b drm/i915: Get active pending request for given context
d713a976ff0d drm/i915: set
>> >> Add correspondent helpers to be able to get old/new bandwidth
>> >> global state object.
>> >>
>> >> v2: - Fixed typo in function call
>> >> v3: - Changed new functions naming to use convention proposed
>> >> by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
>>
>> >Still nak on the
On 13/03/2020 00:41, Tvrtko Ursulin wrote:
On 12/03/2020 18:19, Tvrtko Ursulin wrote:
On 06/03/2020 10:05, Lionel Landwerlin wrote:
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This
On 12/03/2020 20:19, Tvrtko Ursulin wrote:
On 06/03/2020 10:05, Lionel Landwerlin wrote:
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly with the
Am 13.03.20 um 12:21 schrieb Christoph Hellwig:
On Thu, Mar 12, 2020 at 11:19:28AM -0300, Jason Gunthorpe wrote:
The non-page scatterlist is also a big concern for RDMA as we have
drivers that want the page list, so even if we did as this series
contemplates I'd have still have to split the
On Fri, Mar 13, 2020 at 08:49:30AM +, Lisovskiy, Stanislav wrote:
> >> Add correspondent helpers to be able to get old/new bandwidth
> >> global state object.
> >>
> >> v2: - Fixed typo in function call
> >> v3: - Changed new functions naming to use convention proposed
> >> by Jani
== Series Details ==
Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev5)
URL : https://patchwork.freedesktop.org/series/69980/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8133 -> Patchwork_16963
Summary
---
== Series Details ==
Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev5)
URL : https://patchwork.freedesktop.org/series/69980/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Get active pending request for given context
== Series Details ==
Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev5)
URL : https://patchwork.freedesktop.org/series/69980/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b969a95d47cd drm/i915: Get active pending request for given context
80a1bbfce2f4 drm/i915: set
Hi Daniele,
On Wed, Mar 11, 2020 at 06:16:27PM -0700, Daniele Ceraolo Spurio wrote:
> The pool will be private to GuC in the new submission scheme, so we
> won't be able to print it and we can just drop the current legacy code.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Michal Wajdeczko
>
== Series Details ==
Series: drm/i915/selftest: Add move poison patterns
URL : https://patchwork.freedesktop.org/series/74668/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8132 -> Patchwork_16962
Summary
---
From: Srinivasan S
drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within
kernel
This patch sets improves GPU power consumption on Linux kernel based OS such as
Chromium OS, Ubuntu, etc. Following are the power savings.
Power savings on GLK-GT1 Bobba platform running on
From: Srinivasan S
This patch will select optimum eu/slice/sub-slice configuration based on
type of load (low, medium, high) as input.
Based on our readings and experiments we have predefined set of optimum
configuration for each platform(CHT, KBL).
i915_gem_context_set_load_type will select
From: Srinivasan S
This patch gives us the active pending request count which is yet
to be submitted to the GPU.
V2:
* Change 64-bit to atomic for request count. (Tvrtko Ursulin)
V3:
* Remove mutex for request count.
* Rebase.
* Fixes hitting underflow for predictive request. (Tvrtko
From: Srinivasan S
High resolution timer is used for predictive governor to control
eu/slice/subslice based on workloads.
param is provided to enable/disable/update timer configuration
V2:
* Fix code style.
* Move predictive_load_timer into a drm_i915_private
structure.
* Make generic
Op 12-03-2020 om 12:53 schreef Chris Wilson:
> During driver unload, we have many asserts that we have released our
> bookkeeping structs and are idle. In some cases, these struct are
> protected by RCU and we do not release them until after an RCU grace
> period.
>
> Reported-by: Maarten
Quoting Tvrtko Ursulin (2020-03-11 18:26:12)
> From: Tvrtko Ursulin
>
> I need to keep the GEM context around a bit longer so adding an explicit
> flag for syncing execbuf with closed/abandonded contexts.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c
Quoting Tvrtko Ursulin (2020-03-11 18:26:11)
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 6ca797128aa1..ae236058c87e 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -330,17 +330,17 @@ static
== Series Details ==
Series: Per client engine busyness (rev7)
URL : https://patchwork.freedesktop.org/series/70977/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8132 -> Patchwork_16961
Summary
---
**SUCCESS**
Quoting Tvrtko Ursulin (2020-03-11 18:26:10)
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index cb6b6be48978..2c3fd9748d39 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
Quoting Tvrtko Ursulin (2020-03-11 18:26:09)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index ca5420012a22..7def0930684b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1218,12 +1218,14 @@ static void
== Series Details ==
Series: Per client engine busyness (rev7)
URL : https://patchwork.freedesktop.org/series/70977/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Expose list of clients in sysfs
Okay!
Commit: drm/i915: Update client name
On Thu, 12 Mar 2020 18:01:12 +0200
Ville Syrjälä wrote:
> On Thu, Mar 12, 2020 at 03:37:03PM +, Laxminarayan Bharadiya, Pankaj
> wrote:
> >
> >
> > > -Original Message-
> > > From: Ville Syrjälä
> > > Sent: 12 March 2020 19:35
> > > To: Laxminarayan Bharadiya, Pankaj
> > >
> >
Chris Wilson writes:
> Throw in the inverse patterns to create more examples of poison to use
> against the LRC state.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 7 ++-
> 1 file changed, 6
Throw in the inverse patterns to create more examples of poison to use
against the LRC state.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
== Series Details ==
Series: Per client engine busyness (rev7)
URL : https://patchwork.freedesktop.org/series/70977/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
daf5b042e025 drm/i915: Expose list of clients in sysfs
-:74: WARNING:FILE_PATH_CHANGES: added, moved or deleted
On 13/03/2020 01:05, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
This new parameter let's the application choose how often the OA
buffer should be checked on the CPU side for data availability. Longer
polling period tend to reduce CPU overhead if the application does not
care about
On 13/03/2020 01:04, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
We're about to introduce an options to open the perf stream, giving
the user ability to configure how often it wants the kernel to poll
the OA registers for available data.
Right now the workaround against the OA tail
== Series Details ==
Series: drm/i915: do AUD_FREQ_CNTRL state save on all gen9+ platforms
URL : https://patchwork.freedesktop.org/series/74664/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8132 -> Patchwork_16960
Summary
== Series Details ==
Series: drm/i915 Support for integrated privacy screen
URL : https://patchwork.freedesktop.org/series/74650/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8127_full -> Patchwork_16957_full
Summary
>> Add correspondent helpers to be able to get old/new bandwidth
>> global state object.
>>
>> v2: - Fixed typo in function call
>> v3: - Changed new functions naming to use convention proposed
>> by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
>Still nak on the rename.
Cool. Discuss it
Replace the TGL/ICL specific platform checks with a more generic check
using INTEL_GEN(). Fixes bug with broken audio after S3 resume on JSL
platforms.
An initial version of state save and restore of AUD_FREQ_CNTRL register
was added for subset of platforms in commit 87c1694533c9
("drm/i915: save
> -Original Message-
> From: Ville Syrjälä
> Sent: 12 March 2020 19:25
> To: Laxminarayan Bharadiya, Pankaj
>
> Cc: jani.nik...@linux.intel.com; dan...@ffwll.ch; intel-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org; airl...@linux.ie;
>
>> static int
>> skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>> {
>> @@ -4606,22 +4618,29 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
>> *crtc_state)
>> */
>>for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
>>blocks = 0;
>> +
== Series Details ==
Series: Gen11 workarounds (rev5)
URL : https://patchwork.freedesktop.org/series/74475/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8127_full -> Patchwork_16956_full
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915/selftests: Use igt_random_offset()
URL : https://patchwork.freedesktop.org/series/74649/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8127_full -> Patchwork_16955_full
Summary
---
On Wed, Mar 11, 2020 at 02:06:32PM +0530, Anshuman Gupta wrote:
Allow 3-display pipes SKU system with any combination
in INTEL_INFO pipe mask.
B.Spec:50075
changes since RFC:
- using intel_pipe_mask_is_valid() function to check integrity of
pipe_mask. [Ville]
v2:
- simplify condition in
Tvrtko Ursulin writes:
> On 11/03/2020 19:54, Francisco Jerez wrote:
>> Tvrtko Ursulin writes:
>>
>>> On 10/03/2020 22:26, Chris Wilson wrote:
Quoting Francisco Jerez (2020-03-10 21:41:55)
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
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