These helpers are only for use with kernel threads, and I will tie them
more into the kthread infrastructure going forward. Also move the
prototypes to kthread.h - mmu_context.h was a little weird to start with
as it otherwise contains very low-level MM bits.
Signed-off-by: Christoph Hellwig
Hi all,
this series improves the use_mm / unuse_mm interface by better
documenting the assumptions, and my taking the set_fs manipulations
spread over the callers into the core API.
Changes since v1:
- drop a few patches
- fix a comment typo
- cover the newly merged use_mm/unuse_mm caller in
Switch the function documentation to kerneldoc comments, and add
WARN_ON_ONCE asserts that the calling thread is a kernel thread and
does not have ->mm set (or has ->mm set in the case of unuse_mm).
Also give the functions a kthread_ prefix to better document the
use case.
Signed-off-by:
Some architectures like arm64 and s390 require USER_DS to be set for
kernel threads to access user address space, which is the whole purpose
of kthread_use_mm, but other like x86 don't. That has lead to a huge
mess where some callers are fixed up once they are tested on said
architectures, while
== Series Details ==
Series: sna: fix --enable-debug=full
URL : https://patchwork.freedesktop.org/series/76002/
State : failure
== Summary ==
Applying: sna: fix --enable-debug=full
error: sha1 information is lacking or useless (src/sna/compiler.h).
error: could not build fake ancestor
hint:
From: Alexei Podtelezhnikov
Once a typo is fixed, the debug build triggers an assertion failure.
Given that the normal build is just fine, the assert might be wrong.
Signed-off-by: Alexei Podtelezhnikov
---
src/sna/compiler.h | 2 +-
src/sna/sna_accel.c | 2 +-
2 files changed, 2
On Tue, Apr 14, 2020 at 04:04:40PM -0700, José Roberto de Souza wrote:
> Right now dp.regs.dp_tp_ctl/status are only set during the encoder
> pre_enable() hook, what is causing all reads and writes to those
> registers to go to offset 0x0 before pre_enable() is executed.
>
> So if i915 takes the
== Series Details ==
Series: drm/i915/gt: Update PMINTRMSK holding fw
URL : https://patchwork.freedesktop.org/series/75958/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17305_full
Summary
---
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
MAINTAINERS
between commits:
4400b7d68f6e ("MAINTAINERS: sort entries by entry name")
3b50142d8528 ("MAINTAINERS: sort field names for all entries")
from Linus' tree and commits:
5304058b1526 ("dt-bindings:
== Series Details ==
Series: series starting with [1/2] drm/i915/tgl: TBT AUX should use TC power
well ops
URL : https://patchwork.freedesktop.org/series/75998/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8305 -> Patchwork_17319
== Series Details ==
Series: series starting with [1/2] drm/i915/tgl: TBT AUX should use TC power
well ops
URL : https://patchwork.freedesktop.org/series/75998/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610:
On Wed, 2020-04-15 at 16:34 -0700, Matt Roper wrote:
> As on ICL, we want to use the Type-C aux handlers for the TBT aux
> wells
> to ensure the DP_AUX_CH_CTL_TBT_IO flag is set properly.
Reviewed-by: José Roberto de Souza
>
> Fixes: 656409bbaf87 ("drm/i915/tgl: Add power well support")
> Cc:
== Series Details ==
Series: drm/i915/tgl: Wa_14011059788 (rev2)
URL : https://patchwork.freedesktop.org/series/75990/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8304 -> Patchwork_17318
Summary
---
**SUCCESS**
== Series Details ==
Series: devm_drm_dev_alloc, v2
URL : https://patchwork.freedesktop.org/series/75956/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17304_full
Summary
---
**SUCCESS**
No
== Series Details ==
Series: drm/i915/tgl: Wa_14011059788 (rev2)
URL : https://patchwork.freedesktop.org/series/75990/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label
gpu/i915:layout, other
Hi Chris,
On Wed, Apr 15, 2020 at 06:03:17PM +0100, Chris Wilson wrote:
> Since we depend upon RPS generating interrupts after evaluation
> intervals to determine when to up/down clock the GPU, it is imperative
> that we successfully enable interrupt generation! Verify that we do see
> an
As on ICL, we want to use the Type-C aux handlers for the TBT aux wells
to ensure the DP_AUX_CH_CTL_TBT_IO flag is set properly.
Fixes: 656409bbaf87 ("drm/i915/tgl: Add power well support")
Cc: José Roberto de Souza
Cc: Imre Deak
Signed-off-by: Matt Roper
---
AUX power wells sometimes need additional handling besides just
programming the specific power well registers:
* Type-C PHY's also require additional Type-C register programming
* ICL combo PHY's require additional workarounds
* TGL & EHL combo PHY's can be treated like any other power well
On Wed, Apr 15, 2020 at 10:16:59PM +0300, Lionel Landwerlin wrote:
On 15/04/2020 21:55, Umesh Nerlige Ramappa wrote:
On Wed, Apr 15, 2020 at 01:00:30PM +0300, Lionel Landwerlin wrote:
On 13/04/2020 18:48, Umesh Nerlige Ramappa wrote:
A condition in wait_event_interruptible seems to be checked
Reflect recent Bspec changes
v2: fix whitespace, typo
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b632b6bb9c3e..3d12a0617c84 100644
---
On Wed, Apr 15, 2020 at 09:47:21PM +, Patchwork wrote:
> == Series Details ==
>
> Series: Tigerlake workaround updates
> URL : https://patchwork.freedesktop.org/series/75944/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17302_full
>
== Series Details ==
Series: drm/i915/tgl: Wa_14011059788
URL : https://patchwork.freedesktop.org/series/75990/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M]
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Load DP_TP_CTL/STATUS
offset before use it
URL : https://patchwork.freedesktop.org/series/75946/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17303_full
Reflect recent Bspec changes
Signed-off-by: Matt Atwood
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b632b6bb9c3e..30b45c0de6fb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++
== Series Details ==
Series: Tigerlake workaround updates
URL : https://patchwork.freedesktop.org/series/75944/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17302_full
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Use single set of AUX powerwell ops for gen11+
URL : https://patchwork.freedesktop.org/series/75943/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17301_full
On Wed, Apr 15, 2020 at 12:19:05PM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ehl: extended Wa_2006604312 to ehl
> URL : https://patchwork.freedesktop.org/series/75894/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8298_full ->
Hi Dave and Daniel,
Here goes drm-intel-fixes-2020-04-15:
- Fix guest page access by using the brand new VFIO dma r/w interface (Yan)
- Fix for i915 perf read buffers (Ashutosh)
Thanks,
Rodrigo.
The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
Linux 5.7-rc1
Quoting José Roberto de Souza (2020-04-15 20:14:08)
> The intel_display_power_put_async() used in TC cold sequences made
> easy to hit the missing deinitialization of driver in case of load
> failure as seen in the stack trace bellow.
>
> intel_modeset_driver_remove_noirq() had to be removed from
== Series Details ==
Series: drm/i915: Add missing deinitialization cases of load failure
URL : https://patchwork.freedesktop.org/series/75987/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8302 -> Patchwork_17316
Summary
== Series Details ==
Series: drm/i915: Add missing deinitialization cases of load failure
URL : https://patchwork.freedesktop.org/series/75987/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate
Quoting José Roberto de Souza (2020-04-15 20:14:08)
> + i915_reset_error_state(i915);
If you are bored, we should move this to unregister as that is the last
point at which it can be accessed from userspace. Hopefully I remember
next time we are rearranging this sequence.
-Chris
== Series Details ==
Series: drm/i915: Add missing deinitialization cases of load failure
URL : https://patchwork.freedesktop.org/series/75987/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
40cdb21a2c1e drm/i915: Add missing deinitialization cases of load failure
-:17:
On 15/04/2020 21:55, Umesh Nerlige Ramappa wrote:
On Wed, Apr 15, 2020 at 01:00:30PM +0300, Lionel Landwerlin wrote:
On 13/04/2020 18:48, Umesh Nerlige Ramappa wrote:
A condition in wait_event_interruptible seems to be checked twice
before
waiting on the event to occur. These checks are
Chris Wilson writes:
> If we use a non-forcewaked write to PMINTRMSK, it does not take effect
> until much later, if at all, causing a loss of RPS interrupts and no GPU
> reclocking, leaving the GPU running at the wrong frequency for long
> periods of time.
>
> Reported-by: Francisco Jerez
>
The intel_display_power_put_async() used in TC cold sequences made
easy to hit the missing deinitialization of driver in case of load
failure as seen in the stack trace bellow.
intel_modeset_driver_remove_noirq() had to be removed from
i915_driver_modeset_remove_noirq() as those are different
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS
interrupt generation
URL : https://patchwork.freedesktop.org/series/75983/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8302 -> Patchwork_17314
On Wed, Apr 15, 2020 at 01:00:30PM +0300, Lionel Landwerlin wrote:
On 13/04/2020 18:48, Umesh Nerlige Ramappa wrote:
A condition in wait_event_interruptible seems to be checked twice before
waiting on the event to occur. These checks are redundant when hrtimer
events will call
== Series Details ==
Series: i915 lpsp support for lpsp igt (rev9)
URL : https://patchwork.freedesktop.org/series/74648/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8302 -> Patchwork_17315
Summary
---
**SUCCESS**
== Series Details ==
Series: i915 lpsp support for lpsp igt (rev9)
URL : https://patchwork.freedesktop.org/series/74648/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label
gpu/i915:layout,
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS
interrupt generation
URL : https://patchwork.freedesktop.org/series/75983/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8302 -> Patchwork_17314
On Wed, 15 Apr 2020 07:39:00 -0700, Chris Wilson wrote:
>
> The poll() is proving unreliable, where our tests timeout without the
> spinner being terminated. Let's try a blocking read instead!
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1676
> Signed-off-by: Chris Wilson
> Cc:
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS
interrupt generation
URL : https://patchwork.freedesktop.org/series/75983/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
On Wed, Apr 15, 2020 at 05:03:55PM +0200, Hans de Goede wrote:
> Hi,
>
> On 4/15/20 9:39 AM, Daniel Vetter wrote:
> > Allows us to drop the cleanup code on the floor.
> >
> > Sam noticed in his review:
> > > With this change we avoid calling pci_disable_device()
> > > twise in case
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/selftests: Exercise basic RPS
interrupt generation
URL : https://patchwork.freedesktop.org/series/75983/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fbb035e1d2f5 drm/i915/selftests: Exercise basic RPS
The commit's headline says 'vboxvidoe'.
Am 15.04.20 um 09:39 schrieb Daniel Vetter:
> Allows us to drop the cleanup code on the floor.
>
> Sam noticed in his review:
>> With this change we avoid calling pci_disable_device()
>> twise in case vbox_mm_init() fails.
>> Once in vbox_hw_fini() and
New i915_pm_lpsp igt solution approach relies on connector specific
debugfs attribute i915_lpsp_capability, it exposes whether an output is
capable of driving lpsp.
v2:
- CI fixup.
v3:
- register i915_lpsp_info only for supported connector. [Jani]
- use intel_display_power_well_is_enabled()
Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.
Reviewed-by: Animesh Manna
Signed-off-by: Anshuman Gupta
---
v5 has fixed the review comment for [PATCH 2/4]
provided by animesh and rebased the series.
Test-with: 20200409053951.26929-2-anshuman.gu...@intel.com
Anshuman Gupta (4):
drm/i915: Power well id for ICL PG3
drm/i915: Add i915_lpsp_capability debugfs
drm/i915: Add connector dbgfs for all
Add connector debugfs attributes for each intel
connector which is getting register.
v2:
- adding connector debugfs for each connector in
intel_connector_register() to fix CI failure for legacy connectors.
Reviewed-by: Jani Nikula
Signed-off-by: Anshuman Gupta
---
It requires a separate debugfs attribute to expose lpsp
status to user space, as there may be display less configuration
without any valid connected output, those configuration will not be
able to test lpsp status, if lpsp status exposed from a connector
based debugfs attribute.
Reviewed-by:
Since we depend upon RPS generating interrupts after evaluation
intervals to determine when to up/down clock the GPU, it is imperative
that we successfully enable interrupt generation! Verify that we do see
an interrupt if we keep the GPU busy for an entire EI.
Signed-off-by: Chris Wilson
---
If we use a non-forcewaked write to PMINTRMSK, it does not take effect
until much later, if at all, causing a loss of RPS interrupts and no GPU
reclocking, leaving the GPU running at the wrong frequency for long
periods of time.
Reported-by: Francisco Jerez
Suggested-by: Francisco Jerez
Fixes:
On Tue, 2020-04-14 at 22:33 -0700, Lucas De Marchi wrote:
> On Tue, Apr 14, 2020 at 4:03 PM José Roberto de Souza
> wrote:
> > Right now dp.regs.dp_tp_ctl/status are only set during the encoder
> > pre_enable() hook, what is causing all reads and writes to those
> > registers to go to offset 0x0
== Series Details ==
Series: series starting with drm/i915/selftests: Exercise basic RPS interrupt
generation (rev3)
URL : https://patchwork.freedesktop.org/series/75973/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8301 -> Patchwork_17313
== Series Details ==
Series: series starting with drm/i915/selftests: Exercise basic RPS interrupt
generation (rev3)
URL : https://patchwork.freedesktop.org/series/75973/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
== Series Details ==
Series: series starting with drm/i915/selftests: Exercise basic RPS interrupt
generation (rev3)
URL : https://patchwork.freedesktop.org/series/75973/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0454a6c7dd1e drm/i915/selftests: Exercise basic RPS
== Series Details ==
Series: SAGV support for Gen12+ (rev21)
URL : https://patchwork.freedesktop.org/series/75129/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8301 -> Patchwork_17312
Summary
---
**SUCCESS**
No
== Series Details ==
Series: series starting with [v5,1/8] drm/i915/display: Move out code to return
the digital_port of the aux ch
URL : https://patchwork.freedesktop.org/series/75941/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17300_full
== Series Details ==
Series: SAGV support for Gen12+ (rev21)
URL : https://patchwork.freedesktop.org/series/75129/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label
gpu/i915:layout, other
> -Original Message-
> From: Roper, Matthew D
> Sent: Wednesday, April 15, 2020 7:52 AM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/icl: Update forcewake firmware ranges
>
> On Wed, Apr 15, 2020 at 07:28:18AM -0700, Sripada,
Since we depend upon RPS generating interrupts after evaluation
intervals to determine when to up/down clock the GPU, it is imperative
that we successfully enable interrupt generation! Verify that we do see
an interrupt if we keep the GPU busy for an entire EI.
Signed-off-by: Chris Wilson
---
== Series Details ==
Series: series starting with drm/i915/selftests: Exercise basic RPS interrupt
generation (rev2)
URL : https://patchwork.freedesktop.org/series/75973/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND
== Series Details ==
Series: drm/i915/gt: Move the batch buffer pool from the engine to the gt
URL : https://patchwork.freedesktop.org/series/75979/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8301 -> Patchwork_17310
== Series Details ==
Series: drm/i915/gt: Move the batch buffer pool from the engine to the gt
URL : https://patchwork.freedesktop.org/series/75979/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate
== Series Details ==
Series: series starting with [1/2] drm/i915/gt: Try to smooth RPS spikes
URL : https://patchwork.freedesktop.org/series/75927/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17298_full
== Series Details ==
Series: drm/i915/gt: Move the batch buffer pool from the engine to the gt
URL : https://patchwork.freedesktop.org/series/75979/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4498659d6015 drm/i915/gt: Move the batch buffer pool from the engine to the gt
== Series Details ==
Series: i915 lpsp support for lpsp igt (rev8)
URL : https://patchwork.freedesktop.org/series/74648/
State : failure
== Summary ==
Applying: drm/i915: Power well id for ICL PG3
Applying: drm/i915: Add i915_lpsp_capability debugfs
Applying: drm/i915: Add connector dbgfs for
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
Upcasting using a container_of macro is more typesafe, faster and
easier for the compiler to optimize.
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Hans de Goede
LGTM:
Reviewed-by: Hans de Goede
Regards,
Hans
---
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
Already using devm_drm_dev_init, so very simple replacment.
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Hans de Goede
LGTM:
Reviewed-by: Hans de Goede
Regards,
Hans
---
drivers/gpu/drm/tiny/gm12u320.c | 13 -
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
Aside from deleting all the cleanup code we're now also setting a name
for the pool
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Hans de Goede
LGTM:
Reviewed-by: Hans de Goede
Regards,
Hans
---
Future platforms require per-crtc SAGV evaluation
and serializing global state when those are changed
from different commits.
v2: - Add has_sagv check to intel_crtc_can_enable_sagv
so that it sets bit in reject mask.
- Use bw_state in intel_pre/post_plane_enable_sagv
instead of
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
Allows us to drop the cleanup code on the floor.
Sam noticed in his review:
With this change we avoid calling pci_disable_device()
twise in case vbox_mm_init() fails.
Once in vbox_hw_fini() and once in the error path.
v2: Include Sam's review
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
Straightforward conversion.
Signed-off-by: Daniel Vetter
Cc: Hans de Goede
LGTM:
Reviewed-by: Hans de Goede
Regards,
Hans
---
drivers/gpu/drm/vboxvideo/vbox_drv.c | 19 +--
1 file changed, 5 insertions(+), 14
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
We use the baseclass pattern here, so lets to the proper (and more
typesafe) upcasting.
Acked-by: Sam Ravnborg
Acked-by: Thomas Zimmermann
Signed-off-by: Daniel Vetter
Cc: Hans de Goede
LGTM:
Reviewed-by: Hans de Goede
Regards,
Hans
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
Doesn't apply to upstream kernels since a rather long time.
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Hans de Goede
LGTM:
Reviewed-by: Hans de Goede
Regards,
Hans
---
drivers/gpu/drm/vboxvideo/vbox_ttm.c | 12
Addressing one of the comments, recommending to extract platform
specific code from intel_can_enable_sagv as a preparation, before
we are going to add support for tgl+.
v2: - Removed whitespace
v3: - Removed premature debug and new cycle introduction(Ville)
- Added missing no active pipes
Since we depend upon RPS generating interrupts after evaluation
intervals to determine when to up/down clock the GPU, it is imperative
that we successfully enable interrupt generation! Verify that we do see
an interrupt if we keep the GPU busy for an entire EI.
Signed-off-by: Chris Wilson
---
== Series Details ==
Series: drm/i915: Always defer fenced work to the worker
URL : https://patchwork.freedesktop.org/series/75917/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17295_full
Summary
== Series Details ==
Series: drm/i915/selftests: Exercise basic RPS interrupt generation (rev5)
URL : https://patchwork.freedesktop.org/series/75966/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8301 -> Patchwork_17308
On Wed, Apr 15, 2020 at 07:28:18AM -0700, Sripada, Radhakrishna wrote:
> Hi Matt,
>
> > -Original Message-
> > From: Roper, Matthew D
> > Sent: Tuesday, April 14, 2020 11:40 AM
> > To: Sripada, Radhakrishna
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [PATCH] drm/i915/icl:
== Series Details ==
Series: drm/i915: Fix indirect context size calculation
URL : https://patchwork.freedesktop.org/series/75916/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17294_full
Summary
Since the introduction of 'soft-rc6', we aim to park the device quickly
and that results in frequent idling of the whole device. Currently upon
idling we free the batch buffer pool, and so this renders the cache
ineffective for many workloads. If we want to have an effective cache of
recently
== Series Details ==
Series: drm/i915/selftests: Exercise basic RPS interrupt generation (rev5)
URL : https://patchwork.freedesktop.org/series/75966/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING:
Lets have a unified way to handle SAGV changes,
espoecially considering the upcoming Gen12 changes.
Current "standard" way of doing this in commit_tail
is pre/post plane updates, when everything which
has to be forbidden and not supported in new config
has to be restricted before update and
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor
Add correspondent helpers to be able to get old/new bandwidth
global state object.
v2: - Fixed typo in function call
v3: - Changed new functions naming to use convention proposed
by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
v4: - Change function naming back to intel_atomic* pattern,
Flip the switch and enable SAGV support
for Gen12 also.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1ab466e4a0c6..dfe511ab2d3b 100644
---
That is a preparation patch before next one where we
introduce old_bw_state and a bunch of other changes
as well.
In a review comment it was suggested to split out
at least that renaming into a separate patch, what
is done here.
v2: Removed spurious space
Reviewed-by: Ville Syrjälä
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid
Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.
v2: Remove long lines
v3: Removed COLOR_PLANE enum references
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +-
Future platforms require per-crtc SAGV evaluation
and serializing global state when those are changed
from different commits.
v2: - Add has_sagv check to intel_crtc_can_enable_sagv
so that it sets bit in reject mask.
- Use bw_state in intel_pre/post_plane_enable_sagv
instead of
We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.
v2: - Extracted those changes into separate patch
(Ville Syrjälä)
v3: - Moved new PCode masks to another place from
PCode commands(Ville)
Addressing one of the comments, recommending to extract platform
specific code from intel_can_enable_sagv as a preparation, before
we are going to add support for tgl+.
v2: - Removed whitespace
v3: - Removed premature debug and new cycle introduction(Ville)
- Added missing no active pipes
Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.
v2, v3: Fix rebase conflict
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 38 -
1 file changed, 28 insertions(+), 10 deletions(-)
diff
For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.
So this accessor will give additional flexibility
to do that.
Currently this accessor is still simply working
as "pass-through" function. This will be
The poll() is proving unreliable, where our tests timeout without the
spinner being terminated. Let's try a blocking read instead!
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1676
Signed-off-by: Chris Wilson
Cc: "Dixit, Ashutosh"
---
lib/igt_dummyload.c | 12 ++--
1 file
== Series Details ==
Series: drm/i915/selftests: Exercise basic RPS interrupt generation (rev5)
URL : https://patchwork.freedesktop.org/series/75966/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ff4a038bdd9a drm/i915/selftests: Exercise basic RPS interrupt generation
-:46:
Hi Matt,
> -Original Message-
> From: Roper, Matthew D
> Sent: Tuesday, April 14, 2020 11:40 AM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/icl: Update forcewake firmware ranges
>
> On Mon, Apr 13, 2020 at 02:00:03AM -0700,
== Series Details ==
Series: series starting with [v4,1/3] drm/dp: DRM DP helper for reading Ignore
MSA from DPCD
URL : https://patchwork.freedesktop.org/series/75899/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8298_full -> Patchwork_17293_full
1 - 100 of 248 matches
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