Hi Dave & Daniel -
Pretty quiet still, but here's some cc: stable fixes.
(Well, one doesn't have the explicit stable tag, but the Fixes tag
points at a commit in v3.9...)
drm-intel-fixes-2021-01-07:
drm/i915 fixes for v5.11-rc3:
- Use per-connector PM QoS tracking for DP aux communication
-
On Wed, 09 Dec 2020, Imre Deak wrote:
> For an enabled DSC during HW readout the corresponding power reference
> is taken along the CRTC power domain references in
> get_crtc_power_domains(). Remove the incorrect get ref from the DSI
> encoder hook.
Does this fix [1] which is v5.11-rc2 on TGL
> -Original Message-
> From: Imre Deak
> Sent: Wednesday, January 6, 2021 9:33 PM
> To: Gupta, Anshuman
> Cc: intel-gfx@lists.freedesktop.org; Mason, Michael W
> ; Nikula, Jani ; Ville
> Syrjälä
> Subject: Re: [RFC v2] drm/i915/pps: Add PPS power domain
>
> On Wed, Jan 06, 2021 at
Hello,
I already have new patchset upstream for review, please review
https://patchwork.freedesktop.org/patch/412072/ .
Thanks,
Tejas
> -Original Message-
> From: Lyude Paul
> Sent: 06 January 2021 23:45
> To: Surendrakumar Upadhyay, TejaskumarX
> ; Roper, Matthew D
>
> Cc:
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Wrap our timer_list.expires
checking
URL : https://patchwork.freedesktop.org/series/85551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9551_full -> Patchwork_19271_full
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev19)
URL : https://patchwork.freedesktop.org/series/84620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9554 -> Patchwork_19276
Summary
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev19)
URL : https://patchwork.freedesktop.org/series/84620/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fbdd4e2e287d drm/i915/pxp: Introduce Intel PXP component
-:119:
== Series Details ==
Series: drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST
URL : https://patchwork.freedesktop.org/series/8/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9554 -> Patchwork_19275
Summary
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(defualt) session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
1 file changed, 8 insertions(+)
diff --git
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive. And Implement the funciton to set
the protected flag for gem context.
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 19 +--
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig |
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c |
PXP (Protected Xe Path) is an i915 component, available on
GEN12+ that helps to establish the hardware protected session
and manage the status of the alive software session, as well
as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 3 +-
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session
== Series Details ==
Series: drm/i915/selftests: Skip unstable timing measurements
URL : https://patchwork.freedesktop.org/series/85554/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9554 -> Patchwork_19274
Summary
---
From: Sean Paul
The HDCP 1.4 spec does not require the QUERY_STREAM_ENCRYPTION_STATUS
check, it was always a nice-to-have. After deploying this across various
devices, we've determined that some MST bridge chips do not properly
support this call for HDCP 1.4 (namely Synaptics and Realtek).
I
If any of the perf tests run into 0 time, not only are we liable to
divide by zero, but the result would be highly questionable.
Nevertheless, let's not have a div-by-zero error.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_memory_region.c | 3 +++
1 file changed, 3
== Series Details ==
Series: drm/i915/rkl: Add DP vswing programming tables (rev2)
URL : https://patchwork.freedesktop.org/series/85056/
State : failure
== Summary ==
Applying: drm/i915/rkl: Add DP vswing programming tables
error: patch fragment without header at line 16: @@ -1267,8 +1298,13
Reviewed-by: Swathi Dhanavanthri
-Original Message-
From: Matt Roper
Sent: Thursday, December 17, 2020 8:06 PM
To: intel-gfx@lists.freedesktop.org
Cc: Roper, Matthew D
Subject: [PATCH] drm/i915/rkl: Add DP vswing programming tables
The bspec has been updated with new vswing
Quoting Daniele Ceraolo Spurio (2021-01-06 17:21:16)
>
>
> On 1/5/2021 6:55 PM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2021-01-06 02:32:28)
> >>
> >> On 1/5/2021 4:58 PM, Chris Wilson wrote:
> >>> Quoting Daniele Ceraolo Spurio (2021-01-05 23:19:44)
> GuC owns the execlists
== Series Details ==
Series: drm/i915: Add support for Intel's eDP backlight controls (rev7)
URL : https://patchwork.freedesktop.org/series/81702/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9554 -> Patchwork_19272
On Wed, Jan 06, 2021 at 07:04:42PM +0100, Greg KH wrote:
> On Wed, Jan 06, 2021 at 07:53:01PM +0200, Imre Deak wrote:
> > Stable team, please backport the upstream commit
> >
> > 8f329967d596 ("drm/i915/tgl: Fix Combo PHY DPLL fractional divider for
> > 38.4MHz ref clock")
> >
> > to the v5.10
== Series Details ==
Series: drm/i915: Add support for Intel's eDP backlight controls (rev7)
URL : https://patchwork.freedesktop.org/series/81702/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1b13d103ba78 drm/i915: Keep track of pwm-related backlight hooks separately
-:593:
On Mon, 2021-01-04 at 04:40 +, Surendrakumar Upadhyay, TejaskumarX wrote:
>
>
> > -Original Message-
> > From: Matt Roper
> > Sent: 01 January 2021 02:32
> > To: Surendrakumar Upadhyay, TejaskumarX
> >
> > Cc: intel-gfx@lists.freedesktop.org; Pandey, Hariom
> >
> > Subject: Re:
On Wed, Jan 06, 2021 at 07:53:01PM +0200, Imre Deak wrote:
> Stable team, please backport the upstream commit
>
> 8f329967d596 ("drm/i915/tgl: Fix Combo PHY DPLL fractional divider for
> 38.4MHz ref clock")
>
> to the v5.10 stable kernel.
I see no such commit id in Linus's kernel :(
Stable team, please backport the upstream commit
8f329967d596 ("drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz
ref clock")
to the v5.10 stable kernel.
Thanks,
Imre
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
On Tue, Jan 05, 2021 at 05:50:41AM +, Matthew Wilcox wrote:
> On Tue, Dec 29, 2020 at 04:41:31PM +0200, Imre Deak wrote:
> > Hi,
> >
> > On Mon, Dec 21, 2020 at 04:07:58AM +, Matthew Wilcox wrote:
> > >
> > > At boot,
> > >
> > > [2.787995] [drm:lspcon_init [i915]] *ERROR* Failed to
On 1/5/2021 7:09 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-01-06 02:38:09)
On 1/5/2021 5:02 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-01-05 23:19:46)
Initialize all required entries from guc_set_default_submission, instead
of calling the execlists
On 1/5/2021 6:55 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-01-06 02:32:28)
On 1/5/2021 4:58 PM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2021-01-05 23:19:44)
GuC owns the execlists state and the context IDs used for submission, so
the status of the ports and
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Wrap our timer_list.expires
checking
URL : https://patchwork.freedesktop.org/series/85551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9551 -> Patchwork_19271
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Wrap our timer_list.expires
checking
URL : https://patchwork.freedesktop.org/series/85551/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: series starting with [1/4] drm/i915/selftests: Break out of the lrc
layout test after register mismatch
URL : https://patchwork.freedesktop.org/series/85548/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9549_full -> Patchwork_19269_full
In the next^W future patch, we remove the strict priority system and
continuously re-evaluate the relative priority of tasks. As such we need
to enable the timeslice whenever there is more than one context in the
pipeline. This simplifies the decision and removes some of the tweaks to
suppress
Refactor our timer_list.expires checking into its own timer_active()
helper.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_utils.c | 2 +-
drivers/gpu/drm/i915/i915_utils.h | 7 ++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git
Quoting Chris Wilson (2021-01-06 16:08:40)
> Quoting Tvrtko Ursulin (2021-01-06 15:57:49)
> >
> >
> > On 06/01/2021 12:39, Chris Wilson wrote:
> > > In the next^W future patch, we remove the strict priority system and
> > > continuously re-evaluate the relative priority of tasks. As such we need
Quoting Tvrtko Ursulin (2021-01-06 15:57:49)
>
>
> On 06/01/2021 12:39, Chris Wilson wrote:
> > In the next^W future patch, we remove the strict priority system and
> > continuously re-evaluate the relative priority of tasks. As such we need
> > to enable the timeslice whenever there is more
On Wed, Jan 06, 2021 at 10:04:38AM +0530, Anshuman Gupta wrote:
> It abstracts getting the AUX power domain in pps_lock under
> PPS power domain. This makes sure that the platforms which really
> requires AUX power in order to access PPS registers will get the
> reference to necessary power wells.
On 06/01/2021 12:39, Chris Wilson wrote:
In the next^W future patch, we remove the strict priority system and
continuously re-evaluate the relative priority of tasks. As such we need
to enable the timeslice whenever there is more than one context in the
pipeline. This simplifies the decision
On 06/01/2021 15:17, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-01-06 15:10:02)
On 06/01/2021 12:39, Chris Wilson wrote:
AFter detecting a register mismatch between the protocontext and the
image generated by HW, immediately break out of the double loop.
(Otherwise we end up a second
Quoting Tvrtko Ursulin (2021-01-06 15:10:02)
>
> On 06/01/2021 12:39, Chris Wilson wrote:
> > AFter detecting a register mismatch between the protocontext and the
> > image generated by HW, immediately break out of the double loop.
> > (Otherwise we end up a second configuing error message.)
>
>
On 06/01/2021 12:39, Chris Wilson wrote:
Use memset_io() on the iomem, and silence sparse as we copy from the
iomem to normal system pages.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_reset.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
On 06/01/2021 12:39, Chris Wilson wrote:
AFter detecting a register mismatch between the protocontext and the
image generated by HW, immediately break out of the double loop.
(Otherwise we end up a second configuing error message.)
s/configuing/confusing/?
No use of dumping all differences?
== Series Details ==
Series: series starting with [1/8] drm/i915/gt: Rearrange vlv workarounds
URL : https://patchwork.freedesktop.org/series/85549/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9549 -> Patchwork_19270
== Series Details ==
Series: series starting with [1/8] drm/i915/gt: Rearrange vlv workarounds
URL : https://patchwork.freedesktop.org/series/85549/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
The GFX_MODE is reset along with the engine, turning off ppGTT. We need
to re-enable it upon resume.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c| 9 -
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 13 ++---
2 files changed, 10
Push the sleeping stop_ring() out of the reset resume function to reset
prepare; we are not allowed to sleep in the former.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 97 +++
1 file changed, 36 insertions(+), 61 deletions(-)
diff --git
Take advantage of calling xcs_resume under a forcewake by using direct
mmio access. In particular, we can avoid the sleeping variants to allow
resume to be called from softirq context, required for engine resets.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 96
The engine resets selftests kick the tasklets, safe up until now as only
execlists supported engine resets.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 18 ++
drivers/gpu/drm/i915/gt/selftest_reset.c | 11 ---
2 files changed, 22
The benefit of only resetting a single engine is that we leave other
streams of userspace work intact across a hang; vital for process
isolation. We had wired up individual engine resets for gen6, but only
enabled it from gen8; now let's turn it on for the forgotten gen7. gen6
is still a mystery
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 122
1 file changed, 49 insertions(+), 73 deletions(-)
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 95 +++--
1 file changed, 51 insertions(+), 44 deletions(-)
In the legacy ringbuffer submission, we still had an open-coded version
of intel_engine_stop_cs() with one addition verification step. Transfer
that verification to intel_engine_stop_cs() itself, and call it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 15
== Series Details ==
Series: series starting with [1/4] drm/i915/selftests: Break out of the lrc
layout test after register mismatch
URL : https://patchwork.freedesktop.org/series/85548/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9549 -> Patchwork_19269
Hi,
I have an Intel NUC D54250WYK which no longer shuts down properly after
moving from 5.9.16 to 5.10.4, because systemd hangs. The kernel logs
make me beleive it is likely a locking issue in either DRM or ALSA or
both. Relevant messages which I could extract from the journal:
Jan 05 22:21:38
== Series Details ==
Series: series starting with [1/4] drm/i915/selftests: Break out of the lrc
layout test after register mismatch
URL : https://patchwork.freedesktop.org/series/85548/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used,
== Series Details ==
Series: series starting with [1/4] drm/i915/selftests: Break out of the lrc
layout test after register mismatch
URL : https://patchwork.freedesktop.org/series/85548/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
df520ae36315 drm/i915/selftests: Break out
In the next^W future patch, we remove the strict priority system and
continuously re-evaluate the relative priority of tasks. As such we need
to enable the timeslice whenever there is more than one context in the
pipeline. This simplifies the decision and removes some of the tweaks to
suppress
Use memset_io() on the iomem, and silence sparse as we copy from the
iomem to normal system pages.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_reset.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c
Before we mark the virtual engine as no longer inflight, flush any
ongoing signaling that may be using the ce->signal_link along the
previous breadcrumbs. On switch to a new physical engine, that link will
be inserted into the new set of breadcrumbs, causing confusion to an
ongoing iterator.
This
AFter detecting a register mismatch between the protocontext and the
image generated by HW, immediately break out of the double loop.
(Otherwise we end up a second configuing error message.)
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 10 ++
1 file changed,
drm-misc-next-2021-01-06:
drm-misc-next for v5.12:
Core Changes:
- Lots of drm documentation updates by Simor Ser.
- Require that each crtc has a unique primary plane.
- Add fixme that fbdev_generic_setup is confusing.
Driver Changes:
- Update addresses for TI display drivers maintainers.
- Make
Quoting Janusz Krzysztofik (2020-12-04 19:50:07)
> We may still be interested in results of a test even if it has tainted
> the kernel. On the other hand, we need to kill the test on taint if no
> other means of killing it on a jam is active.
>
> If abort on both kernel taint or a timeout is
== Series Details ==
Series: drm/i915/pps: Add PPS power domain (rev2)
URL : https://patchwork.freedesktop.org/series/85470/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9548_full -> Patchwork_19267_full
Summary
---
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