Am 04.02.21 um 19:38 schrieb Jason Gunthorpe:
On Thu, Feb 04, 2021 at 06:16:27PM +0100, Daniel Vetter wrote:
On Thu, Feb 4, 2021 at 5:13 PM Jason Gunthorpe wrote:
On Wed, Feb 03, 2021 at 10:19:48PM +0100, Daniel Vetter wrote:
tldr; DMA buffers aren't normal memory, expecting that you can use
> -Original Message-
> From: Imre Deak
> Sent: Thursday, February 4, 2021 11:58 PM
> To: Gupta, Anshuman
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/debugfs: HDCP capability enc NULL
> check
>
> On Fri, Jan 29, 2021 at 01:30:43PM +0530, Anshuman G
On Thu, Feb 4, 2021 at 9:59 PM Jason Gunthorpe wrote:
>
> On Thu, Feb 04, 2021 at 09:19:57PM +0100, Daniel Vetter wrote:
> > On Thu, Feb 4, 2021 at 9:09 PM Jason Gunthorpe wrote:
> > >
> > > On Thu, Feb 04, 2021 at 08:59:59PM +0100, Daniel Vetter wrote:
> > >
> > > > So I think just checking for
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/selftests: Restore previous
heartbeat interval
URL : https://patchwork.freedesktop.org/series/86727/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9733_full -> Patchwork_19596_full
===
== Series Details ==
Series: drm/i915/hdcp: Show connector hdcp capability
URL : https://patchwork.freedesktop.org/series/86740/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9736 -> Patchwork_19601
Summary
---
**SUC
On 04/02/2021 16:11, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-02-04 15:18:31)
On 01/02/2021 08:56, Chris Wilson wrote:
Whether a scheduler chooses to implement timeslicing is up to it, and
not an underlying property of the HW engine. The scheduler does depend
on the HW supporting pre
We emit a store on each GPU after loading the module to confirm the
basic liveness of command submission. Trim away some of the chaff.
Signed-off-by: Chris Wilson
Cc: Ramalingam C
---
tests/i915/i915_module_load.c | 146 ++
1 file changed, 58 insertions(+), 88 de
Get rid of the strange REGION_MAP encoding stuff and just use an
explicit class/instance pair for each region. This better matches our
future uAPI where all queryable regions are identified with a u16 class
and u16 instance.
v2: fix whitespace
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilso
In some future patches we will need to also support a stolen region
carved from device local memory, on platforms like DG1. To handle this
we can simply describe each in terms of its own memory class.
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_st
The heartbeat runs through a few phases that we expect to complete
within a certain number of heartbeat intervals. First we must submit the
heartbeat to the queue, and if the queue is occupied it may take a
couple of intervals before the heartbeat preempts the workload and is
submitted to HW. Once
On Thu, Feb 4, 2021 at 11:04 AM Andy Shevchenko
wrote:
>> Today's linux-next merge of the drivers-x86 tree got a conflict in:
>
> Thanks. I already asked Patrik yesterday day if DRM missed to pull an
> immutable tag I provided. I think they can pull and resolve conflicts
> themselves. Alternativ
On Fri, Feb 5, 2021 at 12:07 PM Andy Shevchenko
wrote:
>
> On Thu, Feb 4, 2021 at 11:04 AM Andy Shevchenko
> wrote:
> >> Today's linux-next merge of the drivers-x86 tree got a conflict in:
> >
> > Thanks. I already asked Patrik yesterday day if DRM missed to pull an
> > immutable tag I provided.
The heartbeat runs through a few phases that we expect to complete
within a certain number of heartbeat intervals. First we must submit the
heartbeat to the queue, and if the queue is occupied it may take a
couple of intervals before the heartbeat preempts the workload and is
submitted to HW. Once
Wait for the GPU to wake up from the semaphore before measuring the
time, so that we coordinate the sampling on both the CPU and GPU for
more accurate comparisons.
v2: Switch to local_irq_disable() as once suggested by Mika.
Reported-by: Bruce Chang
Signed-off-by: Chris Wilson
Cc: CQ Tang
Revi
On Fri, Feb 05, 2021 at 10:16:30AM +0200, Gupta, Anshuman wrote:
> > -Original Message-
> > From: Imre Deak
> > Sent: Thursday, February 4, 2021 11:58 PM
> > To: Gupta, Anshuman
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/debugfs: HDCP capability
> -Original Message-
> From: Imre Deak
> Sent: Friday, February 5, 2021 5:35 PM
> To: Gupta, Anshuman
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/debugfs: HDCP capability enc NULL
> check
>
> On Fri, Feb 05, 2021 at 10:16:30AM +0200, Gupta, Anshum
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: cleanup the region
class/instance encoding
URL : https://patchwork.freedesktop.org/series/86753/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9737 -> Patchwork_19602
gallium (iris) depends on os_same_file_description() to disambiguate
screens and so avoid importing the same screen fd twice as two distinct
entities (that share all the kernel resources, so actions on screen
affect the other and would cause random faiure). As they depend on it,
so must we. os_same
On Fri, Feb 5, 2021 at 12:14 PM Patrik Jakobsson
wrote:
>
> On Fri, Feb 5, 2021 at 12:07 PM Andy Shevchenko
> wrote:
> >
> > On Thu, Feb 4, 2021 at 11:04 AM Andy Shevchenko
> > wrote:
> > >> Today's linux-next merge of the drivers-x86 tree got a conflict in:
> > >
> > > Thanks. I already asked P
> -Original Message-
> From: Chris Wilson
> Sent: Friday, January 15, 2021 6:51 PM
> To: S, Saichandana ; intel-
> g...@lists.freedesktop.org
> Cc: Nikula, Jani ; S, Saichandana
>
> Subject: Re: [Intel-gfx] [PATCH v4] drm/i915/debugfs : PM_REQ and
> PM_RES registers
>
> Quoting Saicha
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting S, Saichandana (2021-02-05 13:05:20)
>
>
> > -Original Message-
> > From: Chris Wilson
> > Sent: Friday, January 15, 2021 6:51 PM
> > To: S, Saichandana ; intel-
> > g...@lists.freedesktop.org
> > Cc: Nikula, Jani ; S, Saichandana
> >
> > Subject: Re: [Intel-gfx] [PATCH v4] drm/
== Series Details ==
Series: drm/i915/icl, tgl: whitelist COMMON_SLICE_CHICKEN3 register
URL : https://patchwork.freedesktop.org/series/86733/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9735_full -> Patchwork_19598_full
== Series Details ==
Series: drm/i915/gt: Ratelimit heartbeat completion probing (rev5)
URL : https://patchwork.freedesktop.org/series/86665/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9737 -> Patchwork_19603
Summary
---
On Thu, 2021-02-04 at 15:40 +0200, Gwan-gyeong Mun wrote:
> It is a preliminary work for supporting multiple EDP PSR and
> DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> supportable PSR.
> And this moves and renames the i915_psr structure of drm_i915_private's to
> intel_dp's
On Fri, 2021-02-05 at 07:40 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display: support ddr5 mem types
> URL : https://patchwork.freedesktop.org/series/86726/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9732_full -> Patchwork_19595_full
> =
Quoting Sagar Ghuge (2021-02-05 00:33:10)
> Adding this register to whitelist will allow UMD to toggle State Cache
> Perf fix disable chicken bit.
>
>"If this bit is enabled, RCC uses BTP+BTI as address tag in its state
>cache instead of BTI only"
>
> which will lead to dropping unnecessa
On Fri, 2021-02-05 at 03:08 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v15,1/2] drm/i915/display: Support PSR Multiple
> Instances
> URL : https://patchwork.freedesktop.org/series/86701/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI
On Fri, 2021-02-05 at 04:53 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display: Remove PSR2 on JSL and EHL
> URL : https://patchwork.freedesktop.org/series/86714/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9732_full -> Patchwork_19592_full
tldr; DMA buffers aren't normal memory, expecting that you can use
them like that (like calling get_user_pages works, or that they're
accounting like any other normal memory) cannot be guaranteed.
Since some userspace only runs on integrated devices, where all
buffers are actually all resident sys
On Fri, 2021-02-05 at 04:00 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Make psr_safest_params and enable_psr2_sel_fetch parameters
> read only
> URL : https://patchwork.freedesktop.org/series/86710/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI
Am 05.02.21 um 14:41 schrieb Daniel Vetter:
tldr; DMA buffers aren't normal memory, expecting that you can use
them like that (like calling get_user_pages works, or that they're
accounting like any other normal memory) cannot be guaranteed.
Since some userspace only runs on integrated devices, w
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Thursday, February 4, 2021 4:09 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Index min_{cdclk, voltage_level}[]
> with pipe
>
> From: Ville Syrjälä
>
> min_cdclk[] and
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Thursday, February 4, 2021 4:09 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Use intel_hdmi_port_clock() more
>
> From: Ville Syrjälä
>
> Replace the hand rolled intel_
On Thu, 04 Feb 2021, Jani Nikula wrote:
> From: Dave Airlie
>
> Daniel asked for this, but it's a bit messy and I'm not sure
> how best to clean it up yet.
Thanks, pushed.
BR,
Jani.
>
> Signed-off-by: Dave Airlie
> [Jani: also moved fdi buf trans to intel_fdi.c.]
> Reviewed-by: Ville Syrjälä
On Fri, Feb 5, 2021 at 3:05 PM Daniel Vetter wrote:
> On Fri, Feb 5, 2021 at 12:14 PM Patrik Jakobsson
> wrote:
> >
> > On Fri, Feb 5, 2021 at 12:07 PM Andy Shevchenko
> > wrote:
> > >
> > > On Thu, Feb 4, 2021 at 11:04 AM Andy Shevchenko
> > > wrote:
> > > >> Today's linux-next merge of the dr
The heartbeat runs through a few phases that we expect to complete
within a certain number of heartbeat intervals. First we must submit the
heartbeat to the queue, and if the queue is occupied it may take a
couple of intervals before the heartbeat preempts the workload and is
submitted to HW. Once
The heartbeat runs through a few phases that we expect to complete
within a certain number of heartbeat intervals. First we must submit the
heartbeat to the queue, and if the queue is occupied it may take a
couple of intervals before the heartbeat preempts the workload and is
submitted to HW. Once
From: Dave Airlie
Daniel suggested this should move here.
v2: move vrr code.
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crtc.c | 241
drivers/gpu/drm/i915/display/intel_sprite.c | 238 ---
Rebase of [1], which wen't stale in less than a day, but managed to push the
first two. Progress! This also addresses Ville's review comments, I hope.
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/86723/
Dave Airlie (8):
drm/i915: migrate skl planes code new file (v5)
drm/i915: move
From: Dave Airlie
There is no need for this to be out of line.
Reviewed-by: Ville Syrjälä
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 9 -
drivers/gpu/drm/i915/display/intel_display.h | 1 -
drivers/gpu/drm/i915
From: Dave Airlie
This just cleans these up a bit.
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c| 7 +++
drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++--
2 files changed, 5 insertions(+
From: Dave Airlie
This moves the older i9xx/vlv/chv enable/disable to dpll file.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 512 ---
drivers/gpu/drm/i915/display/intel_display.h | 3 -
From: Dave Airlie
Migrate this code out like the skylake code.
Signed-off-by: Dave Airlie
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 119 +++
drivers/gpu/drm/i915/display/i9xx_plane.h| 4 +
drivers/gpu/drm/i9
From: Dave Airlie
This just migrates the hsw+ code to a better place.
Signed-off-by: Dave Airlie
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 219 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 223 ++
drivers/gpu/drm/i915/d
From: Dave Airlie
This moves the code from various places and consolidates it
into one new file.
v2:
- rename skl_program_plane -> skl_program_plane_scaler (Ville)
- also move skl_pfit_enable, and consequently make some skl_scaler_*
functions static to skl_scaler.c (Ville)
Signed-off-by: Dave
On Fri, Feb 05, 2021 at 04:48:42PM +0200, Jani Nikula wrote:
> From: Dave Airlie
>
> This moves the code from various places and consolidates it
> into one new file.
>
> v2:
> - rename skl_program_plane -> skl_program_plane_scaler (Ville)
> - also move skl_pfit_enable, and consequently make some
On Fri, Feb 05, 2021 at 04:48:43PM +0200, Jani Nikula wrote:
> From: Dave Airlie
>
> This just migrates the hsw+ code to a better place.
>
> Signed-off-by: Dave Airlie
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 219 +
> drivers/gpu/drm
== Series Details ==
Series: drm/i915: Add link rate and lane count to i915_display_info
URL : https://patchwork.freedesktop.org/series/86738/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9735_full -> Patchwork_19600_full
On Thu, Feb 04, 2021 at 05:55:28PM +0200, Ville Syrjälä wrote:
> On Thu, Feb 04, 2021 at 04:32:16PM +0100, Daniel Vetter wrote:
> > On Thu, Feb 04, 2021 at 04:04:00AM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > drm_vblank_restore() exists because certain power saving states
Right now CI is blacklisting module reload, so we need to be able to
enable PSR2 selective fetch in run time to test this feature before
enable it by default.
Changes in IGT will also be needed.
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_disp
On Fri, Feb 05, 2021 at 01:03:07PM +, Chris Wilson wrote:
> gallium (iris) depends on os_same_file_description() to disambiguate
> screens and so avoid importing the same screen fd twice as two distinct
> entities (that share all the kernel resources, so actions on screen
> affect the other and
On Fri, Feb 05, 2021 at 04:58:32PM +0100, Daniel Vetter wrote:
> On Fri, Feb 05, 2021 at 01:03:07PM +, Chris Wilson wrote:
> > gallium (iris) depends on os_same_file_description() to disambiguate
> > screens and so avoid importing the same screen fd twice as two distinct
> > entities (that shar
Am Freitag, dem 05.02.2021 um 16:59 +0100 schrieb Daniel Vetter:
> On Fri, Feb 05, 2021 at 04:58:32PM +0100, Daniel Vetter wrote:
> > On Fri, Feb 05, 2021 at 01:03:07PM +, Chris Wilson wrote:
> > > gallium (iris) depends on os_same_file_description() to disambiguate
> > > screens and so avoid i
On Fri, Feb 05, 2021 at 04:46:27PM +0100, Daniel Vetter wrote:
> On Thu, Feb 04, 2021 at 05:55:28PM +0200, Ville Syrjälä wrote:
> > On Thu, Feb 04, 2021 at 04:32:16PM +0100, Daniel Vetter wrote:
> > > On Thu, Feb 04, 2021 at 04:04:00AM +0200, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > >
Userspace has discovered the functionality offered by SYS_kcmp and has
started to depend upon it. In particular, Mesa uses SYS_kcmp for
os_same_file_description() in order to identify when two fd (e.g. device
or dmabuf) point to the same struct file. Since they depend on it for
core functionality,
Am Freitag, dem 05.02.2021 um 16:37 + schrieb Chris Wilson:
> Userspace has discovered the functionality offered by SYS_kcmp and has
> started to depend upon it. In particular, Mesa uses SYS_kcmp for
> os_same_file_description() in order to identify when two fd (e.g. device
> or dmabuf) point t
== Series Details ==
Series: drm/i915/selftest: Synchronise with the GPU timestamp (rev2)
URL : https://patchwork.freedesktop.org/series/86731/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9739 -> Patchwork_19604
Summary
-
On 2021-02-05 at 10:10:05 +, Chris Wilson wrote:
> We emit a store on each GPU after loading the module to confirm the
> basic liveness of command submission. Trim away some of the chaff.
>
> Signed-off-by: Chris Wilson
> Cc: Ramalingam C
Looks good to me
Reviewed-by: Ramalingam C
> ---
>
We check for idle during debug prints and other debugging actions.
Simplify the flow by not touching execlists state.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --gi
Put all the scheduler initialisation code for execlists into a common
routine. This is to reduce code movement later.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 26 ---
1 file changed, 16 insertions(+), 10 deletion
== Series Details ==
Series: drm/i915: Autoselect CONFIG_CHECKPOINT_RESTORE for SYS_kcmp
URL : https://patchwork.freedesktop.org/series/86759/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9739 -> Patchwork_19605
Summary
--
== Series Details ==
Series: drm/i915/hdcp: Show connector hdcp capability
URL : https://patchwork.freedesktop.org/series/86740/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9736_full -> Patchwork_19601_full
Summary
--
On Fri, Feb 05, 2021 at 04:37:52PM +, Chris Wilson wrote:
> Userspace has discovered the functionality offered by SYS_kcmp and has
> started to depend upon it. In particular, Mesa uses SYS_kcmp for
> os_same_file_description() in order to identify when two fd (e.g. device
> or dmabuf) point to
On 2/5/21 5:33 AM, Chris Wilson wrote:
> Quoting Sagar Ghuge (2021-02-05 00:33:10)
>> Adding this register to whitelist will allow UMD to toggle State Cache
>> Perf fix disable chicken bit.
>>
>>"If this bit is enabled, RCC uses BTP+BTI as address tag in its state
>>cache instead of BTI o
Link rate and lane count information are more easier and faster to check in
i915_display_info
than checking kernel logs for people not familiar with i915 in the following
scenarios:
* Debugging DP tunnel bandwidth usage in Thunderbolt driver.
* In USB4 certification, it is a requirement to know w
== Series Details ==
Series: RFC: dma-buf: Require VM_SPECIAL vma for mmap (rev2)
URL : https://patchwork.freedesktop.org/series/86667/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a259cff180fc RFC: dma-buf: Require VM_PFNMAP vma for mmap
-:34: WARNING:TYPO_SPELLING: 'entires'
/linux.git
2ab38c17aac10bf55ab3efde4c4db3893d8691d2
config: powerpc-randconfig-r023-20210205 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
c9439ca36342fb6013187d0a69aef92736951476)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com
/linux.git
2ab38c17aac10bf55ab3efde4c4db3893d8691d2
config: i386-randconfig-s002-20210205 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-215-g0fb77bb6-dirty
#
https://github.com/0day-ci/li
== Series Details ==
Series: RFC: dma-buf: Require VM_SPECIAL vma for mmap (rev2)
URL : https://patchwork.freedesktop.org/series/86667/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9740 -> Patchwork_19606
Summary
---
On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote:
> DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> Do not read the registers if DPCD rev < 1.4.
>
> Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/2868
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/
On Thu, Feb 04, 2021 at 12:18:41PM +0530, Ankit Nautiyal wrote:
> Currently the FRL training mode (Concurrent, Sequential) and
> training type (Normal, Extended) are not defined properly and
> are passed as bool values in drm_helpers for pcon
> configuration for FRL training.
>
> This patch:
> -De
On Thu, Feb 04, 2021 at 12:18:42PM +0530, Ankit Nautiyal wrote:
> Remove code for resetting frl related members from intel_disable_dp, as
> this is not applicable for older platforms.
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 2 --
> 1 file changed, 2 de
On Fri, Feb 05, 2021 at 09:58:07PM +0200, Ville Syrjälä wrote:
> On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote:
> > DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> > Do not read the registers if DPCD rev < 1.4.
> >
> > Fixes: https://gitlab.freedesktop.org/d
On Fri, Feb 05, 2021 at 12:07:41PM -0800, Navare, Manasi wrote:
> On Fri, Feb 05, 2021 at 09:58:07PM +0200, Ville Syrjälä wrote:
> > On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote:
> > > DP-HDMI2.1 PCON has DSC encoder caps defined in registers 0x92-0x9E.
> > > Do not read the regis
On Fri, Feb 05, 2021 at 10:06:48PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 05, 2021 at 12:07:41PM -0800, Navare, Manasi wrote:
> > On Fri, Feb 05, 2021 at 09:58:07PM +0200, Ville Syrjälä wrote:
> > > On Thu, Feb 04, 2021 at 12:18:40PM +0530, Ankit Nautiyal wrote:
> > > > DP-HDMI2.1 PCON has DSC e
On Fri, Feb 05, 2021 at 11:09:36AM -0800, Khaled Almahallawy wrote:
> Link rate and lane count information are more easier and faster to check in
> i915_display_info
> than checking kernel logs for people not familiar with i915 in the following
> scenarios:
> * Debugging DP tunnel bandwidth usage
From: Ville Syrjälä
We tend to use output_format!=RGB as a shorthand for YCbCr, but
this fails if we have a disabled crtc where output_format==INVALID.
We're now getting some fail from intel_color_check() when we have:
hw.enable==false
hw.ctm!=NULL
output_format==INVALID
Let's avoid that by t
== Series Details ==
Series: drm/i915/gt: Ratelimit heartbeat completion probing (rev7)
URL : https://patchwork.freedesktop.org/series/86665/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9740 -> Patchwork_19607
Summary
---
On Mon, Feb 01, 2021 at 11:02:28PM +0800, Lee Shawn C wrote:
> According to Bspec #20124, max link rate table for DP was updated
> at BDB version 230. Max link rate can support upto UHBR.
>
> After migrate to BDB v230, the definition for LBR, HBR2 and HBR3
> were changed. For backward compatibilit
== Series Details ==
Series: drm/i915: refactor intel_display.c + a bit more (rev2)
URL : https://patchwork.freedesktop.org/series/86723/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2685c66ddd72 drm/i915: migrate skl planes code new file (v5)
-:2738: WARNING:FILE_PATH_CHANGES
== Series Details ==
Series: drm/i915: refactor intel_display.c + a bit more (rev2)
URL : https://patchwork.freedesktop.org/series/86723/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gp
On Fri, Feb 05, 2021 at 05:09:14PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 05, 2021 at 04:48:43PM +0200, Jani Nikula wrote:
> > From: Dave Airlie
> >
> > This just migrates the hsw+ code to a better place.
> >
> > Signed-off-by: Dave Airlie
> > Signed-off-by: Jani Nikula
> > ---
> > drivers
On Fri, Feb 5, 2021 at 7:37 PM Kees Cook wrote:
>
> On Fri, Feb 05, 2021 at 04:37:52PM +, Chris Wilson wrote:
> > Userspace has discovered the functionality offered by SYS_kcmp and has
> > started to depend upon it. In particular, Mesa uses SYS_kcmp for
> > os_same_file_description() in order
== Series Details ==
Series: drm/i915: refactor intel_display.c + a bit more (rev2)
URL : https://patchwork.freedesktop.org/series/86723/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9740 -> Patchwork_19608
Summary
---
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: cleanup the region
class/instance encoding
URL : https://patchwork.freedesktop.org/series/86753/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9737_full -> Patchwork_19602_full
==
Userspace has discovered the functionality offered by SYS_kcmp and has
started to depend upon it. In particular, Mesa uses SYS_kcmp for
os_same_file_description() in order to identify when two fd (e.g. device
or dmabuf) point to the same struct file. Since they depend on it for
core functionality,
The subject should of course be changed, as it is no longer being
enabled by default.
Something like
kcmp: Support selection of SYS_kcmp without CHECKPOINT_RESTORE
Quoting Chris Wilson (2021-02-05 21:06:10)
> Userspace has discovered the functionality offered by SYS_kcmp and has
> started to dep
On Fri, Feb 05, 2021 at 06:24:08PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 05, 2021 at 04:46:27PM +0100, Daniel Vetter wrote:
> > On Thu, Feb 04, 2021 at 05:55:28PM +0200, Ville Syrjälä wrote:
> > > On Thu, Feb 04, 2021 at 04:32:16PM +0100, Daniel Vetter wrote:
> > > > On Thu, Feb 04, 2021 at 04:
On Fri, Feb 05, 2021 at 09:16:01PM +, Chris Wilson wrote:
> The subject should of course be changed, as it is no longer being
> enabled by default.
"default n" is redundant. I thought Daniel said CONFIG_DRM needed to
"select" it too, though? Otherwise, yeah, this looks good. Was the
export due
Quoting Kees Cook (2021-02-05 21:20:33)
> On Fri, Feb 05, 2021 at 09:16:01PM +, Chris Wilson wrote:
> > The subject should of course be changed, as it is no longer being
> > enabled by default.
>
> "default n" is redundant.
I thought being explicit would be preferred. There are a few other
de
== Series Details ==
Series: drm/i915/display: Allow PSR2 selective fetch to be enabled at run-time
URL : https://patchwork.freedesktop.org/series/86773/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9740 -> Patchwork_19609
From: Ville Syrjälä
Sorry for spamming the same series again and again.
v2 still had some issues around FDI, and to fix those
I had to stick a fresh patch to the start of the series.
Hopefully it's now solid.
I have a few more patches already cooked up on top to
clean up the readout side too. Bu
From: Ville Syrjälä
The current code dealing with the clock routing for DDI encoders
is a maintenance nightmare. Let's start cleaning it up by allowing
the encoder to provide vfuncs for enablign/disabling the clock.
We leave them initially unimplemented, falling back to the old
if-else approach.
From: Ville Syrjälä
We want to put all DDI clock routing code into one place.
Unify the FDI enable sequence to use the standard function
instead of hand rolling its own. The disable sequence already
uses the normal thing.
Cc: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i9
From: Ville Syrjälä
Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}()
and put it into the new encoder .{enable,disable}_clock() vfuncs.
v2: s/dev_priv/i915/ (Lucas)
v3: Deal with FDI
Reviewed-by: Lucas De Marchi #v2
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/
From: Ville Syrjälä
Extract the DDI clock routing clode for skl/derivatives
into the new encoder vfuncs.
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 53 +---
1 file changed, 38 inser
From: Ville Syrjälä
Replace dg1_{map,unmap}_plls_to_ports() with the appropriate
encoder vfuncs. And let's relocate the disable function next to
the enable function while at it.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 43 +++
From: Ville Syrjälä
Extract the DDI clock routing for CNL into the new vfuncs.
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 62
1 file changed, 42 insertions(+), 20 deletions(-)
From: Ville Syrjälä
The DDI clock routing programming is riddled with shared
registers, forcing us to do a lot of RMW. Switch over to
intel_de_rmw() to make that a bit less obnoxious.
Reviewed-by: Lucas De Marchi
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 77 +
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