We've seen recent regression with host and windows VM running
simultaneously that cause gpu hang or even crash. Finally bisect to
58586680ffad ("drm/i915: Disable atomics in L3 for gen9"), which seems
cached atomics behavior difference caused regression issue.
This trys to add new scratch register
On Fri, 16 Jul 2021 at 21:07, Maarten Lankhorst
wrote:
>
> Hi Dave & Daniel,
>
> Lots of stuff this time around.
>
> Enjoy!
I've pulled this but there is an outstanding warning
/home/airlied/devel/kernel/dim/src/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c:
In function ‘hibmc_unload’:
/home/a
== Series Details ==
Series: Nuke legacy hw_id
URL : https://patchwork.freedesktop.org/series/92797/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10359_full -> Patchwork_20660_full
Summary
---
**SUCCESS**
No regr
On Tue, Jul 20, 2021 at 04:01:27PM -0600, Alex Williamson wrote:
> On Tue, 20 Jul 2021 14:42:48 -0300
> Jason Gunthorpe wrote:
>
> > Compared to mbochs_remove() two cases are missing from the
> > vfio_register_group_dev() unwind. Add them in.
> >
> > Fixes: 681c1615f891 ("vfio/mbochs: Convert to
On 2021.07.16 18:41:38 +0800, Xiyu Yang wrote:
> refcount_t type and corresponding API can protect refcounters from
> accidental underflow and overflow and further use-after-free situations
>
Thanks for the patch. Is there any specific problem you run with current code?
Any shadow ppgtt error?
>
On 7/20/2021 15:39, Matthew Brost wrote:
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
v2:
(Daniel Vetter)
- Use msleep_interruptible rather than cond_resched in busy loop
(Michal)
- Remove C++ style comment
v3:
(Matthew Brost
On 7/10/2021 11:41 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
This feature hands over the control of HW RC6 to the GUC.
GUC decides when to put HW into RC6 based on it's internal
busyness algorithms.
GUCRC needs GUC submission to be enabled, and only
supported
On 7/10/2021 11:29 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
Tests that exercise the slpc get/set frequency interfaces.
Clamp_max will set max frequency to multiple levels and check
that slpc requests frequency lower than or equal to it.
Clamp_min will set mi
== Series Details ==
Series: Nuke legacy hw_id
URL : https://patchwork.freedesktop.org/series/92797/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10359 -> Patchwork_20660
Summary
---
**SUCCESS**
No regressions fo
gen8_clear_engine_error_register() is actually not used by
GRAPHICS_VER >= 8, since for those we are using another register that is
not engine-dependent. Fix the platform prefix, to make clear we are not
using any GEN6_RING_FAULT_REG_* one GRAPHICS_VER >= 8.
Signed-off-by: Lucas De Marchi
---
dr
== Series Details ==
Series: Nuke legacy hw_id
URL : https://patchwork.freedesktop.org/series/92797/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function
parameter 'jump_whitelist' description in 'in
On 7/20/2021 15:39, Matthew Brost wrote:
Implement GuC submission tasklet for new interface. The new GuC
interface uses H2G to submit contexts to the GuC. Since H2G use a single
channel, a single tasklet is used for the submission path.
Also the per engine interrupt handler has been updated to d
== Series Details ==
Series: Series to merge a subset of GuC submission
URL : https://patchwork.freedesktop.org/series/92791/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10358_full -> Patchwork_20659_full
Summary
---
This is only used by GRAPHICS_VER == 6 and GRAPHICS_VER == 7. All other
recent platforms do not depend on this field, so it doesn't make much
sense to keep it generic like that. Instead, just do a mapping from
engine class to HW ID in the single place that is needed.
Signed-off-by: Lucas De Marchi
Motivated by my review in
https://patchwork.freedesktop.org/patch/443857/?series=92135&rev=5 I
went to look why we needed the additional hw_id fields. It turns out we
don't, but we kept adding new IDs to keep it consistent. Now that with
the extra media engines we would just leave than zero'ed, let
On Tue, Jul 20, 2021 at 04:40:52PM -0700, John Harrison wrote:
On 7/20/2021 16:03, Lucas De Marchi wrote:
On Tue, Jul 13, 2021 at 08:14:56PM -0700, Matt Roper wrote:
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the basic
definitions for them.
v2:
- Re-orde
On Tue, 2021-07-20 at 12:48 -0700, Lucas De Marchi wrote:
> On Fri, Jun 25, 2021 at 04:55:59PM -0700, Jose Souza wrote:
> > Implements changes around PSR for alderlake-P:
> >
> > - EDP_SU_TRACK_ENABLE was removed and bit 30 now has other function
> > - Some bits of PSR2_MAN_TRK_CTL moved and SF_PA
On 7/20/2021 16:03, Lucas De Marchi wrote:
On Tue, Jul 13, 2021 at 08:14:56PM -0700, Matt Roper wrote:
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the basic
definitions for them.
v2:
- Re-order intel_gt_info and intel_device_info slightly to avoid
unnece
On 7/10/2021 11:20 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
Update the get/set min/max freq hooks to work for
slpc case as well. Consolidate helpers for requested/min/max
frequency get/set to intel_rps where the proper action can
be taken depending on whether
We kept adding new engines and for that increasing hw_id unnecessarily:
it's not used since GRAPHICS_VER == 8. Prepend "gen6" to the field and
try to pack it in the structs to give a hint this field is actually not
used in recent platforms.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915
The engine hw_id is only used by RING_FAULT_REG(), which is not used
since GRAPHICS_VER == 8. We tend to keep adding new defines just to be
consistent, but let's try to remove them and let them defined to 0 when
not used.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_engine_cs
On 7/10/2021 11:15 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
Cache rp0, rp1 and rpn platform limits into slpc structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland. Thes
On Tue, Jul 13, 2021 at 08:14:56PM -0700, Matt Roper wrote:
From: John Harrison
Xe_HP can have a lot of extra media engines. This patch adds the basic
definitions for them.
v2:
- Re-order intel_gt_info and intel_device_info slightly to avoid
unnecessary padding now that we've increased the s
On Tue, 20 Jul 2021 19:49:55 -0300
Jason Gunthorpe wrote:
> On Tue, Jul 20, 2021 at 04:01:27PM -0600, Alex Williamson wrote:
> > On Tue, 20 Jul 2021 14:42:48 -0300
> > Jason Gunthorpe wrote:
> >
> > > Compared to mbochs_remove() two cases are missing from the
> > > vfio_register_group_dev() u
== Series Details ==
Series: Series to merge a subset of GuC submission
URL : https://patchwork.freedesktop.org/series/92791/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10358 -> Patchwork_20659
Summary
---
**SUCCE
On 7/10/2021 11:08 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
This prints out relevant SLPC info from the SLPC shared structure.
We will send a h2g message which forces SLPC to update the
shared data structure with latest information before reading it.
Signed
== Series Details ==
Series: Series to merge a subset of GuC submission
URL : https://patchwork.freedesktop.org/series/92791/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/i915_cmd_parser.c:1436: warning: Excess function
parameter 'jump_whit
== Series Details ==
Series: Series to merge a subset of GuC submission
URL : https://patchwork.freedesktop.org/series/92791/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/g
== Series Details ==
Series: Series to merge a subset of GuC submission
URL : https://patchwork.freedesktop.org/series/92791/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ec53f1834fea drm/i915/guc: Add new GuC interface defines and structures
-:99: WARNING:BLOCK_COMMENT_STYLE:
== Series Details ==
Series: Provide core infrastructure for managing open/release (rev5)
URL : https://patchwork.freedesktop.org/series/92556/
State : failure
== Summary ==
Applying: vfio/samples: Remove module get/put
Applying: vfio/mbochs: Fix missing error unwind in mbochs_probe()
Applying
When running the GuC the GPU can't be considered idle if the GuC still
has contexts pinned. As such, a call has been added in
intel_gt_wait_for_idle to idle the UC and in turn the GuC by waiting for
the number of unpinned contexts to go to zero.
v2: rtimeout -> remaining_timeout
v3: Drop unnecessa
Add trace point for GuC submit. Extended existing request trace points
to include submit fence value,, guc_id, and ring tail value.
v2: Fix white space alignment in i915_request_add trace point
v3: Delete dep_from , dep_to (Tvrtko)
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Joh
Extend the deregistration context fence to fence whne a GuC context has
scheduling disable pending.
v2:
(John H)
- Update comment why we check the pin count within spin lock
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submi
Update GuC debugfs to support the new GuC structures.
v2:
(John Harrison)
- Remove intel_lrc_reg.h include from i915_debugfs.c
(Michal)
- Rename GuC debugfs functions
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/inte
If two requests are on the same ring, they are explicitly ordered by the
HW. So, a submission fence is sufficient to ensure ordering when using
the new GuC submission interface. Conversely, if two requests share a
timeline and are on the same physical engine but different context this
doesn't ensur
Semaphores are an optimization and not required for basic GuC submission
to work properly. Disable until we have time to do the implementation to
enable semaphores and tune them for performance. Also long direction is
just to delete semaphores from the i915 so another reason to not enable
these for
Add intel_context tracing. These trace points are particular helpful
when debugging the GuC firmware and can be enabled via
CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS kernel config option.
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_co
Ensure G2H response has space in the buffer before sending H2G CTB as
the GuC can't handle any backpressure on the G2H interface.
v2:
(Matthew)
- s/INTEL_GUC_SEND/INTEL_GUC_CT_SEND
v3:
(Matthew)
- Add G2H credit accounting to blocking path, add g2h_release_space
helper
(John H)
- CTB_
Disable preempt busywait when using GuC scheduling. This isn't needed as
the GuC controls preemption when scheduling.
v2:
(John H):
- Fix commit message
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 --
1 file
Sometimes during context pinning a context with the same guc_id is
registered with the GuC. In this a case deregister must be done before
the context can be registered. A fence is inserted on all requests while
the deregister is in flight. Once the G2H is received indicating the
deregistration is c
Add new GuC interface defines and structures while maintaining old ones
in parallel.
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 14 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 41 +++
Disable engine barriers for unpinning with GuC. This feature isn't
needed with the GuC as it disables context scheduling before unpinning
which guarantees the HW will not reference the context. Hence it is
not necessary to defer unpinning until a kernel context request
completes on each engine in t
With GuC scheduling, it isn't safe to unpin a context while scheduling
is enabled for that context as the GuC may touch some of the pinned
state (e.g. LRC). To ensure scheduling isn't enabled when an unpin is
done, a call back is added to intel_context_unpin when pin count == 1
to disable schedulin
Add bypass tasklet submission path to GuC. The tasklet is only used if H2G
channel has backpresure.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++
1 file changed, 29 insertions(+), 8 deletions(-)
diff --git a/
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
v2:
(Daniel Vetter)
- Use msleep_interruptible rather than cond_resched in busy loop
(Michal)
- Remove C++ style comment
v3:
(Matthew Brost)
- Drop GUC_ID_START
(John Harrison)
- Fix
Remove old GuC stage descriptor, add LRC descriptor which will be used
by the new GuC interface implemented in this patch series.
v2:
(John Harrison)
- s/lrc/LRC/g
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h|
The first 18 patches [1] are basically ready to merge - only 3 are
missing RBs but all issues are mostly nits and have been address.
Hopefully by the time CI returns we can merge these.
Signed-off-by: Matthew Brost
[1] https://patchwork.freedesktop.org/series/91840/
Matthew Brost (18):
drm/i
Implement GuC submission tasklet for new interface. The new GuC
interface uses H2G to submit contexts to the GuC. Since H2G use a single
channel, a single tasklet is used for the submission path.
Also the per engine interrupt handler has been updated to disable the
rescheduling of the physical eng
Add LRC descriptor context lookup array which can resolve the
intel_context from the LRC descriptor index. In addition to lookup, it
can determine if the LRC descriptor context is currently registered with
the GuC by checking if an entry for a descriptor index is present.
Future patches in the seri
On 7/10/2021 10:52 AM, Michal Wajdeczko wrote:
On 10.07.2021 03:20, Vinay Belgaumkar wrote:
Add helpers to read the min/max frequency being used
by SLPC. This is done by send a h2g command which forces
s/h2g/H2G
done.
SLPC to update the shared data struct which can then be
read.
Si
On Mon, Jul 19, 2021 at 3:18 AM Matthew Auld
wrote:
>
> On Fri, 16 Jul 2021 at 15:14, Jason Ekstrand wrote:
> >
> > Since we don't allow changing the set of regions after creation, we can
> > make ext_set_placements() build up the region set directly in the
> > create_ext and assign it to the obj
On Tue, Jul 13, 2021 at 08:15:02PM -0700, Matt Roper wrote:
> From: Prathap Kumar Valsan
>
> The layout of some engine contexts has changed on Xe_HP. Define the new
> offsets.
>
> Bspec: 45585, 46256
> Signed-off-by: Prathap Kumar Valsan
> Signed-off-by: Ramalingam C
> Signed-off-by: Venkata
On Tue, Jul 20, 2021 at 4:35 AM Matthew Auld
wrote:
>
> On Thu, 15 Jul 2021 at 23:39, Jason Ekstrand wrote:
> >
> > Instead of hand-rolling the same three calls in each function, pull them
> > into an i915_gem_object_create_user helper. Apart from re-ordering of
> > the placements array ENOMEM c
On Tue, 20 Jul 2021 14:42:48 -0300
Jason Gunthorpe wrote:
> Compared to mbochs_remove() two cases are missing from the
> vfio_register_group_dev() unwind. Add them in.
>
> Fixes: 681c1615f891 ("vfio/mbochs: Convert to use vfio_register_group_dev()")
> Reported-by: Cornelia Huck
> Signed-off-by:
On Tue, Jul 20, 2021 at 4:07 AM Matthew Auld
wrote:
>
> On Fri, 16 Jul 2021 at 15:14, Jason Ekstrand wrote:
> >
> > From: Thomas Hellström
> >
> > If our exported dma-bufs are imported by another instance of our driver,
> > that instance will typically have the imported dma-bufs locked during
>
On 7/16/2021 13:17, Matthew Brost wrote:
Requests may take slightly longer with GuC submission, let's increase
the timeouts in live_requests.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/selftests/i915_request.c | 4 ++--
1 file changed, 2 insertions(+
Like vfio_pci_try_bus_reset() this code wants to reset all of the devices
in the "reset group" which is the same membership as the device set.
Instead of trying to reconstruct the device set from the PCI list go
directly from the device set's device list to execute the reset.
The same basic struc
Currently the driver ops have an open/release pair that is called once
each time a device FD is opened or closed. Add an additional set of
open/close_device() ops which are called when the device FD is opened for
the first time and closed for the last time.
An analysis shows that all of the driver
From: Max Gurtovoy
This pairs with vfio_init_group_dev() and allows undoing any state that is
stored in the vfio_device unrelated to registration. Add appropriately
placed calls to all the drivers.
The following patch will use this to add pre-registration state for the
device set.
Signed-off-by
The core code no longer requires these ops to be defined, so delete these
empty functions and leave the op as NULL. mtty's functions only log a
pointless message, delete that entirely.
Signed-off-by: Yishai Hadas
Reviewed-by: Cornelia Huck
Signed-off-by: Jason Gunthorpe
---
samples/vfio-mdev/m
Nothing uses this anymore, delete it.
Signed-off-by: Yishai Hadas
Signed-off-by: Jason Gunthorpe
---
drivers/vfio/mdev/vfio_mdev.c | 22 --
drivers/vfio/vfio.c | 14 +-
include/linux/mdev.h | 7 ---
include/linux/vfio.h | 4
The user can open multiple device FDs if it likes, however these open()
functions call vfio_register_notifier() on some device global
state. Calling vfio_register_notifier() twice in will trigger a WARN_ON
from notifier_chain_register() and the first close will wrongly delete the
notifier and more.
mbochs_close() iterates over global device state and frees it. Currently
this is done every time a device FD is closed, but if multiple device FDs
are open this could corrupt other still active FDs.
Change this to use close_device() so it only runs on the last close.
Reviewed-by: Cornelia Huck
S
From: Yishai Hadas
PCI wants to have the usual open/close_device() logic with the slight
twist that the open/close_device() must be done under a singelton lock
shared by all of the vfio_devices that are in the PCI "reset group".
The reset group, and thus the device set, is determined by what dev
Compared to mbochs_remove() two cases are missing from the
vfio_register_group_dev() unwind. Add them in.
Fixes: 681c1615f891 ("vfio/mbochs: Convert to use vfio_register_group_dev()")
Reported-by: Cornelia Huck
Signed-off-by: Jason Gunthorpe
---
samples/vfio-mdev/mbochs.c | 7 +--
1 file ch
Keep track of all the vfio_devices that have been added to the device set
and use this list in vfio_pci_try_bus_reset() instead of trying to work
backwards from the pci_device.
The dev_set->lock directly prevents devices from joining/leaving the set,
which further implies the pci_device cannot cha
This is in support of Max's series to split vfio-pci. For that to work the
reflck concept embedded in vfio-pci needs to be sharable across all of the
new VFIO PCI drivers which motivated re-examining how this is
implemented.
Another significant issue is how the VFIO PCI core includes code like:
The user can open multiple device FDs if it likes, however the open
function calls vfio_register_notifier() on device global state. Calling
vfio_register_notifier() twice will trigger a WARN_ON from
notifier_chain_register() and the first close will wrongly delete the
notifier and more.
Since thes
FSL uses the internal reflck to implement the open_device() functionality,
conversion to the core code is straightforward.
The decision on which set to be part of is trivially based on the
is_fsl_mc_bus_dprc() and we use a 'struct device *' pointer as the set_id.
The dev_set lock is protecting th
Platform simply wants to run some code when the device is first
opened/last closed. Use the core framework and locking for this. Aside
from removing a bit of code this narrows the locking scope from a global
lock.
Signed-off-by: Yishai Hadas
Signed-off-by: Jason Gunthorpe
---
drivers/vfio/plat
The patch to move the get/put to core and the patch to convert the samples
to use vfio_device crossed in a way that this was missed. When both
patches are together the samples do not need their own get/put.
Fixes: 437e41368c01 ("vfio/mdpy: Convert to use vfio_register_group_dev()")
Fixes: 681c1615
On 7/16/2021 13:17, Matthew Brost wrote:
When using GuC submission, if a context gets banned disable scheduling
and mark all inflight requests as complete.
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
Fixed all the nits below locally. It'll be in the next send.
On Tue, Jul 20, 2021 at 5:53 AM Matthew Auld
wrote:
>
> On Fri, 16 Jul 2021 at 15:14, Jason Ekstrand wrote:
> >
> > From: Thomas Hellström
> >
> > Until we support p2p dma or as a complement to that, migrate data
> > to system memory
On Tue, Jul 13, 2021 at 08:15:01PM -0700, Matt Roper wrote:
> From: Stuart Summers
>
> Xe_HP changes the format of the context ID from past platforms.
>
> Signed-off-by: Stuart Summers
> Signed-off-by: Umesh Nerlige Ramappa
> Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
> ---
> .../dr
== Series Details ==
Series: drm/i915: Correct the docs for intel_engine_cmd_parser
URL : https://patchwork.freedesktop.org/series/92786/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10358_full -> Patchwork_20656_full
Summ
On Tue, Jul 20, 2021 at 01:19:48PM -0700, John Harrison wrote:
> On 7/16/2021 13:16, Matthew Brost wrote:
> > Reset implementation for new GuC interface. This is the legacy reset
> > implementation which is called when the i915 owns the engine hang check.
> > Future patches will offload the engine
On Tue, Jul 20, 2021 at 3:26 PM Rodrigo Vivi wrote:
>
> On Tue, Jul 20, 2021 at 04:25:21PM -0400, Rodrigo Vivi wrote:
> > On Tue, Jul 20, 2021 at 01:21:08PM -0500, Jason Ekstrand wrote:
> > > In c9d9fdbc108a ("drm/i915: Revert "drm/i915/gem: Asynchronous
> > > cmdparser""), the parameters to intel
On Tue, Jul 13, 2021 at 08:14:59PM -0700, Matt Roper wrote:
> Implement Xe_HP forcewake handling. While we're at it, let's reorder to
> the forcewake assignment if/else ladder to match our usual driver
> conventions.
>
> Co-authored-by: Daniele Ceraolo Spurio
> Signed-off-by: Daniele Ceraolo Spu
== Series Details ==
Series: Parallel submission aka multi-bb execbuf
URL : https://patchwork.freedesktop.org/series/92789/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
LD [M]
== Series Details ==
Series: Fix the debugfs splat from mock selftests (rev2)
URL : https://patchwork.freedesktop.org/series/92729/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10358_full -> Patchwork_20655_full
Summary
--
Since child contexts do not own the guc_ids or GuC context registration,
child contexts can simply be freed on destroy. Add
guc_child_context_destroy context operation to do this.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 +++
1 file changed, 7 in
Submitting to a subset of hardware contexts is not allowed, so use the
copy engine for GPU relocations when using a parallel context.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/
The GuC must receive requests in the order submitted for contexts in a
parent-child relationship to function correctly. To ensure this, insert
a submit fence between the current request and last request submitted
for requests / contexts in a parent child relationship. This is
conceptually similar t
Update context and full GPU reset to work with multi-lrc. The idea is
parent context tracks all the active requests inflight for itself and
its' children. The parent context owns the reset replaying / canceling
requests as needed.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_co
Move the job of creating an input/exec fences (from a file descriptor)
out of i915_gem_do_execbuffer.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 75 +++
1 file changed, 43 insertions(+), 32 deletions(-)
diff --
Move the job of creating a new sync fence and installing it onto a file
descriptor to i915_gem_execbuffer2.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 39 +--
1 file changed, 19 insertions(+), 20 deletions(-)
di
Certain VMA functions in the execbuf IOCTL only need to be called on
first or last BB of a multi-BB submission. eb_relocate() on the first
and eb_release_vmas() on the last. Doing so will save CPU / GPU cycles.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 123
In GuC parent-child contexts the parent context controls the scheduling,
ensure only the parent does the scheduling operations.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 48 +++
1 file changed, 38 insertions(+), 10 deletions(-)
diff --git a
Goal is to remove all input sanity checks from the core submission.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 35 +++
1 file changed, 21 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i91
Allow specifying the batch directly over what is inferred from passed in
execbuf flags.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem
For contexts with width set to two or more, we add a mode to execbuf2
which implies there are N batch buffers in the buffer list, each of
which will be sent to one of the engines from the engine map array
(I915_CONTEXT_PARAM_ENGINES, I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT).
Those N batches can e
In case of multiple batches all batches will be at the beginning on the exec
objects array or at the end based on the existing execbuffer2 flag.
Batches not executed in the current execbuf call will not be processed for
relocations or but will be pinned in same manner as the current batch.
This w
For some users of multi-lrc, e.g. split frame, it isn't safe to preempt
mid BB. To safely enable preemption at the BB boundary, a handshake
between to parent and child is needed. This is implemented via custom
emit_bb_start & emit_fini_breadcrumb functions and enabled via by
default if a context is
A weak implmentation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Basically doing as little as possible to support this
interface for execlists - basically just passing submit fences between
each request generated and virtual engines are not allowed. This is on
par with what is th
This will help with upcoming extensions where more than 1 batch can be
submitted in a single execbuf IOCTL.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
di
Sometimes it is desirable to queue work up for later if the GT PM isn't
held and run that work on next GT PM unpark.
Implemented with a list in the GT of all pending work, workqueues in
the list, a callback to add a workqueue to the list, and finally a
wakeref post_get callback that iterates / dra
Expose logical engine instance to user via query engine info IOCTL. This
is required for split-frame workloads as these needs to be placed on
engines in a logically contiguous order. The logical mapping can change
based on fusing. Rather than having user have knowledge of the fusing we
simply just
Only track object dependencies on the first request generated from the
execbuf, this help with the upcoming multi-bb execbuf extension.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/
Move the job of creating a new file descriptor and passing it back to
userspace to i915_gem_execbuffer2.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 45 ++-
1 file changed, 25 insertions(+), 20 deletions(-)
diff
Display the workqueue status in debugfs for GuC contexts that are in
parent-child relationship.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 56 +--
1 file changed, 39 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/inte
1 - 100 of 202 matches
Mail list logo
