== Series Details ==
Series: series starting with [01/10] drm/i915/bios: Allow DSI ports to be
parsed by parse_ddi_port()
URL : https://patchwork.freedesktop.org/series/92874/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10368 -> Patchwork_20674
=
== Series Details ==
Series: 5.14-rc2 warnings with kvmgvt (rev2)
URL : https://patchwork.freedesktop.org/series/92845/
State : failure
== Summary ==
Applying: 5.14-rc2 warnings with kvmgvt
error: patch failed: drivers/gpu/drm/i915/display/intel_display.c:11371
error: drivers/gpu/drm/i915/disp
== Series Details ==
Series: series starting with [01/10] drm/i915/bios: Allow DSI ports to be
parsed by parse_ddi_port()
URL : https://patchwork.freedesktop.org/series/92874/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit w
== Series Details ==
Series: series starting with [01/10] drm/i915/bios: Allow DSI ports to be
parsed by parse_ddi_port()
URL : https://patchwork.freedesktop.org/series/92874/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ef88c9c5b742 drm/i915/bios: Allow DSI ports to be parse
On Wed, Jul 21, 2021 at 06:00:23PM -0400, Rodrigo Vivi wrote:
PORT_A to PORT_F are regular integers defined in the enum port,
while for_each_port_masked requires a bit mask for the ports.
Current given mask: 0b111
Desired mask: 0b11
I noticed this while Christoph was reporting a bug found o
== Series Details ==
Series: drm/i915/bios: Fix ports mask
URL : https://patchwork.freedesktop.org/series/92850/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367_full -> Patchwork_20672_full
Summary
---
**SUCCESS*
On Thu, Jul 22, 2021 at 05:24:30AM +0100, Christoph Hellwig wrote:
On Wed, Jul 21, 2021 at 05:18:18PM -0400, Rodrigo Vivi wrote:
could you please try this small patch?
I had to hand apply it as it wa corruped to due to cut off context.
It fixes one of the warnings, new output below:
[4.1
On Thu, Jul 22, 2021 at 01:05:49PM +0800, Zhenyu Wang wrote:
> On 2021.07.21 13:10:49 +0200, Christoph Hellwig wrote:
> > Hi all,
> >
> > I'm trying to test some changes for the gvt code, but even with a baseline
> > 5.14-rc2 host and guest the 915 driver does not seem overly happy:
> >
>
> I thi
On Wed, 2021-07-21 at 18:00 -0400, Rodrigo Vivi wrote:
> PORT_A to PORT_F are regular integers defined in the enum port,
> while for_each_port_masked requires a bit mask for the ports.
>
> Current given mask: 0b111
> Desired mask: 0b11
>
> I noticed this while Christoph was reporting a bug fo
Continuing the conversion from single integrated VBT data to two, now
handling DSI data.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/icl_dsi.c | 12 +-
drivers/gpu/drm/i915/display/intel_bios.c| 163 ++-
dri
Tigerlake and newer has two instances of PPS, to support up to two
eDP panels.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_pps.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/
Continuing the conversion from single integrated VBT data to two, now
handling PSR data.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 73 +--
drivers/gpu/drm/i915/display/intel_bios.h | 2 +
drivers/
Continuing the conversion from single integrated VBT data to two, now
handling backlight data.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 59 +++
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
All the users was converted now we can drop it.
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 36 ---
drivers/gpu/drm/i915/i915_drv.h | 1 -
2 files changed, 37 deletions(-)
diff --git a/dr
Continuing the conversion from single integrated VBT data to two, now
handling eDP data.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/g4x_dp.c | 9 +--
drivers/gpu/drm/i915/display/intel_bios.c | 62 +---
drive
On newer platform this opregion call always fails, also it do not
support multiple panels so dropping it.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c | 19 +++
1 file changed, 7 insertions(+), 12 deletions
Continuing the conversion from single integrated VBT data to two.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_bios.c| 53 +---
drivers/gpu/drm/i915/display/intel_bios.h| 1 +
drivers/gpu/drm/i915/display
Allow MIPI DSI ports to be parsed like any other DDI port.
This will be helpful to integrate into just one function the parse of
information about integrated panels(eDP and DSI).
Allow MIPI DSI ports to be parsed to be parsed like any other DDI
port.
This will be helpful to integrate into just one
VBT has support for up two integrated panels but i915 only supports one.
So here stating to add the basic support for two integrated panels
and moving the DRRS to ddi_vbt_port_info instead of keeping a global
one.
Other VBT blocks will be converted in following patches.
While at is also nucking l
On 2021.07.21 13:10:49 +0200, Christoph Hellwig wrote:
> Hi all,
>
> I'm trying to test some changes for the gvt code, but even with a baseline
> 5.14-rc2 host and guest the 915 driver does not seem overly happy:
>
I think we also got bug report on those display related warnings, should be
some i
On Wed, Jul 21, 2021 at 3:51 PM Matt Roper wrote:
>
> On Tue, Jul 20, 2021 at 04:20:13PM -0700, Lucas De Marchi wrote:
> > We kept adding new engines and for that increasing hw_id unnecessarily:
> > it's not used since GRAPHICS_VER == 8. Prepend "gen6" to the field and
> > try to pack it in the st
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/step: Add macro magic for
handling steps
URL : https://patchwork.freedesktop.org/series/92849/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367_full -> Patchwork_20671_full
On Fri, Jul 16, 2021 at 01:17:06PM -0700, Matthew Brost wrote:
> From: John Harrison
>
> The driver must provide GuC with a list of mmio registers
> that should be saved/restored during a GuC-based engine reset.
> Unfortunately, the list must be dynamically allocated as its size is
> variable. Th
On Wed, Jul 21, 2021 at 05:18:18PM -0400, Rodrigo Vivi wrote:
> could you please try this small patch?
I had to hand apply it as it wa corruped to due to cut off context.
It fixes one of the warnings, new output below:
[4.182820] i915 :00:04.0: [drm] Virtual GPU for Intel GVT-g detected.
== Series Details ==
Series: Series to merge a subset of GuC submission (rev2)
URL : https://patchwork.freedesktop.org/series/92791/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367_full -> Patchwork_20670_full
Summary
-
== Series Details ==
Series: drm/i915: Migrate memory to SMEM when imported cross-device (rev3)
URL : https://patchwork.freedesktop.org/series/92617/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367_full -> Patchwork_20668_full
==
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.14-rc2 next-20210721]
[If your patch is applied to the wrong git tree
== Series Details ==
Series: drm/i915: Ditch i915 globals shrink infrastructure
URL : https://patchwork.freedesktop.org/series/92841/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10367_full -> Patchwork_20667_full
Summary
== Series Details ==
Series: drm/i915/guc: Enable GuC based power management features
URL : https://patchwork.freedesktop.org/series/92831/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367_full -> Patchwork_20666_full
Su
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.14-rc2 next-20210721]
[If your patch is applied to the wrong git tree
On 7/21/2021 10:24 AM, Michal Wajdeczko wrote:
On 21.07.2021 18:11, Vinay Belgaumkar wrote:
Add macros to check for SLPC support. This feature is currently supported
for Gen12+ and enabled whenever GuC submission is enabled/selected.
Include templates for SLPC init/fini and enable.
v2: Mov
== Series Details ==
Series: CI pass for reviewed Xe_HP SDV and DG2 patches
URL : https://patchwork.freedesktop.org/series/92853/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367 -> Patchwork_20673
Summary
---
**S
== Series Details ==
Series: CI pass for reviewed Xe_HP SDV and DG2 patches
URL : https://patchwork.freedesktop.org/series/92853/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/
== Series Details ==
Series: CI pass for reviewed Xe_HP SDV and DG2 patches
URL : https://patchwork.freedesktop.org/series/92853/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3c0d66813984 drm/i915: Add XE_HP initial definitions
35b61c43f3e6 drm/i915/xehpsdv: add initial XeHP S
On 7/20/2021 6:51 PM, John Harrison wrote:
On 7/20/2021 15:39, Matthew Brost wrote:
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
v2:
(Daniel Vetter)
- Use msleep_interruptible rather than cond_resched in busy loop
(Michal)
-
On 7/19/2021 9:04 PM, Matthew Brost wrote:
On Mon, Jul 19, 2021 at 05:51:46PM -0700, Daniele Ceraolo Spurio wrote:
On 7/16/2021 1:16 PM, Matthew Brost wrote:
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
v2:
(Daniel Vetter)
-
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next drm/drm-next v5.14-rc2 next-20210721]
[If your patch is applied to the wrong git tree
== Series Details ==
Series: drm/i915/bios: Fix ports mask
URL : https://patchwork.freedesktop.org/series/92850/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367 -> Patchwork_20672
Summary
---
**SUCCESS**
No re
On Wed, Jul 21, 2021 at 03:47:22PM -0700, Matt Roper wrote:
On Tue, Jul 20, 2021 at 04:20:12PM -0700, Lucas De Marchi wrote:
The engine hw_id is only used by RING_FAULT_REG(), which is not used
since GRAPHICS_VER == 8. We tend to keep adding new defines just to be
consistent, but let's try to re
== Series Details ==
Series: drm/i915/bios: Fix ports mask
URL : https://patchwork.freedesktop.org/series/92850/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
69ca4ceb0ec6 drm/i915/bios: Fix ports mask
-:35: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#35:
On Tue, Jul 20, 2021 at 04:20:14PM -0700, Lucas De Marchi wrote:
> This is only used by GRAPHICS_VER == 6 and GRAPHICS_VER == 7. All other
> recent platforms do not depend on this field, so it doesn't make much
> sense to keep it generic like that. Instead, just do a mapping from
> engine class to
The i915 currently has 2k visible priority levels which are currently
unqiue. This is changing to statically map these 2k levels into 3
buckets:
low: < 0
mid: 0
high: > 0
Update gem_scheduler to understand this. This entails updating promotion
test to use 3 levels that will map into different buc
The i915 currently has 2k visible priority levels which are currently
unqiue. This is changing to statically map these 2k levels into 3
buckets:
low: < 0
mid: 0
high: > 0
Update gem_scheduler to understand this. This entails updating promotion
test to use 3 levels that will map into different buc
Signed-off-by: Matthew Brost
---
lib/intel_ctx.c | 28 +++-
lib/intel_ctx.h | 2 ++
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/lib/intel_ctx.c b/lib/intel_ctx.c
index f28c15544..11ec6fca4 100644
--- a/lib/intel_ctx.c
+++ b/lib/intel_ctx.c
@@ -83,6 +83,
Signed-off-by: Matthew Brost
---
include/drm-uapi/i915_drm.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 6ac6c76b4..008d39426 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -572,6 +572,
Add basic parallel execbuf submission test which more or less just
submits the same BB in loop a which does an atomic increment to a memory
location. The memory location is checked at the end for the correct
value. Different sections use various IOCTL options (e.g. fences,
location of BBs, etc...).
IGT updates for GuC submission [1] and parallel submission (aka multi-bb
execbuf) [2]. This entails adding tests for parallel submission and
teaching IGTs to know of static priority mapping.
More IGTs likely need to be updated gem_ctx_persistence and i915_hangman
come to mind. Expect following ser
Signed-off-by: Matthew Brost
---
include/drm-uapi/i915_drm.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 3c1aac348..6ac6c76b4 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@
Signed-off-by: Matthew Brost
---
include/drm-uapi/i915_drm.h | 128
1 file changed, 128 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index a1c0030c3..3c1aac348 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/step: Add macro magic for
handling steps
URL : https://patchwork.freedesktop.org/series/92849/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367 -> Patchwork_20671
==
On Tue, Jul 20, 2021 at 04:20:13PM -0700, Lucas De Marchi wrote:
> We kept adding new engines and for that increasing hw_id unnecessarily:
> it's not used since GRAPHICS_VER == 8. Prepend "gen6" to the field and
> try to pack it in the structs to give a hint this field is actually not
> used in rec
On Tue, Jul 20, 2021 at 04:20:12PM -0700, Lucas De Marchi wrote:
> The engine hw_id is only used by RING_FAULT_REG(), which is not used
> since GRAPHICS_VER == 8. We tend to keep adding new defines just to be
> consistent, but let's try to remove them and let them defined to 0 when
> not used.
s/w
On Tue, Jul 20, 2021 at 04:20:11PM -0700, Lucas De Marchi wrote:
> gen8_clear_engine_error_register() is actually not used by
> GRAPHICS_VER >= 8, since for those we are using another register that is
> not engine-dependent. Fix the platform prefix, to make clear we are not
> using any GEN6_RING_FA
On DG2 we're supposed to just wait 600us after programming the well
before moving on; there won't be an ack from the hardware.
Bspec: 49296
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
.../gpu/drm/i915/display/intel_display_power.c | 16
.../gpu/drm/i915/d
Although the BW_BUDDY registers still exist, they are not used for
anything on DG2. This change is expected to hold true for future dgpu's
too.
Bspec: 49218
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_power.c | 4
1 file chan
DG2 has no shared DPLL's or DDI clock muxing. The Port PLL is embedded
within the PHY.
Bspec: 54032
Bspec: 54034
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++---
drivers/gpu/drm/i915/display/int
From: Stuart Summers
Xe_HP changes the format of the context ID from past platforms.
Signed-off-by: Stuart Summers
Signed-off-by: Umesh Nerlige Ramappa
Signed-off-by: Matt Roper
Reviewed-by: Matt Atwood
---
.../drm/i915/gt/intel_execlists_submission.c | 74 ---
drivers/gpu/
As with DG1, DG2 has an ICL-style south display interface provided on
the same PCI device. Add a fake PCH to ensure DG2 takes the appropriate
codepaths for south display handling.
Bspec: 54871, 50062, 49961, 53673
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
Signed-off-by: Aditya Swarup
Signe
DG2 extends our DDB to four DBuf slices; pipes A+B only have access to
the first two slices, whereas pipes C+D only have access to the second
two.
Confusingly, our bspec decided to switch from 1-based numbering
of dbuf slices (S1, S2) to 0-based numbering (S0, S1, S2, S3) in
Display13. At the mom
From: Lucas De Marchi
Our _FEATURES macro went back to GEN7, extending each other, making it
difficult to grasp what was really enabled/disabled. Take the
opportunity of the GEN -> XE_HP name break and also break with the
feature inheritance.
For XE_HP this basically goes from GEN12 back to GEN7
Note that DG2 only has a single possible refclk frequency (38.4 MHz).
v2:
- Drop two now-unused cdclk entries
Bspec: 54034
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Signed-off-by: Matt Roper
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 22
From: Prathap Kumar Valsan
The layout of some engine contexts has changed on Xe_HP. Define the new
offsets.
Bspec: 45585, 46256
Signed-off-by: Prathap Kumar Valsan
Signed-off-by: Ramalingam C
Signed-off-by: Venkata Ramana Nayana
Signed-off-by: Akeem G Abodunrin
Signed-off-by: Matt Roper
Re
DG2 doesn't have a SAGV or QGV points that determine memory bandwidth.
Instead it has a constant amount of memory bandwidth available to
display that does not need to be reduced based on the number of active
planes.
For simplicity, we'll just modify driver initialization to create a
single dummy Q
DG2 has outputs on DDI A-D attached to what the bspec diagram shows as
"Combo PHY A-D." Note that despite being labelled "combo" the PHYs on
these outputs are Synopsys PHYs rather than traditional Intel combo PHY
technology.
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
Reviewed-by: José Robert
DG2 does not use system DRAM information for BW_BUDDY programming or
watermark workarounds, so there's no need to read this out at startup.
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_dram.c | 6 +++---
1 file changed, 3 insertions(
From: John Harrison
Increasing the engine count causes a couple of local array variables
to exceed the kernel stack limit. So make them dynamic allocations
instead.
Signed-off-by: John Harrison
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
---
From: Tvrtko Ursulin
On Xe_HP the fusing register is renamed and changed to have the "enable"
semantics, but otherwise remains compatible (mmio address, bitmask
ranges) with older platforms.
To simplify things we do not add a new register definition but just stop
inverting the fusing masks befor
From: Paulo Zanoni
The current interrupt handler is getting increasingly complicated and
Xe_HP changes will bring even more complexity. Let's split off a new
interrupt handler starting with DG1 (i.e., when the master tile
interrupt register was added to the design) and use that as the basis
for
DG2 has Xe_LPD display (version 13) and Xe_HPG (version 12.55) graphics.
There are two variants (treated as subplatforms in the code): DG2-G10
and DG2-G11 that require independent programming in some areas (e.g.,
workarounds).
Bspec: 44472, 44474, 46197, 48028, 48077
Cc: Anusha Srivatsa
Signed-o
From: Venkata Sandeep Dhanalakota
In Gen12 there are various fuse combinations and in each configuration
vdbox engine may be connected to SFC depending on which engines are
available, so we need to set the SFC capability based on fuse value from
the hardware. Even numbered physical instance alway
From: Lucas De Marchi
XeHP SDV is a Intel® dGPU without display. This is just the definition
of some basic platform macros, by large a copy of current state of
Tigerlake which does not reflect the end state of this platform.
v2:
- Switch to intel_step infrastructure for stepping matches. (Jani)
We have enough reviews that we can start applying some of these patches;
let's kick off another CI run for the reviewed patches that don't have
dependencies on other unreviewed patches.
The plan is to apply the first couple patches (which have the
definitions like IS_XEHPSDV and IS_DG2) to a topic
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/step: Add macro magic for
handling steps
URL : https://patchwork.freedesktop.org/series/92849/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be check
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/step: Add macro magic for
handling steps
URL : https://patchwork.freedesktop.org/series/92849/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c0b839cec037 drm/i915/step: Add macro magic for handling steps
-:24:
== Series Details ==
Series: Series to merge a subset of GuC submission (rev2)
URL : https://patchwork.freedesktop.org/series/92791/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367 -> Patchwork_20670
Summary
---
PORT_A to PORT_F are regular integers defined in the enum port,
while for_each_port_masked requires a bit mask for the ports.
Current given mask: 0b111
Desired mask: 0b11
I noticed this while Christoph was reporting a bug found on headless
GVT configuration which bisect blamed commit 3ae04c0c
== Series Details ==
Series: Series to merge a subset of GuC submission (rev2)
URL : https://patchwork.freedesktop.org/series/92791/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm
== Series Details ==
Series: Series to merge a subset of GuC submission (rev2)
URL : https://patchwork.freedesktop.org/series/92791/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
081c22c811d7 drm/i915/guc: Add new GuC interface defines and structures
87421139cc96 drm/i915/guc:
Lets use RUNTIME_INFO->step since all platforms now have their
stepping info in intel_step.c. This makes intel_get_stepping_info()
a lot simpler.
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dmc.c | 50 --
Add support to load latest DMC version.
The Release Notes mentions that this version fixes
timeout issues.
Cc: Madhumitha Pradeep
Signed-off-by: Anusha Srivatsa
Reviewed-by: Madhumitha Pradeep <
---
drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(
Add support to the latest DMC firmware.
Cc: Madhunitha Pradeep
Signed-off-by: Anusha Srivatsa
Reviewed-by: Madhumitha Pradeep <
---
drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/driver
With the addition of stepping info for
all platforms, lets use macros for handling them
and autogenerating code for all steps at a time.
Suggested-by: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_step.c | 14
== Series Details ==
Series: drm/i915: Migrate memory to SMEM when imported cross-device (rev3)
URL : https://patchwork.freedesktop.org/series/92617/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10367 -> Patchwork_20668
Su
== Series Details ==
Series: 5.14-rc2 warnings with kvmgvt
URL : https://patchwork.freedesktop.org/series/92845/
State : failure
== Summary ==
Applying: 5.14-rc2 warnings with kvmgvt
error: corrupt patch at line 12
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=dif
Update GuC debugfs to support the new GuC structures.
v2:
(John Harrison)
- Remove intel_lrc_reg.h include from i915_debugfs.c
(Michal)
- Rename GuC debugfs functions
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/inte
Add trace point for GuC submit. Extended existing request trace points
to include submit fence value,, guc_id, and ring tail value.
v2: Fix white space alignment in i915_request_add trace point
v3: Delete dep_from , dep_to (Tvrtko)
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Joh
Add intel_context tracing. These trace points are particular helpful
when debugging the GuC firmware and can be enabled via
CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS kernel config option.
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_co
Disable preempt busywait when using GuC scheduling. This isn't needed as
the GuC controls preemption when scheduling.
v2:
(John H):
- Fix commit message
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 --
1 file
Extend the deregistration context fence to fence whne a GuC context has
scheduling disable pending.
v2:
(John H)
- Update comment why we check the pin count within spin lock
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submi
Disable engine barriers for unpinning with GuC. This feature isn't
needed with the GuC as it disables context scheduling before unpinning
which guarantees the HW will not reference the context. Hence it is
not necessary to defer unpinning until a kernel context request
completes on each engine in t
Semaphores are an optimization and not required for basic GuC submission
to work properly. Disable until we have time to do the implementation to
enable semaphores and tune them for performance. Also long direction is
just to delete semaphores from the i915 so another reason to not enable
these for
If two requests are on the same ring, they are explicitly ordered by the
HW. So, a submission fence is sufficient to ensure ordering when using
the new GuC submission interface. Conversely, if two requests share a
timeline and are on the same physical engine but different context this
doesn't ensur
When running the GuC the GPU can't be considered idle if the GuC still
has contexts pinned. As such, a call has been added in
intel_gt_wait_for_idle to idle the UC and in turn the GuC by waiting for
the number of unpinned contexts to go to zero.
v2: rtimeout -> remaining_timeout
v3: Drop unnecessa
Add bypass tasklet submission path to GuC. The tasklet is only used if H2G
channel has backpresure.
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++
1 file changed, 29 insertions(+), 8 deletions(-)
diff --git a/
Ensure G2H response has space in the buffer before sending H2G CTB as
the GuC can't handle any backpressure on the G2H interface.
v2:
(Matthew)
- s/INTEL_GUC_SEND/INTEL_GUC_CT_SEND
v3:
(Matthew)
- Add G2H credit accounting to blocking path, add g2h_release_space
helper
(John H)
- CTB_
Remove old GuC stage descriptor, add LRC descriptor which will be used
by the new GuC interface implemented in this patch series.
v2:
(John Harrison)
- s/lrc/LRC/g
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h|
With GuC scheduling, it isn't safe to unpin a context while scheduling
is enabled for that context as the GuC may touch some of the pinned
state (e.g. LRC). To ensure scheduling isn't enabled when an unpin is
done, a call back is added to intel_context_unpin when pin count == 1
to disable schedulin
Implement GuC context operations which includes GuC specific operations
alloc, pin, unpin, and destroy.
v2:
(Daniel Vetter)
- Use msleep_interruptible rather than cond_resched in busy loop
(Michal)
- Remove C++ style comment
v3:
(Matthew Brost)
- Drop GUC_ID_START
(John Harrison)
- Fix
Add LRC descriptor context lookup array which can resolve the
intel_context from the LRC descriptor index. In addition to lookup, it
can determine if the LRC descriptor context is currently registered with
the GuC by checking if an entry for a descriptor index is present.
Future patches in the seri
Add new GuC interface defines and structures while maintaining old ones
in parallel.
Cc: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 14 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 42 +++
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