[Intel-gfx] [PATCH v4] drm/i915/gt: move remaining debugfs interfaces into gt

2021-10-08 Thread Andi Shyti
From: Andi Shyti The following interfaces: i915_wedged i915_forcewake_user are dependent on gt values. Put them inside gt/ and drop the "i915_" prefix name. This would be the new structure: dri/0/gt | +-- forcewake_user | \-- reset For backwards compatibility with existing igt

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: move remaining debugfs interfaces into gt (rev11)

2021-10-08 Thread Patchwork
== Series Details == Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev11) URL : https://patchwork.freedesktop.org/series/75333/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21301_full

[Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Initial multi-tile support

2021-10-08 Thread Patchwork
== Series Details == Series: i915: Initial multi-tile support URL : https://patchwork.freedesktop.org/series/95631/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21298_full Summary ---

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev8)

2021-10-08 Thread Patchwork
== Series Details == Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev8) URL : https://patchwork.freedesktop.org/series/95127/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21296_full

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: move remaining debugfs interfaces into gt (rev11)

2021-10-08 Thread Patchwork
== Series Details == Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev11) URL : https://patchwork.freedesktop.org/series/75333/ State : success == Summary == CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21301

Re: [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers

2021-10-08 Thread Harry Wentland
On 2021-10-08 04:36, Tvrtko Ursulin wrote: > > Hi, > > Is it my checkout only or this causes a lot of build warnings for everyone? > > ./include/drm/drm_dp_helper.h:1120: warning: > "DP_TEST_264BIT_CUSTOM_PATTERN_7_0" redefined >  1120 | #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0  0x2230 >  

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/icl: Fix read of memory frequency

2021-10-08 Thread Patchwork
== Series Details == Series: drm/i915/icl: Fix read of memory frequency URL : https://patchwork.freedesktop.org/series/95627/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21295_full Summary ---

Re: [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt

2021-10-08 Thread Andi Shyti
Hi Ville, > > + if (IS_CHERRYVIEW(i915)) { > > + seq_printf(m, "Master Interrupt Control:\t%08x\n", > > + intel_uncore_read(uncore, GEN8_MASTER_IRQ)); > > + > > + for (i = 0; i < 4; i++) { > > + seq_printf(m, "GT Interrupt IMR

[Intel-gfx] ✗ Fi.CI.BAT: failure for i915: Initial multi-tile support (rev2)

2021-10-08 Thread Patchwork
== Series Details == Series: i915: Initial multi-tile support (rev2) URL : https://patchwork.freedesktop.org/series/95631/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21300 Summary ---

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Initial multi-tile support (rev2)

2021-10-08 Thread Patchwork
== Series Details == Series: i915: Initial multi-tile support (rev2) URL : https://patchwork.freedesktop.org/series/95631/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2226b987792c drm/i915: rework some irq functions to take intel_gt as argument -:17: WARNING:BAD_SIGN_OFF:

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Failsafe migration blits

2021-10-08 Thread Patchwork
== Series Details == Series: drm/i915: Failsafe migration blits URL : https://patchwork.freedesktop.org/series/95617/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21293_full Summary ---

Re: [Intel-gfx] [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt

2021-10-08 Thread Lucas De Marchi
On Fri, Oct 8, 2021 at 3:14 AM Andi Shyti wrote: > > Hi Lucas, > > > > I am reproposing this patch exactly as it was proposed initially > > > where the original interfaces are kept where they have been > > > originally placed. It might generate some duplicated code but, > > > well, it's debugfs

Re: [Intel-gfx] [PATCH 07/11] drm/i915/xehp: Determine which tile raised an interrupt

2021-10-08 Thread Matt Roper
On Fri, Oct 08, 2021 at 02:56:31PM -0700, Matt Roper wrote: > From: Paulo Zanoni > > The first step of interrupt handling is to read a tile0 register that > tells us in which tile the interrupt happened; we can then we read the > usual interrupt registers from the appropriate tile. > > Note

[Intel-gfx] ✗ Fi.CI.BAT: failure for dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev3)

2021-10-08 Thread Patchwork
== Series Details == Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev3) URL : https://patchwork.freedesktop.org/series/95605/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21299

[Intel-gfx] [PATCH v2 11/11] drm/i915/xehpsdv: Initialize multi-tiles

2021-10-08 Thread Matt Roper
From: Tvrtko Ursulin Check how many extra GT tiles are available on the system and setup register access for all of them. We can detect how may GT tiles are available by reading a register on the root tile. The same register returns the tile ID on all tiles. v2: - Include some additional

Re: [Intel-gfx] [PATCH 1/1] RFC : drm/i915: Adding new sysfs frequency attributes

2021-10-08 Thread Sundaresan, Sujaritha
On 10/8/2021 4:03 PM, Andi Shyti wrote: Hi Sujaritha, On Fri, Oct 08, 2021 at 01:44:54PM -0700, Sujaritha Sundaresan wrote: This patch adds the following new sysfs frequency attributes; - punit_req_freq_mhz - throttle_reason_status - throttle_reason_pl1 -

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev3)

2021-10-08 Thread Patchwork
== Series Details == Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev3) URL : https://patchwork.freedesktop.org/series/95605/ State : warning == Summary == $ dim checkpatch origin/drm-tip f35815098fd4 dma-resv: Fix dma_resv_get_fences and

Re: [Intel-gfx] [PATCH 1/1] RFC : drm/i915: Adding new sysfs frequency attributes

2021-10-08 Thread Andi Shyti
Hi Sujaritha, On Fri, Oct 08, 2021 at 01:44:54PM -0700, Sujaritha Sundaresan wrote: > This patch adds the following new sysfs frequency attributes; > - punit_req_freq_mhz > - throttle_reason_status > - throttle_reason_pl1 > - throttle_reason_pl2 > -

[Intel-gfx] ✓ Fi.CI.BAT: success for i915: Initial multi-tile support

2021-10-08 Thread Patchwork
== Series Details == Series: i915: Initial multi-tile support URL : https://patchwork.freedesktop.org/series/95631/ State : success == Summary == CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21298 Summary --- **SUCCESS**

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Initial multi-tile support

2021-10-08 Thread Patchwork
== Series Details == Series: i915: Initial multi-tile support URL : https://patchwork.freedesktop.org/series/95631/ State : warning == Summary == $ dim checkpatch origin/drm-tip 21a66c454734 drm/i915: rework some irq functions to take intel_gt as argument -:17: WARNING:BAD_SIGN_OFF:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev8)

2021-10-08 Thread Patchwork
== Series Details == Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev8) URL : https://patchwork.freedesktop.org/series/95127/ State : success == Summary == CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21296

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/1] RFC : drm/i915: Adding new sysfs frequency attributes

2021-10-08 Thread Patchwork
== Series Details == Series: series starting with [1/1] RFC : drm/i915: Adding new sysfs frequency attributes URL : https://patchwork.freedesktop.org/series/95629/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: move remaining debugfs interfaces into gt (rev10)

2021-10-08 Thread Patchwork
== Series Details == Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev10) URL : https://patchwork.freedesktop.org/series/75333/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21292_full

[Intel-gfx] [PATCH 08/11] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware

2021-10-08 Thread Matt Roper
From: Paulo Zanoni Loop through all the tiles when initializing and resetting interrupts. Signed-off-by: Paulo Zanoni Signed-off-by: Tvrtko Ursulin Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_irq.c | 28 ++-- 1 file changed, 18 insertions(+), 10

[Intel-gfx] [PATCH 11/11] drm/i915/xehpsdv: Initialize multi-tiles

2021-10-08 Thread Matt Roper
From: Tvrtko Ursulin Check how many extra GT tiles are available on the system and setup register access for all of them. We can detect how may GT tiles are available by reading a register on the root tile. The same register returns the tile ID on all tiles. Bspec: 33407 Original-author: Abdiel

[Intel-gfx] [PATCH 03/11] drm/i915: Restructure probe to handle multi-tile platforms

2021-10-08 Thread Matt Roper
On a multi-tile platform, each tile has its own registers + GGTT space, and BAR 0 is extended to cover all of them. Upcoming patches will start exposing the tiles as multiple GTs within a single PCI device. In preparation for supporting such setups, restructure the driver's probe code a bit.

[Intel-gfx] [PATCH 06/11] drm/i915: Initial support for per-tile uncore

2021-10-08 Thread Matt Roper
From: Daniele Ceraolo Spurio Initialization and suspend/resume is replicated per-tile. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Tvrtko Ursulin Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt.c | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 5 ++-

[Intel-gfx] [PATCH 07/11] drm/i915/xehp: Determine which tile raised an interrupt

2021-10-08 Thread Matt Roper
From: Paulo Zanoni The first step of interrupt handling is to read a tile0 register that tells us in which tile the interrupt happened; we can then we read the usual interrupt registers from the appropriate tile. Note that this is just the first step of handling interrupts properly on

[Intel-gfx] [PATCH 10/11] drm/i915: Release per-gt resources allocated

2021-10-08 Thread Matt Roper
From: Venkata Sandeep Dhanalakota Iterate for_each_gt during release to support multi-tile devices. Cc: Tvrtko Ursulin Signed-off-by: Venkata Sandeep Dhanalakota Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_drv.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff

[Intel-gfx] [PATCH 01/11] drm/i915: rework some irq functions to take intel_gt as argument

2021-10-08 Thread Matt Roper
From: Paulo Zanoni We'll be adding multi-tile support soon; on multi-tile platforms interrupts are per-tile and every tile has the full set of interrupt registers. In this commit we start passing intel_gt instead of dev_priv for the functions that are related to Xe_HP irq handling. Right now

[Intel-gfx] [PATCH 04/11] drm/i915: Store backpointer to GT in uncore

2021-10-08 Thread Matt Roper
From: Michał Winiarski We now support a per-gt uncore, yet we're not able to infer which GT we're operating upon. Let's store a backpointer for now. Signed-off-by: Michał Winiarski Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-

[Intel-gfx] [PATCH 05/11] drm/i915: Prepare for multiple gts

2021-10-08 Thread Matt Roper
From: Tvrtko Ursulin Add some basic plumbing to support more than one dynamically allocated struct intel_gt. Up to four gts are supported in i915->gts[], with slot zero shadowing the existing i915->gt to enable source compatibility with legacy driver paths. A for_each_gt macro is added to

[Intel-gfx] [PATCH 02/11] drm/i915: split general MMIO setup from per-GT uncore init

2021-10-08 Thread Matt Roper
From: Daniele Ceraolo Spurio In coming patches we'll be doing the actual tile initialization between these two uncore init phases. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_drv.c | 9 - drivers/gpu/drm/i915/intel_uncore.c | 17

[Intel-gfx] [PATCH 00/11] i915: Initial multi-tile support

2021-10-08 Thread Matt Roper
Some of our upcoming platforms, including the Xe_HP SDV, support a "multi-tile" design. A multi-tile platform is effectively a platform with multiple GT instances and local memory regions, all behind a single PCI device. From an i915 perspective, this translates to multiple intel_gt structures

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev8)

2021-10-08 Thread Patchwork
== Series Details == Series: drm/dp, drm/i915: Finish basic PWM support for VESA backlight helpers (rev8) URL : https://patchwork.freedesktop.org/series/95127/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Fix read of memory frequency

2021-10-08 Thread Patchwork
== Series Details == Series: drm/i915/icl: Fix read of memory frequency URL : https://patchwork.freedesktop.org/series/95627/ State : success == Summary == CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21295 Summary ---

Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix read of memory frequency

2021-10-08 Thread Souza, Jose
On Fri, 2021-10-08 at 13:58 -0700, José Roberto de Souza wrote: > All display 9 and display 10 platforms has only 4 bits for the memory > frequency but display 11 platforms it changes to 8 bits. > > Display 9 platforms has another register in bits 7:4 that prevents us > to have a single mask. >

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm: cleanup: Use DRM_MODESET_LOCK_ALL_* helpers

2021-10-08 Thread Fernando Ramos
On 21/10/07 11:58PM, Patchwork wrote: > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_21282_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_invalid_mode@clock-too-high: > -

Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: cleanup: Use DRM_MODESET_LOCK_ALL_* helpers

2021-10-08 Thread Fernando Ramos
On 21/10/07 08:58PM, Patchwork wrote: > > 7bf784bb287c drm: cleanup: remove acquire_ctx from drm_mode_config > -:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate > one > > -:27: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) > > total: 1 errors, 1 warnings, 0

Re: [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: cleanup: Use DRM_MODESET_LOCK_ALL_* helpers

2021-10-08 Thread Fernando Ramos
On 21/10/07 09:01PM, Patchwork wrote: > == Series Details == > > Series: drm: cleanup: Use DRM_MODESET_LOCK_ALL_* helpers > URL : https://patchwork.freedesktop.org/series/95578/ > State : warning > > == Summary == > > $ dim sparse --fast origin/drm-tip > Sparse version: v0.6.2 > Fast mode

[Intel-gfx] [PATCH 1/1] RFC : drm/i915: Adding new sysfs frequency attributes

2021-10-08 Thread Sujaritha Sundaresan
This patch adds the following new sysfs frequency attributes; - punit_req_freq_mhz - throttle_reason_status - throttle_reason_pl1 - throttle_reason_pl2 - throttle_reason_pl4 - throttle_reason_thermal - throttle_reason_prochot -

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Fix read of memory frequency

2021-10-08 Thread Patchwork
== Series Details == Series: drm/i915/icl: Fix read of memory frequency URL : https://patchwork.freedesktop.org/series/95627/ State : warning == Summary == $ dim checkpatch origin/drm-tip fe3148c5e2ce drm/i915/icl: Fix read of memory frequency -:17: WARNING:UNKNOWN_COMMIT_ID: Unknown commit

Re: [Intel-gfx] [PATCH v3 20/20] drm: cleanup: remove acquire_ctx from drm_mode_config

2021-10-08 Thread Fernando Ramos
On 21/10/07 09:37PM, Fernando Ramos wrote: > --- > include/drm/drm_mode_config.h | 10 -- > 1 file changed, 10 deletions(-) > > diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h > index 48b7de80daf5..b214b07157f2 100644 > This patch was missing the commit

[Intel-gfx] [PATCH] drm/i915/icl: Fix read of memory frequency

2021-10-08 Thread José Roberto de Souza
All display 9 and display 10 platforms has only 4 bits for the memory frequency but display 11 platforms it changes to 8 bits. Display 9 platforms has another register in bits 7:4 that prevents us to have a single mask. Also adding new mask with the current name in CRWebViewer, not sure why

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] dri: cleanup debugfs error handling

2021-10-08 Thread Patchwork
== Series Details == Series: series starting with [1/5] dri: cleanup debugfs error handling URL : https://patchwork.freedesktop.org/series/95602/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10699_full -> Patchwork_21290_full

Re: [Intel-gfx] [PATCH 07/26] drm/i915/guc: Introduce context parent-child relationship

2021-10-08 Thread Matthew Brost
On Thu, Oct 07, 2021 at 12:35:08PM -0700, John Harrison wrote: > On 10/4/2021 15:06, Matthew Brost wrote: > > Introduce context parent-child relationship. Once this relationship is > > created all pinning / unpinning operations are directed to the parent > > context. The parent context is

Re: [Intel-gfx] [PATCH 02/26] drm/i915/guc: Take GT PM ref when deregistering context

2021-10-08 Thread Matthew Brost
On Wed, Oct 06, 2021 at 08:37:03PM -0700, John Harrison wrote: > On 10/4/2021 15:06, Matthew Brost wrote: > > Taking a PM reference to prevent intel_gt_wait_for_idle from short > > circuiting while a deregister context H2G is in flight. To do this must > > issue the deregister H2G from a worker as

Re: [Intel-gfx] [PATCH v2 1/7] drm/sysfs: introduce drm_sysfs_connector_hotplug_event

2021-10-08 Thread Simon Ser
Ping

[Intel-gfx] ✗ Fi.CI.BAT: failure for dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev2)

2021-10-08 Thread Patchwork
== Series Details == Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev2) URL : https://patchwork.freedesktop.org/series/95605/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21294

Re: [Intel-gfx] [PATCH 14/26] drm/i915/guc: Implement multi-lrc reset

2021-10-08 Thread Matthew Brost
On Fri, Oct 08, 2021 at 10:39:35AM -0700, John Harrison wrote: > On 10/4/2021 15:06, Matthew Brost wrote: > > Update context and full GPU reset to work with multi-lrc. The idea is > > parent context tracks all the active requests inflight for itself and > > its' children. The parent context owns

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Fixup header includes (rev2)

2021-10-08 Thread Vudum, Lakshminarayana
Re-reported. -Original Message- From: De Marchi, Lucas Sent: Friday, October 8, 2021 8:10 AM To: intel-gfx@lists.freedesktop.org Cc: Vudum, Lakshminarayana Subject: Re: ✗ Fi.CI.BAT: failure for Fixup header includes (rev2) On Fri, Oct 08, 2021 at 06:44:35AM +, Patchwork wrote: >==

Re: [Intel-gfx] [PATCH 16/26] drm/i915: Fix bug in user proto-context creation that leaked contexts

2021-10-08 Thread John Harrison
On 10/4/2021 15:06, Matthew Brost wrote: Set number of engines before attempting to create contexts so the function free_engines can clean up properly. Also check return of alloc_engines for NULL. v2: (Tvrtko) - Send as stand alone patch (John Harrison) - Check for alloc_engines

Re: [Intel-gfx] [PATCH 15/26] drm/i915/guc: Update debugfs for GuC multi-lrc

2021-10-08 Thread John Harrison
On 10/4/2021 15:06, Matthew Brost wrote: Display the workqueue status in debugfs for GuC contexts that are in parent-child relationship. v2: (John Harrison) - Output number children in debugfs Signed-off-by: Matthew Brost Reviewed-by: John Harrison ---

Re: [Intel-gfx] [PATCH 14/26] drm/i915/guc: Implement multi-lrc reset

2021-10-08 Thread John Harrison
On 10/4/2021 15:06, Matthew Brost wrote: Update context and full GPU reset to work with multi-lrc. The idea is parent context tracks all the active requests inflight for itself and its' children. The parent context owns the reset replaying / canceling Still its' should be its. requests as

Re: [Intel-gfx] [PATCH 08/26] drm/i915/guc: Add multi-lrc context registration

2021-10-08 Thread Matthew Brost
On Fri, Oct 08, 2021 at 10:20:16AM -0700, John Harrison wrote: > On 10/7/2021 12:50, John Harrison wrote: > > On 10/4/2021 15:06, Matthew Brost wrote: > > > Add multi-lrc context registration H2G. In addition a workqueue and > > > process descriptor are setup during multi-lrc context registration

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev2)

2021-10-08 Thread Patchwork
== Series Details == Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion (rev2) URL : https://patchwork.freedesktop.org/series/95605/ State : warning == Summary == $ dim checkpatch origin/drm-tip dcabbee4ce57 dma-resv: Fix dma_resv_get_fences and

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Failsafe migration blits

2021-10-08 Thread Patchwork
== Series Details == Series: drm/i915: Failsafe migration blits URL : https://patchwork.freedesktop.org/series/95617/ State : success == Summary == CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21293 Summary --- **SUCCESS**

Re: [Intel-gfx] [PATCH 12/26] drm/i915/guc: Implement multi-lrc submission

2021-10-08 Thread John Harrison
On 10/4/2021 15:06, Matthew Brost wrote: Implement multi-lrc submission via a single workqueue entry and single H2G. The workqueue entry contains an updated tail value for each request, of all the contexts in the multi-lrc submission, and updates these values simultaneously. As such, the tasklet

Re: [Intel-gfx] [PATCH 08/26] drm/i915/guc: Add multi-lrc context registration

2021-10-08 Thread John Harrison
On 10/7/2021 12:50, John Harrison wrote: On 10/4/2021 15:06, Matthew Brost wrote: Add multi-lrc context registration H2G. In addition a workqueue and process descriptor are setup during multi-lrc context registration as these data structures are needed for multi-lrc submission. v2:   (John

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Failsafe migration blits

2021-10-08 Thread Patchwork
== Series Details == Series: drm/i915: Failsafe migration blits URL : https://patchwork.freedesktop.org/series/95617/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. -

[Intel-gfx] ✓ Fi.CI.BAT: success for Fixup header includes (rev2)

2021-10-08 Thread Patchwork
== Series Details == Series: Fixup header includes (rev2) URL : https://patchwork.freedesktop.org/series/95587/ State : success == Summary == CI Bug Log - changes from CI_DRM_10697 -> Patchwork_21289 Summary --- **SUCCESS** No

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: move remaining debugfs interfaces into gt (rev10)

2021-10-08 Thread Patchwork
== Series Details == Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev10) URL : https://patchwork.freedesktop.org/series/75333/ State : success == Summary == CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21292

Re: [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt

2021-10-08 Thread Ville Syrjälä
On Fri, Oct 08, 2021 at 01:27:33PM +0200, Andi Shyti wrote: > + > + if (IS_CHERRYVIEW(i915)) { > + seq_printf(m, "Master Interrupt Control:\t%08x\n", > +intel_uncore_read(uncore, GEN8_MASTER_IRQ)); > + > + for (i = 0; i < 4; i++) { > +

Re: [Intel-gfx] [PATCH 10/26] drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids

2021-10-08 Thread John Harrison
On 10/7/2021 18:21, Matthew Brost wrote: On Thu, Oct 07, 2021 at 03:03:04PM -0700, John Harrison wrote: On 10/4/2021 15:06, Matthew Brost wrote: Assign contexts in parent-child relationship consecutive guc_ids. This is accomplished by partitioning guc_id space between ones that need to be

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: move remaining debugfs interfaces into gt (rev10)

2021-10-08 Thread Patchwork
== Series Details == Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev10) URL : https://patchwork.freedesktop.org/series/75333/ State : warning == Summary == $ dim checkpatch origin/drm-tip 99b302f7 drm/i915/gt: move remaining debugfs interfaces into gt -:138:

Re: [Intel-gfx] [PATCH] dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion

2021-10-08 Thread Christian König
Am 08.10.21 um 12:49 schrieb Tvrtko Ursulin: On 08/10/2021 11:21, Christian König wrote: Am 08.10.21 um 11:50 schrieb Tvrtko Ursulin: From: Tvrtko Ursulin Cache the count of shared fences in the iterator to avoid dereferencing the dma_resv_object outside the RCU protection. Otherwise

Re: [Intel-gfx] [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt

2021-10-08 Thread Andi Shyti
Hi, please ignore! I run the command from the history and forgot that I had to update the patch file. :) V3 of this patch is coming soon. Andi On Fri, Oct 08, 2021 at 01:22:48PM +0200, Andi Shyti wrote: > From: Andi Shyti > > The following interfaces: > > i915_wedged >

[Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt

2021-10-08 Thread Andi Shyti
From: Andi Shyti The following interfaces: i915_wedged i915_forcewake_user i915_gem_interrupt are dependent on gt values. Put them inside gt/ and drop the "i915_" prefix name. This would be the new structure: dri/0/gt | +-- forcewake_user | +-- interrupt_info | \-- reset

[Intel-gfx] [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt

2021-10-08 Thread Andi Shyti
From: Andi Shyti The following interfaces: i915_wedged i915_forcewake_user i915_gem_interrupt are dependent on gt values. Put them inside gt/ and drop the "i915_" prefix name. This would be the new structure: dri/0/gt | +-- forcewake_user | +-- interrupt_info | \-- reset

[Intel-gfx] ✗ Fi.CI.BAT: failure for dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion

2021-10-08 Thread Patchwork
== Series Details == Series: dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion URL : https://patchwork.freedesktop.org/series/95605/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10699 -> Patchwork_21291

Re: [Intel-gfx] [PATCH 3/5] drm/radeon: check dri root before debugfs init

2021-10-08 Thread Das, Nirmoy
[AMD Official Use Only] I sent all the patches to dr-devel. I think there is an issue with our email server. Thunderbird is asking for a password every few minutes. https://patchwork.freedesktop.org/series/95603/ Nirmoy [sending this from my browser] From:

Re: [Intel-gfx] [PATCH 3/5] drm/radeon: check dri root before debugfs init

2021-10-08 Thread Christian König
Am 08.10.21 um 11:17 schrieb Nirmoy Das: Return early if dri minor root dentry is NULL. CC: Alex Deucher CC: "Christian König" CC: "Pan, Xinhui" Signed-off-by: Nirmoy Das Acked-by: Christian König Where are the other patches from the series? Thanks, Christian. ---

Re: [Intel-gfx] [PATCH] dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion

2021-10-08 Thread Christian König
Am 08.10.21 um 11:50 schrieb Tvrtko Ursulin: From: Tvrtko Ursulin Cache the count of shared fences in the iterator to avoid dereferencing the dma_resv_object outside the RCU protection. Otherwise iterator and its users can observe an incosistent state which makes it impossible to use safely.

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] dri: cleanup debugfs error handling

2021-10-08 Thread Patchwork
== Series Details == Series: series starting with [1/5] dri: cleanup debugfs error handling URL : https://patchwork.freedesktop.org/series/95602/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. -

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] dri: cleanup debugfs error handling

2021-10-08 Thread Patchwork
== Series Details == Series: series starting with [1/5] dri: cleanup debugfs error handling URL : https://patchwork.freedesktop.org/series/95602/ State : warning == Summary == $ dim checkpatch origin/drm-tip 59b65376d0a0 dri: cleanup debugfs error handling -:40: CHECK:PARENTHESIS_ALIGNMENT:

[Intel-gfx] [PATCH 6/6] drm/i915: Use irq work for coalescing-only dma-fence-work

2021-10-08 Thread Thomas Hellström
We are using a timeline-attached struct dma_fence_work to coalesce dma-fences on eviction. In this mode we will not have a work callback attached. Similar to how the dma-fence-chain and dma-fence-array containers do this, use irq work to signal to reduce latency. Signed-off-by: Thomas Hellström

[Intel-gfx] [PATCH 3/6] drm/i915/ttm: Failsafe migration blits

2021-10-08 Thread Thomas Hellström
If the initial fill blit or copy blit of an object fails, the old content of the data might be exposed and read as soon as either CPU- or GPU PTEs are set up to point at the pages. Intercept the blit fence with an async dma_fence_work that checks the blit fence for errors and if there are errors

[Intel-gfx] [PATCH 5/6] drm/i915/ttm: Attach the migration fence to a region timeline on eviction

2021-10-08 Thread Thomas Hellström
On eviction, TTM requires that migration fences from the same region are ordered using dma_fence_is_later(). For request-based fences we therefore need to use the same context for the migration, but now that we use a dma_fence_work for error recovery, and, in addition, might need to coalesce the

[Intel-gfx] [PATCH 4/6] drm/i915: Add a struct dma_fence_work timeline

2021-10-08 Thread Thomas Hellström
The TTM managers and, possibly, the gtt address space managers will need to be able to order fences for async operation. Using dma_fence_is_later() for this will require that the fences we hand them are from a single fence context and ordered. Introduce a struct dma_fence_work_timeline, and a

[Intel-gfx] [PATCH 2/6] drm/i915: Introduce refcounted sg-tables

2021-10-08 Thread Thomas Hellström
As we start to introduce asynchronous failsafe object migration, where we update the object state and then submit asynchronous commands we need to record what memory resources are actually used by various part of the command stream. Initially for three purposes: 1) Error capture. 2) Asynchronous

[Intel-gfx] [PATCH 1/6] drm/i915: Update dma_fence_work

2021-10-08 Thread Thomas Hellström
Move the release callback to after fence signaling to align with what's done for upcoming VM_BIND user-fence signaling. Finally call the work callback regardless of whether we have a fence error or not and update the existing callbacks accordingly. We will need this to intercept the error for

[Intel-gfx] [PATCH 0/6] drm/i915: Failsafe migration blits

2021-10-08 Thread Thomas Hellström
This patch series introduces failsafe migration blits. The reason for this seemingly strange concept is that if the initial clearing or readback of LMEM fails for some reason, and we then set up either GPU- or CPU ptes to the allocated LMEM, we can expose old contents from other clients. So after

[Intel-gfx] [PATCH 2/5] drm/i915: check dri root before debugfs init

2021-10-08 Thread Nirmoy Das
Return early if dri minor root dentry is NULL. CC: Zhenyu Wang CC: Zhi Wang CC: Jani Nikula CC: Joonas Lahtinen CC: Rodrigo Vivi CC: David Airlie CC: Daniel Vetter Signed-off-by: Nirmoy Das --- drivers/gpu/drm/i915/gvt/debugfs.c | 3 +++ drivers/gpu/drm/i915/i915_debugfs.c | 3 +++ 2

[Intel-gfx] [PATCH 1/5] dri: cleanup debugfs error handling

2021-10-08 Thread Nirmoy Das
Debugfs API returns encoded error instead of NULL. This patch cleanups drm debugfs error handling to properly set dri and its minor's root dentry to NULL. Also do not error out if dri/minor debugfs directory creation fails as a debugfs error is not a fatal error. CC: Maarten Lankhorst CC:

[Intel-gfx] [PATCH 3/5] drm/radeon: check dri root before debugfs init

2021-10-08 Thread Nirmoy Das
Return early if dri minor root dentry is NULL. CC: Alex Deucher CC: "Christian König" CC: "Pan, Xinhui" Signed-off-by: Nirmoy Das --- drivers/gpu/drm/radeon/r100.c | 9 + drivers/gpu/drm/radeon/r300.c | 3 +++ drivers/gpu/drm/radeon/r420.c | 3 +++

[Intel-gfx] [PATCH 4/5] drm/armada: check dri/crtc root before debugfs init

2021-10-08 Thread Nirmoy Das
Return early if dri minor root dentry is NULL. CC: Russell King CC: David Airlie CC: Daniel Vetter Signed-off-by: Nirmoy Das --- drivers/gpu/drm/armada/armada_debugfs.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/armada/armada_debugfs.c

[Intel-gfx] [PATCH 5/5] drm/tegra: check root dentry before debugfs init

2021-10-08 Thread Nirmoy Das
Return early if crtc or connector's debugfs root dentries are NULL. CC: Thierry Reding CC: David Airlie CC: Daniel Vetter CC: Jonathan Hunter Signed-off-by: Nirmoy Das --- drivers/gpu/drm/tegra/dc.c | 5 + drivers/gpu/drm/tegra/dsi.c | 4 drivers/gpu/drm/tegra/hdmi.c | 5 +

Re: [Intel-gfx] [PATCH 1/5] dri: cleanup debugfs error handling

2021-10-08 Thread Das, Nirmoy
[AMD Official Use Only] Thanks, Greg and Jani. So I have to do the exact opposite. We do have some NULL dentry check in the drm code. I will remove those instead. Regards, Nirmoy From: Greg KH Sent: Friday, October 8, 2021 1:07 PM To: Jani Nikula Cc: Das,

Re: [Intel-gfx] [PATCH 1/5] dri: cleanup debugfs error handling

2021-10-08 Thread Greg KH
On Fri, Oct 08, 2021 at 12:40:47PM +0300, Jani Nikula wrote: > On Fri, 08 Oct 2021, Nirmoy Das wrote: > > Debugfs API returns encoded error instead of NULL. > > This patch cleanups drm debugfs error handling to > > properly set dri and its minor's root dentry to NULL. > > > > Also do not error

Re: [Intel-gfx] [PATCH] dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion

2021-10-08 Thread Tvrtko Ursulin
On 08/10/2021 11:21, Christian König wrote: Am 08.10.21 um 11:50 schrieb Tvrtko Ursulin: From: Tvrtko Ursulin Cache the count of shared fences in the iterator to avoid dereferencing the dma_resv_object outside the RCU protection. Otherwise iterator and its users can observe an incosistent

Re: [Intel-gfx] [PATCH 04/16] drm/i915: Add all per-lane register definitions for icl combo phy

2021-10-08 Thread Ville Syrjälä
On Fri, Oct 08, 2021 at 01:21:42PM +0300, Jani Nikula wrote: > On Wed, 06 Oct 2021, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Add the FOO_LN() register macros for all the icl combo phy registers. > > Also get rid of the semi-pointless FOO_LN0() variants and just use > > the

Re: [Intel-gfx] [PATCH 06/16] drm/i915: Extract icl_combo_phy_loadgen_select()

2021-10-08 Thread Jani Nikula
On Wed, 06 Oct 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > Pull the convoluted loadgen calculation into a small helper. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 23 ++- > 1 file changed, 14

Re: [Intel-gfx] [PATCH 05/16] drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff

2021-10-08 Thread Jani Nikula
On Wed, 06 Oct 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > DKL_TX_LOADGEN_SHARING_PMD_DISABLE doesn't even seem to exist, > also the spec says to skip all loadgen stuff. > > The code was dead anyway since it wasn't actually writing the value > anywhere. > > Signed-off-by: Ville Syrjälä

Re: [Intel-gfx] [PATCH 04/16] drm/i915: Add all per-lane register definitions for icl combo phy

2021-10-08 Thread Jani Nikula
On Wed, 06 Oct 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > Add the FOO_LN() register macros for all the icl combo phy registers. > Also get rid of the semi-pointless FOO_LN0() variants and just use > the parametrized version. > > Signed-off-by: Ville Syrjälä Might argue the phy should

Re: [Intel-gfx] [PATCH 03/16] drm/i915: Use standard form terminating condition for lane for loops

2021-10-08 Thread Jani Nikula
On Wed, 06 Oct 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > Use <4 instead of <=3 as the terminating condition for the > loops over the 4 lanes. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++-- > 1 file changed, 2

Re: [Intel-gfx] [PATCH 02/16] drm/i915: Shrink {icl_mg, tgl_dkl}_phy_ddi_buf_trans

2021-10-08 Thread Jani Nikula
On Wed, 06 Oct 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > All the values we have in {icl_mg,tgl_dkl}_phy_ddi_buf_trans > fit into u8. Shrink the types accordingly. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h

Re: [Intel-gfx] [PATCH 01/16] drm/i915: Remove pointless extra namespace from dkl/snps buf trans structs

2021-10-08 Thread Jani Nikula
On Wed, 06 Oct 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > The struct itself already has sufficient namespace. No need to > duplicate it in the members. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---

Re: [Intel-gfx] [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt

2021-10-08 Thread Andi Shyti
Hi Lucas, > > I am reproposing this patch exactly as it was proposed initially > > where the original interfaces are kept where they have been > > originally placed. It might generate some duplicated code but, > > well, it's debugfs and I don't see any issue. In the future we > > can transform

[Intel-gfx] [PATCH] dma-resv: Fix dma_resv_get_fences and dma_resv_copy_fences after conversion

2021-10-08 Thread Tvrtko Ursulin
From: Tvrtko Ursulin Cache the count of shared fences in the iterator to avoid dereferencing the dma_resv_object outside the RCU protection. Otherwise iterator and its users can observe an incosistent state which makes it impossible to use safely. Such as: <6> [187.517041] [IGT] gem_sync:

Re: [Intel-gfx] [PATCH] drm/i915: Stop using I915_TILING_* in client blit selftest

2021-10-08 Thread Ville Syrjälä
On Thu, Sep 30, 2021 at 05:58:16PM -0700, Matt Roper wrote: > The I915_TILING_* definitions in the uapi header are intended solely for > tiling modes that are visible to the old de-tiling fence ioctls. Since > modern hardware does not support de-tiling fences, we should not add new > definitions

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