On 10/29/21 00:55, Matthew Brost wrote:
On Thu, Oct 28, 2021 at 02:01:27PM +0200, Thomas Hellström wrote:
With asynchronous migrations, the vma state may be several migrations
ahead of the state that matches the request we're capturing.
Address that by introducing an i915_vma_snapshot structur
== Series Details ==
Series: drm/i915/display: Check async flip state of every crtc and plane once
URL : https://patchwork.freedesktop.org/series/96402/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10809_full -> Patchwork_21480_full
===
On Thu, Oct 28, 2021 at 01:34:18PM -0700, José Roberto de Souza wrote:
> For every crtc in state, intel_atomic_check_async() was checking all
> the crtc and plane states again.
>
> Cc: Karthik B S
> Cc: Vandita Kulkarni
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> driver
On Thu, Oct 28, 2021 at 08:18:48PM +, Souza, Jose wrote:
> On Thu, 2021-10-28 at 20:46 +0300, Ville Syrjälä wrote:
> > On Thu, Oct 28, 2021 at 05:43:51PM +, Souza, Jose wrote:
> > > On Thu, 2021-10-28 at 20:38 +0300, Ville Syrjälä wrote:
> > > > On Thu, Oct 28, 2021 at 05:02:41PM +, Sou
Currently the HDMI2.1 PCON's frl link config DPCD registers are
reset and configured even if they are already configured.
Also the HDMI Link Mode does not settle to FRL MODE immediately after
HDMI Link Status is active.
This patch:
-Checks if the PCON is already configured for FRL.
-Include HDMI L
Currently we reset the whole PCON linkConfig DPCD to set the TMDS mode.
This also resets the Source control bit and HDMI link enable bit and
goes to autonomous mode of operation, which is seen to spoil the PCONs
internal state.
This patch avoids resetting the PCON link config register and sets onl
Some optimizations in HDMI2.1 PCON configuration and avoiding
resetting the config DPCD.
Ankit Nautiyal (2):
drm/i915/dp: Optimize the FRL configuration for HDMI2.1 PCON
drm/i915/dp: For PCON TMDS mode set only the relavant bits in config
DPCD
drivers/gpu/drm/i915/display/intel_dp.c | 62
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/audio: group audio under
anonymous struct in drm_i915_private
URL : https://patchwork.freedesktop.org/series/96399/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10809_full -> Patchwork_21478_full
===
== Series Details ==
Series: i915: Initial multi-tile support (rev3)
URL : https://patchwork.freedesktop.org/series/95631/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10809 -> Patchwork_21485
Summary
---
**SUCCESS*
> -Original Message-
> From: Ceraolo Spurio, Daniele
> Sent: 29 October 2021 05:41
> To: Surendrakumar Upadhyay, TejaskumarX
> ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH V2 2/2] drm/i915/gt: Hold RPM wakelock
> during PXP suspend
>
>
>
> On 10/25/2021 12:1
== Series Details ==
Series: i915: Initial multi-tile support (rev3)
URL : https://patchwork.freedesktop.org/series/95631/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1705fd0a9784 drm/i915: rework some irq functions to take intel_gt as argument
-:17: WARNING:BAD_SIGN_OFF: Non
From: Tvrtko Ursulin
Check how many extra GT tiles are available on the system and setup
register access for all of them. We can detect how may GT tiles are
available by reading a register on the root tile. The same register
returns the tile ID on all tiles.
v2:
- Include some additional refact
From: Paulo Zanoni
Loop through all the tiles when initializing and resetting interrupts.
v2:
- Access tile0 registers through dev_priv->uncore rather than
dev_priv->gt.uncore for clarity.
Signed-off-by: Paulo Zanoni
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Reviewed-by: An
From: Michał Winiarski
We now support a per-gt uncore, yet we're not able to infer which GT
we're operating upon. Let's store a backpointer for now.
Signed-off-by: Michał Winiarski
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
From: Michal Wajdeczko
Update CT debug macros by including tile ID in all messages.
Cc: Michał Winiarski
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/g
Some of our upcoming platforms, including the Xe_HP SDV, support a
"multi-tile" design. A multi-tile platform is effectively a platform
with multiple GT instances and local memory regions, all behind a single
PCI device. From an i915 perspective, this translates to multiple
intel_gt structures pe
From: Daniele Ceraolo Spurio
In coming patches we'll be doing the actual tile initialization between
these two uncore init phases.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/i915_drv.c |
From: Daniele Ceraolo Spurio
Initialization and suspend/resume is replicated per-tile.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/i915_debugfs.c |
From: Tvrtko Ursulin
Add some basic plumbing to support more than one dynamically allocated
struct intel_gt. Up to four gts are supported in i915->gts[], with slot
zero shadowing the existing i915->gt to enable source compatibility with
legacy driver paths. A for_each_gt macro is added to itera
From: Paulo Zanoni
The first step of interrupt handling is to read a tile0 register that
tells us in which tile the interrupt happened; we can then read the
usual interrupt registers from the appropriate tile.
Note that this is just the first step of handling interrupts properly on
multi-tile pl
From: Paulo Zanoni
We'll be adding multi-tile support soon; on multi-tile platforms
interrupts are per-tile and every tile has the full set of
interrupt registers.
In this commit we start passing intel_gt instead of dev_priv for the
functions that are related to Xe_HP irq handling. Right now we'
On a multi-tile platform, each tile has its own registers + GGTT space,
and BAR 0 is extended to cover all of them. Upcoming patches will start
exposing the tiles as multiple GTs within a single PCI device. In
preparation for supporting such setups, restructure the driver's probe
code a bit.
Onl
On Thu, Oct 28, 2021 at 8:42 PM Sean Paul wrote:
>
> On Tue, Oct 26, 2021 at 03:21:00PM -0400, Mark Yacoub wrote:
> > From: Mark Yacoub
> >
> > [Why]
> > This function and enum do not do generic checking on the luts but they
> > test color channels in the LUTs.
>
> I'm not sure there's anything i
On Thu, Oct 21, 2021 at 04:40:44PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> When GuC submission is enabled, GuC itself manages hang detection and
> recovery. Therefore, any test that relies on being able to trigger an
> engine reset in the driver will fail. Full GT resets
On Thu, Oct 21, 2021 at 04:40:42PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The syfs helper functions were all using basic 'int' data types for
> sizs, offsets, etc. when reading from sysfs. This works fine for
> little files, but not for large error capture logs (which c
On Thu, Oct 21, 2021 at 04:40:39PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The decode of the error capture contents was happening in two
> different sub-tests with two very different pieces of code. One being
> much more extensive than the other (actually decodes and ver
On Thu, Oct 21, 2021 at 04:40:41PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The sysfs file read helper does not actually report any errors if a
> realloc fails. It just silently returns a 'valid' but truncated
> buffer. This then leads to the decode of the buffer failing
On Thu, Oct 21, 2021 at 04:40:37PM -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The 'many' test ended with an 'assert(count)', presumably meaning to
> ensure that some objects were actually captured. However, 'count' is
> the number of objects created not how many were captur
On Tue, Oct 26, 2021 at 03:21:01PM -0400, Mark Yacoub wrote:
> From: Mark Yacoub
>
> [Why]
> 1. drm_atomic_helper_check doesn't check for the LUT sizes of either Gamma
> or Degamma props in the new CRTC state, allowing any invalid size to
> be passed on.
> 2. Each driver has its own LUT size, whi
On Tue, Oct 26, 2021 at 03:21:00PM -0400, Mark Yacoub wrote:
> From: Mark Yacoub
>
> [Why]
> This function and enum do not do generic checking on the luts but they
> test color channels in the LUTs.
I'm not sure there's anything inherently specific to channels, it seems like
one could add a new
== Series Details ==
Series: drm/i915/resets: Don't set / test for per-engine reset bits with GuC
submission
URL : https://patchwork.freedesktop.org/series/96406/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10809 -> Patchwork_21483
==
== Series Details ==
Series: Enable PXP support (rev2)
URL : https://patchwork.freedesktop.org/series/96232/
State : failure
== Summary ==
Applying: drm/i915/pxp: run CI with PXP and MEI_PXP enabled.
Applying: drm/i915/gt: Hold RPM wakelock during PXP suspend
error: git diff header lacks filen
Hi Matt,
> > > - dg1_master_intr_enable(uncore->regs);
> > > - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
> > > + dg1_master_intr_enable(dev_priv->gt.uncore->regs);
> > > + intel_uncore_posting_read(dev_priv->gt.uncore, DG1_MSTR_TILE_INTR);
> >
> > I guess this should also go under a
On 10/25/2021 12:13 AM, Tejas Upadhyay wrote:
selftest --r live shows failure in suspend tests when
RPM wakelock is not acquired during suspend.
This changes addresses below error :
<4> [154.177535] RPM wakelock ref not held during HW access
<4> [154.177575] WARNING: CPU: 4 PID: 5772 at
drive
== Series Details ==
Series: drm/i915/adlp: Implement workaround 16013190616
URL : https://patchwork.freedesktop.org/series/96405/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10809 -> Patchwork_21482
Summary
---
**
On 10/28/2021 15:42, Matthew Brost wrote:
Don't set, test for, or clear per-engine reset bits with GuC submission
as the GuC owns the per engine resets not the i915. Setting, testing
for, and clearing these bits is causing issues with the hangcheck
selftest. Rather than change to test to not use
On Thu, Oct 28, 2021 at 06:30:09PM +0200, Andi Shyti wrote:
> Hi Paulo and Matt,
>
> [...]
>
> > @@ -3190,14 +3190,19 @@ static void dg1_irq_reset(struct drm_i915_private
> > *dev_priv)
>
> mmmhhh... bad naming :/
Even though dg1 wasn't a multi-tile platform, it was the platform that
introduce
On Thu, Oct 28, 2021 at 02:01:27PM +0200, Thomas Hellström wrote:
> With asynchronous migrations, the vma state may be several migrations
> ahead of the state that matches the request we're capturing.
> Address that by introducing an i915_vma_snapshot structure that
> can be used to snapshot releva
Don't set, test for, or clear per-engine reset bits with GuC submission
as the GuC owns the per engine resets not the i915. Setting, testing
for, and clearing these bits is causing issues with the hangcheck
selftest. Rather than change to test to not use these bits, rip the use
of these bits out fr
New workaround added to specification, requiring bit 15 of
GEN8_CHICKEN_DCPR_1 to be programed before power well 1 is enabled.
BSpec: 54369
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display_power.c | 5 +
drivers/gpu/drm/i915/i915_reg.h|
== Series Details ==
Series: Prepare error capture for asynchronous migration (rev4)
URL : https://patchwork.freedesktop.org/series/96281/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10809 -> Patchwork_21481
Summary
-
== Series Details ==
Series: i915/display/dmc: Add Support for PipeC and PipeD DMC (rev2)
URL : https://patchwork.freedesktop.org/series/95532/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10807_full -> Patchwork_21477_full
== Series Details ==
Series: Prepare error capture for asynchronous migration (rev4)
URL : https://patchwork.freedesktop.org/series/96281/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9ddf9655f463 drm/i915: Introduce refcounted sg-tables
d3a3c169f330 drm/i915: Update error cap
== Series Details ==
Series: drm/i915/display: Check async flip state of every crtc and plane once
URL : https://patchwork.freedesktop.org/series/96402/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10809 -> Patchwork_21480
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/audio: group audio under
anonymous struct in drm_i915_private
URL : https://patchwork.freedesktop.org/series/96399/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10809 -> Patchwork_21478
=
== Series Details ==
Series: drm/i915/psr2: Do full fetches when doing async flips (rev3)
URL : https://patchwork.freedesktop.org/series/96357/
State : failure
== Summary ==
Applying: drm/i915/psr2: Do full fetches when doing async flips
error: sha1 information is lacking or useless
(drivers/
== Series Details ==
Series: series starting with [01/11] drm/i915: Remove unused bits of
i915_vma/active api
URL : https://patchwork.freedesktop.org/series/96388/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10807_full -> Patchwork_21476_full
===
> -Original Message-
> From: Srivatsa, Anusha
> Sent: Thursday, October 28, 2021 2:04 PM
> To: Sripada, Radhakrishna ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH v9] drm/i915: Update memory bandwidth
> formulae
>
> Replying to the right patch this time.
> From
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/audio: group audio under
anonymous struct in drm_i915_private
URL : https://patchwork.freedesktop.org/series/96399/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/audio: group audio under
anonymous struct in drm_i915_private
URL : https://patchwork.freedesktop.org/series/96399/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
99ae5429914a drm/i915/audio: group audio under
On Fri, 2021-10-22 at 21:26 +, Yokoyama, Caz wrote:
> On Wed, 2021-10-20 at 19:19 +, Souza, Jose wrote:
> > On Wed, 2021-10-20 at 15:00 +, Yokoyama, Caz wrote:
> > > On Tue, 2021-10-19 at 17:23 -0700, José Roberto de Souza wrote:
> > > > Adding a structure to standardize access to IP ve
Replying to the right patch this time.
From what the bspec says, the changes look good.
Minor feedback below inline.
With that change,
Reviewed-by: Anusha Srivatsa
> -Original Message-
> From: Intel-gfx On Behalf Of
> Radhakrishna Sripada
> Sent: Friday, October 15, 2021 2:01 PM
> To:
On Thu, 2021-10-28 at 11:27 -0700, Doug Anderson wrote:
> Hi,
>
> On Tue, Oct 26, 2021 at 3:09 PM Lyude Paul wrote:
> >
> > As it turns out, apparently some machines will actually leave additional
> > backlight functionality like dynamic backlight control on before the OS
> > loads. Currently we
For every crtc in state, intel_atomic_check_async() was checking all
the crtc and plane states again.
Cc: Karthik B S
Cc: Vandita Kulkarni
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.c | 38 ++--
1 file changed, 20 inse
On Thu, 2021-10-28 at 20:46 +0300, Ville Syrjälä wrote:
> On Thu, Oct 28, 2021 at 05:43:51PM +, Souza, Jose wrote:
> > On Thu, 2021-10-28 at 20:38 +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 28, 2021 at 05:02:41PM +, Souza, Jose wrote:
> > > > On Thu, 2021-10-28 at 16:32 +0300, Ville Syrj
On 10/27/21 6:33 PM, a...@linux-foundation.org wrote:
The mm-of-the-moment snapshot 2021-10-27-18-32 has been uploaded to
https://www.ozlabs.org/~akpm/mmotm/
mmotm-readme.txt says
README for mm-of-the-moment:
https://www.ozlabs.org/~akpm/mmotm/
This is a snapshot of my -mm patch queue.
== Series Details ==
Series: Prepare error capture for asynchronous migration (rev3)
URL : https://patchwork.freedesktop.org/series/96281/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10807_full -> Patchwork_21475_full
Sum
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/gtt: flush the scratch page
URL : https://patchwork.freedesktop.org/series/96380/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10807_full -> Patchwork_21474_full
==
With an anonymous struct, this can be pure hierarchical organization
without code changes. We'll follow up with adding a name to the
sub-struct separately.
Cc: Dave Airlie
Reviewed-by: Ville Syrjälä
Reviewed-by: Lucas De Marchi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h |
Hi,
On Tue, Oct 26, 2021 at 3:09 PM Lyude Paul wrote:
>
> As it turns out, apparently some machines will actually leave additional
> backlight functionality like dynamic backlight control on before the OS
> loads. Currently we don't take care to disable unsupported features when
> writing back th
On Thu, Oct 28, 2021 at 05:43:51PM +, Souza, Jose wrote:
> On Thu, 2021-10-28 at 20:38 +0300, Ville Syrjälä wrote:
> > On Thu, Oct 28, 2021 at 05:02:41PM +, Souza, Jose wrote:
> > > On Thu, 2021-10-28 at 16:32 +0300, Ville Syrjälä wrote:
> > > > On Wed, Oct 27, 2021 at 11:48:55AM -0700, Jos
On Thu, 2021-10-28 at 20:38 +0300, Ville Syrjälä wrote:
> On Thu, Oct 28, 2021 at 05:02:41PM +, Souza, Jose wrote:
> > On Thu, 2021-10-28 at 16:32 +0300, Ville Syrjälä wrote:
> > > On Wed, Oct 27, 2021 at 11:48:55AM -0700, José Roberto de Souza wrote:
> > > > Async flips are not supported by se
On Wed, 06 Oct 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Our lane power down defines already include the necessary shift,
> don't shit them a second time.
*chuckle*
>
> Fortunately we masked off the correct bits, so we accidentally
> left all lanes powered up all the time.
>
> Bits 8
On Thu, Oct 28, 2021 at 05:02:41PM +, Souza, Jose wrote:
> On Thu, 2021-10-28 at 16:32 +0300, Ville Syrjälä wrote:
> > On Wed, Oct 27, 2021 at 11:48:55AM -0700, José Roberto de Souza wrote:
> > > Async flips are not supported by selective fetch and we had a check
> > > for that but that check w
On Fri, 22 Oct 2021, Jani Nikula wrote:
> On Fri, 22 Oct 2021, Ville Syrjälä wrote:
>> On Fri, Oct 22, 2021 at 07:27:57PM +0300, Jani Nikula wrote:
>>> Add a standalone definition of struct intel_audio_private, and note that
>>> all of it is private to intel_audio.c.
>>>
>>> Cc: Dave Airlie
>>>
On Fri, 22 Oct 2021, Lucas De Marchi wrote:
> On Fri, Oct 22, 2021 at 07:27:55PM +0300, Jani Nikula wrote:
>>With an anonymous struct, this can be pure hierarchical organization
>>without code changes.
>
> start reading from patch 1 left me confused. A sentence here that next
> patches will add th
Follow the filename based prefix naming.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_audio.c | 4 ++--
drivers/gpu/drm/i915/display/intel_audio.h | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/
Unify audio init/cleanup paths wrt LPE audio, and base the logic on the
return values from LPE audio calls. Move the platform device check on
cleanup to intel_lpe_audio.c, thereby limiting all audio.lpe substruct
access to that file.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/in
It's all internal to intel_audio.c.
Cc: Dave Airlie
Reviewed-by: Ville Syrjälä
Reviewed-by: Lucas De Marchi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_audio.c | 9 +
drivers/gpu/drm/i915/i915_drv.h| 10 +-
2 files changed, 10 insertions(+),
Add a standalone definition of struct intel_audio_private, and note that
all of it is private to intel_audio.c.
v2: Rebase
Cc: Dave Airlie
Reviewed-by: Ville Syrjälä
Reviewed-by: Lucas De Marchi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 45 ++---
Add name to the audio sub-struct in drm_i915_private, and remove the
tautologies and other inconsistencies in the member names.
v2: Call the mutex member mutex, not lock. (Ville)
Cc: Dave Airlie
Reviewed-by: Ville Syrjälä
Reviewed-by: Lucas De Marchi
Signed-off-by: Jani Nikula
---
drivers/gp
On Thu, 2021-10-28 at 16:32 +0300, Ville Syrjälä wrote:
> On Wed, Oct 27, 2021 at 11:48:55AM -0700, José Roberto de Souza wrote:
> > Async flips are not supported by selective fetch and we had a check
> > for that but that check was only executed when doing modesets.
> > So moving this check to the
== Series Details ==
Series: i915/display/dmc: Add Support for PipeC and PipeD DMC (rev2)
URL : https://patchwork.freedesktop.org/series/95532/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10807 -> Patchwork_21477
Summary
== Series Details ==
Series: Enable MIPI DSI video mode on ADLP (rev3)
URL : https://patchwork.freedesktop.org/series/95928/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10806_full -> Patchwork_21472_full
Summary
---
== Series Details ==
Series: series starting with [01/11] drm/i915: Remove unused bits of
i915_vma/active api
URL : https://patchwork.freedesktop.org/series/96388/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10807 -> Patchwork_21476
=
On Wed, Oct 27, 2021 at 12:09 AM Lyude Paul wrote:
>
> Since we don't support hybrid AUX/PWM backlights in nouveau right now,
> let's add some explicit checks so that we don't break nouveau once we
> enable support for these backlights in other drivers.
>
> Signed-off-by: Lyude Paul
> ---
> driv
== Series Details ==
Series: series starting with [01/11] drm/i915: Remove unused bits of
i915_vma/active api
URL : https://patchwork.freedesktop.org/series/96388/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be chec
== Series Details ==
Series: series starting with [01/11] drm/i915: Remove unused bits of
i915_vma/active api
URL : https://patchwork.freedesktop.org/series/96388/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
519f1b79715b drm/i915: Remove unused bits of i915_vma/active api
85
On Fri, Oct 22, 2021 at 09:39:13AM +0100, Matthew Auld wrote:
> On Fri, 22 Oct 2021 at 09:22, Daniel Vetter wrote:
> >
> > Gone with userptr rewrite by Maarten in ed29c2691188 ("drm/i915: Fix
> > userptr so we do not have to worry about obj->mm.lock, v7.")
> >
> > Signed-off-by: Daniel Vetter
> >
On Thu, Oct 21, 2021 at 01:53:32PM +0100, Matthew Auld wrote:
> We were overzealous here; even though discrete is non-LLC, it should
> still be always coherent.
>
> Signed-off-by: Matthew Auld
> Cc: Thomas Hellström
> ---
> drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 3 ++-
> 1 file changed, 2
On Thu, Oct 28, 2021 at 10:41:38AM +0200, Christian König wrote:
> Am 21.10.21 um 13:13 schrieb Tvrtko Ursulin:
> >
> > On 21/10/2021 12:06, Maarten Lankhorst wrote:
> > > Op 21-10-2021 om 12:38 schreef Christian König:
> > > > Am 21.10.21 um 12:35 schrieb Maarten Lankhorst:
> > > > > From: Christ
On Fri, Oct 22, 2021 at 03:17:17PM +0200, Christian König wrote:
> Am 13.10.21 um 16:29 schrieb Daniel Vetter:
> > On Tue, Oct 05, 2021 at 01:37:40PM +0200, Christian König wrote:
> > > Makes the handling a bit more complex, but avoids the use of
> > > dma_resv_get_excl_unlocked().
> > >
> > > Sig
== Series Details ==
Series: Prepare error capture for asynchronous migration (rev3)
URL : https://patchwork.freedesktop.org/series/96281/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10807 -> Patchwork_21475
Summary
-
On Thu, Oct 28, 2021 at 04:53:22PM +0300, Kulkarni, Vandita wrote:
> > -Original Message-
> > From: Deak, Imre
> > Sent: Saturday, October 23, 2021 1:53 AM
> > To: Kulkarni, Vandita
> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
> > Roper, Matthew D ;
> > ville.syrj...@linux.inte
== Series Details ==
Series: Prepare error capture for asynchronous migration (rev3)
URL : https://patchwork.freedesktop.org/series/96281/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3ed5872716e5 drm/i915: Introduce refcounted sg-tables
8fb7f2296aa8 drm/i915: Update error cap
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, October 28, 2021 8:06 PM
> To: Kulkarni, Vandita ; intel-
> g...@lists.freedesktop.org
> Cc: Deak, Imre ; Roper, Matthew D
> ; ville.syrj...@linux.intel.com
> Subject: RE: [V2 4/4] drm/i915/dsi: Ungate clock before enabling the ph
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/gtt: flush the scratch page
URL : https://patchwork.freedesktop.org/series/96380/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10807 -> Patchwork_21474
Su
On Thu, 28 Oct 2021, "Kulkarni, Vandita" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Thursday, October 28, 2021 5:13 PM
>> To: Kulkarni, Vandita ; intel-
>> g...@lists.freedesktop.org
>> Cc: Deak, Imre ; Roper, Matthew D
>> ; ville.syrj...@linux.intel.com; Kulkarni,
>> Van
On Thu, 28 Oct 2021, Ville Syrjälä wrote:
> On Thu, Oct 28, 2021 at 01:29:21PM +0300, Jani Nikula wrote:
>>
>> Hi Dave & Daniel -
>>
>> Certainly more than I'd like at this stage, but it's mostly Cc: stable
>> material, and the tracepoint change is a last minute revert to dodge a
>> potential "t
look ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 26.10.2021 19.15, Imre Deak wrote:
To simplify the handling of modifiers on DG2 and future platforms it
makes sense to fold the modifier tiling and CCS type attributes to the
plane capabilities mask. This patchset does that, also including fix
== Series Details ==
Series: drm/i915/gem: Don't try to map and fence 8K/bigjoiner scanout buffers
(rev2)
URL : https://patchwork.freedesktop.org/series/96279/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10807 -> Patchwork_21473
=
On Thu, Oct 28, 2021 at 04:59:28PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 28, 2021 at 04:54:19PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Oct 28, 2021 at 04:03:32PM +0300, Ville Syrjälä wrote:
> > > On Wed, Oct 27, 2021 at 08:11:37PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Mon, Oct 1
On Thu, Oct 28, 2021 at 04:54:19PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Oct 28, 2021 at 04:03:32PM +0300, Ville Syrjälä wrote:
> > On Wed, Oct 27, 2021 at 08:11:37PM +0300, Lisovskiy, Stanislav wrote:
> > > On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> > > > From: Ville S
On Thu, Oct 28, 2021 at 04:03:32PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 27, 2021 at 08:11:37PM +0300, Lisovskiy, Stanislav wrote:
> > On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Chop skl_program_plane() into two halves. Fist half becom
> -Original Message-
> From: Deak, Imre
> Sent: Saturday, October 23, 2021 1:53 AM
> To: Kulkarni, Vandita
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
> Roper, Matthew D ;
> ville.syrj...@linux.intel.com
> Subject: Re: [V2 3/4] drm/i915/dsi/xelpd: Disable DC states in Video mode
On Wed, Oct 27, 2021 at 11:48:55AM -0700, José Roberto de Souza wrote:
> Async flips are not supported by selective fetch and we had a check
> for that but that check was only executed when doing modesets.
> So moving this check to the page flip path, so it can be properly
> handled.
>
> This fix
On Wed, Oct 06, 2021 at 11:49:37PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Our lane power down defines already include the necessary shift,
> don't shit them a second time.
>
> Fortunately we masked off the correct bits, so we accidentally
> left all lanes powered up all the time.
On Thu, Oct 28, 2021 at 01:29:21PM +0300, Jani Nikula wrote:
>
> Hi Dave & Daniel -
>
> Certainly more than I'd like at this stage, but it's mostly Cc: stable
> material, and the tracepoint change is a last minute revert to dodge a
> potential "tracepoints are uabi" bullet before it hits the fina
On Wed, Oct 27, 2021 at 08:11:37PM +0300, Lisovskiy, Stanislav wrote:
> On Mon, Oct 18, 2021 at 02:50:26PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Chop skl_program_plane() into two halves. Fist half becomes
> > the _noarm() variant, second part the _arm() variant.
> >
> > For
From: Maarten Lankhorst
TTM already requires this, and we require it for delayed destroy.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matthew Auld
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu
1 - 100 of 146 matches
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