== Series Details ==
Series: Splitting intel-gtt calls for non-x86 platforms
URL : https://patchwork.freedesktop.org/series/101552/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11385_full -> Patchwork_22618_full
Summary
On Fri, Mar 18, 2022 at 07:00:41PM -0700, Casey Bowman wrote:
The intel-gtt module is not used on other, non-x86 platforms, so we
will restrict it to x86 platforms only.
Signed-off-by: Casey Bowman
this should probably be the second patch, not the first.
Reviewed-by: Lucas De Marchi
On Fri, Mar 18, 2022 at 07:00:42PM -0700, Casey Bowman wrote:
Some functions defined in the intel-gtt module are used in several
areas, but is only supported on x86 platforms.
By separating these calls and their static underlying functions to
area, we are able to compile out these functions for
== Series Details ==
Series: Splitting intel-gtt calls for non-x86 platforms
URL : https://patchwork.freedesktop.org/series/101552/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11385 -> Patchwork_22618
Summary
---
== Series Details ==
Series: Splitting intel-gtt calls for non-x86 platforms
URL : https://patchwork.freedesktop.org/series/101552/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Splitting intel-gtt calls for non-x86 platforms
URL : https://patchwork.freedesktop.org/series/101552/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
71b8a3999b05 drm/i915: Require INTEL_GTT to depend on X86
6fb28942812c drm/i915/gt: Split intel-gtt
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101551/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11384_full -> Patchwork_22617_full
Summary
---
The intel-gtt module is not used on other, non-x86 platforms, so we
will restrict it to x86 platforms only.
Signed-off-by: Casey Bowman
---
drivers/gpu/drm/i915/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/Kconfig
Some functions defined in the intel-gtt module are used in several
areas, but is only supported on x86 platforms.
By separating these calls and their static underlying functions to
area, we are able to compile out these functions for non-x86 builds
and provide stubs for the non-x86
The intel-gtt module defines some functions used by i915, but they are
only supported by x86 platforms. In order to bring i915 to a more
arch-neutral state, we split out these functions and provide stubs in
the case of non-x86 builds.
There may be a better filename choice for the files used in
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101549/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11384_full -> Patchwork_22616_full
Summary
---
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11384 -> Patchwork_22617
Summary
---
**SUCCESS**
No
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101551/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101549/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11384 -> Patchwork_22616
Summary
---
**SUCCESS**
No
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101551/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e394242076f2 drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0
e56e16681fc9 drm/i915/gt: add gt_is_root()
From: Sujaritha Sundaresan
Throttling here refers to the GT frequency being clipped. Each of
the throttle reason attributes will have a 0 or 1 value depending
upon whether there is throttling and also the specific reason for
it.
The following is a brief description of the sysfs throttle
Now tiles have their own sysfs interfaces under the gt/
directory. Because RPS is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│
Now tiles have their own sysfs interfaces under the gt/
directory. Because RC6 is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│
Now that we have tiles we want each of them to have its own
interface. A directory "gt/" is created under "cardN/" that will
contain as many diroctories as the tiles.
In the coming patches tile related interfaces will be added. For
now the sysfs gt structure simply has an id interface related
to
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compatibility
with legacy driver paths. A
Hi,
This is the second series that prepares i915 to host multitile
platforms. It introduces the for_each_gt() macro that loops over
the tiles to perform per gt actions.
This patch is a combination of two patches developed originally
by Abdiel, who introduced some refactoring during probe, and
The "gt_is_root(struct intel_gt *gt)" helper return true if the
gt is the root gt, which means that its id is 0. Return false
otherwise.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/intel_gt.h |
With the upcoming multitile support each tile will have its own
local memory. Mark the current LMEM with the suffix '0' to
emphasise that it belongs to the root tile.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
---
Arghhh Sorry for spamming! I sent the wrong series!
Please ignore this.
Andi
On Sat, Mar 19, 2022 at 12:46:33AM +0200, Andi Shyti wrote:
> Hi,
>
> This is the second series that prepares i915 to host multitile
> platforms. It introduces the for_each_gt() macro that loops over
> the tiles
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101549/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101549/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ac3a14b22f9a drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0
373961700ada drm/i915/gt: add gt_is_root()
From: Sujaritha Sundaresan
This patch adds the following new sysfs frequency attributes:
- punit_req_freq_mhz
- throttle_reason_status
- throttle_reason_pl1
- throttle_reason_pl2
- throttle_reason_pl4
- throttle_reason_thermal
-
Now tiles have their own sysfs interfaces under the gt/
directory. Because RPS is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│
Now tiles have their own sysfs interfaces under the gt/
directory. Because RC6 is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│
Now that we have tiles we want each of them to have its own
interface. A directory "gt/" is created under "cardN/" that will
contain as many diroctories as the tiles.
In the coming patches tile related interfaces will be added. For
now the sysfs gt structure simply has an id interface related
to
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compatibility
with legacy driver paths. A
The "gt_is_root(struct intel_gt *gt)" helper return true if the
gt is the root gt, which means that its id is 0. Return false
otherwise.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/i915/gt/intel_gt.h |
With the upcoming multitile support each tile will have its own
local memory. Mark the current LMEM with the suffix '0' to
emphasise that it belongs to the root tile.
Suggested-by: Michal Wajdeczko
Signed-off-by: Andi Shyti
Reviewed-by: Michal Wajdeczko
Reviewed-by: Andrzej Hajda
---
Hi,
This is the second series that prepares i915 to host multitile
platforms. It introduces the for_each_gt() macro that loops over
the tiles to perform per gt actions.
This patch is a combination of two patches developed originally
by Abdiel, who introduced some refactoring during probe, and
== Series Details ==
Series: drm/i915: avoid concurrent writes to aux_inv (rev8)
URL : https://patchwork.freedesktop.org/series/100772/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11382_full -> Patchwork_22614_full
On Fri, Mar 18, 2022 at 12:55:21PM -0700, José Roberto de Souza wrote:
> This will make easy to extend MBUS joining support to future platforms
> that also supports this feature.
>
> Signed-off-by: José Roberto de Souza
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2
On Fri, Mar 18, 2022 at 12:55:22PM -0700, José Roberto de Souza wrote:
> PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
> enabled leaving other pipes with a wrong A_CREDIT value in cases
> like when going from one pipe enabled to two pipes and the first
> pipe don't need
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL
with adl-p values
URL : https://patchwork.freedesktop.org/series/101545/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11383 -> Patchwork_22615
== Series Details ==
Series: series starting with [1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL
with adl-p values
URL : https://patchwork.freedesktop.org/series/101545/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit
This will make easy to extend MBUS joining support to future platforms
that also supports this feature.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git
PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
enabled leaving other pipes with a wrong A_CREDIT value in cases
like when going from one pipe enabled to two pipes and the first
pipe don't need modeset, similar when going from two or more
pipes to ones.
So here moving the
From: Caz Yokoyama
B credits set by IFWI do not match with specification default, so here
programming the right value.
Also while at it, taking the oportunity to do a read-modify-write to
all other bit in this register that specification don't ask us to
change.
BSpec: 49213
BSpec: 50343
Cc:
== Series Details ==
Series: drm/i915: avoid concurrent writes to aux_inv (rev8)
URL : https://patchwork.freedesktop.org/series/100772/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11382 -> Patchwork_22614
Summary
---
Yes, I have re-opened the issue #3812 and re-reported.
-Original Message-
From: Roper, Matthew D
Sent: Friday, March 18, 2022 10:21 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana
Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/dg2: Add preemption changes for
== Series Details ==
Series: drm/i915/dg2: Add preemption changes for Wa_14015141709 (rev2)
URL : https://patchwork.freedesktop.org/series/101023/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11379_full -> Patchwork_22602_full
From: Fei Yang
GPU hangs have been observed when multiple engines write to the
same aux_inv register at the same time. To avoid this each engine
should only invalidate its own auxiliary table. The function
gen12_emit_flush_xcs() currently invalidate the auxiliary table for
all engines because
>> static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
>> {
>> *cs++ = MI_LOAD_REGISTER_IMM(1);
>> @@ -296,7 +272,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32
>> mode)
>> if (!HAS_FLAT_CCS(rq->engine->i915)) {
>> aux_inv
Maybe also good to add dri-devel to these discussions.
I'm not sure where exactly we landed with dgpu error capture (maybe I
should check the code but it's really w/e here), but I think we can
also toss in "you need a non-recoverable context for error capture to
work on dgpu". Since that
== Series Details ==
Series: Add CDCLK checks to atomic check phase (rev5)
URL : https://patchwork.freedesktop.org/series/101068/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11381 -> Patchwork_22613
Summary
---
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix renamed struct field (rev2)
URL : https://patchwork.freedesktop.org/series/101448/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11380_full -> Patchwork_22611_full
On Thu, Feb 17, 2022 at 05:15:15PM +, Chery, Nanley G wrote:
> > >> [...]
> > >> --- a/include/uapi/drm/drm_fourcc.h
> > >> +++ b/include/uapi/drm/drm_fourcc.h
> > >> @@ -583,6 +583,28 @@ extern "C" {
> > >>*/
> > >> #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
> >
== Series Details ==
Series: Add CDCLK checks to atomic check phase (rev5)
URL : https://patchwork.freedesktop.org/series/101068/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Add CDCLK checks to atomic check phase (rev5)
URL : https://patchwork.freedesktop.org/series/101068/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
29531a1812df drm/i915/display: Add CDCLK actions to intel_cdclk_state
f19caadb81b6 drm/i915/display:
On Fri, Mar 18, 2022 at 04:51:14AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dg2: Add preemption changes for Wa_14015141709 (rev2)
> URL : https://patchwork.freedesktop.org/series/101023/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
@Thomas Hellström - I agree :-)
My question was really to @Joonas Lahtinen, who was saying we could always
migrate in the CPU fault handler. I am pushing back on that unless we have no
choice. It's the very complication we were trying to avoid with the current
SAS. If that's what's needed,
Regression is related to https://gitlab.freedesktop.org/drm/intel/-/issues/4391
All tests - dmesg-warn/dmesg-fail - *ERROR* AUX B/DDI B/PHY B: did not complete
or timeout within 10ms (status 0xad4003ff)
Re-reported the results.
Lakshmi.
-Original Message-
From: De Marchi, Lucas
Sent:
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix renamed struct field (rev2)
URL : https://patchwork.freedesktop.org/series/101448/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11380 -> Patchwork_22611
On Tue, Mar 15, 2022 at 01:51:22PM -0700, José Roberto de Souza wrote:
> A few more updates in the alderlake-P voltage swing tables.
>
> eDP HBR3 table was the same as icelake one but now it has changes for
> voltage 0 and pre-emphasis 2 line.
> And DP tables also had one line change in each.
>
On 18.03.2022 03:10, Andi Shyti wrote:
Now that we have tiles we want each of them to have its own
interface. A directory "gt/" is created under "cardN/" that will
contain as many diroctories as the tiles.
In the coming patches tile related interfaces will be added. For
now the sysfs gt
On Fri, Mar 18, 2022 at 11:19:46AM +0200, Jani Nikula wrote:
On Thu, 17 Mar 2022, Lucas De Marchi wrote:
On Thu, Mar 17, 2022 at 08:36:14PM +0200, Jani Nikula wrote:
Start localizing DMC register and data access to intel_dmc.c.
Signed-off-by: Jani Nikula
---
On 18.03.2022 03:10, Andi Shyti wrote:
Now tiles have their own sysfs interfaces under the gt/
directory. Because RPS is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
On Thu, Mar 17, 2022 at 04:14:16AM +, Patchwork wrote:
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix renamed struct field
URL : https://patchwork.freedesktop.org/series/101448/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11372_full ->
On Fri, Mar 18, 2022 at 04:38:27PM +0200, Souza, Jose wrote:
> On Fri, 2022-03-18 at 16:19 +0200, Lisovskiy, Stanislav wrote:
> > On Fri, Mar 18, 2022 at 02:21:10PM +0200, Souza, Jose wrote:
> > > On Fri, 2022-03-18 at 10:52 +0200, Stanislav Lisovskiy wrote:
> > > > We are currently getting FIFO
On Fri, 2022-03-18 at 16:22 +0200, Lisovskiy, Stanislav wrote:
> On Fri, Mar 18, 2022 at 02:27:53PM +0200, Souza, Jose wrote:
> > On Fri, 2022-03-18 at 05:22 -0700, José Roberto de Souza wrote:
> > > On Fri, 2022-03-18 at 10:52 +0200, Stanislav Lisovskiy wrote:
> > > > We are currently getting
On 18/03/2022 05:26, fei.y...@intel.com wrote:
From: Fei Yang
GPU hangs have been observed when multiple engines write to the
same aux_inv register at the same time. To avoid this each engine
should only invalidate its own auxiliary table. The function
gen12_emit_flush_xcs() currently
On Fri, 2022-03-18 at 16:19 +0200, Lisovskiy, Stanislav wrote:
> On Fri, Mar 18, 2022 at 02:21:10PM +0200, Souza, Jose wrote:
> > On Fri, 2022-03-18 at 10:52 +0200, Stanislav Lisovskiy wrote:
> > > We are currently getting FIFO underruns, in particular
> > > when PSR2 is enabled. There seem to be
Hi Matt and Tvrtko,
> On 18/03/2022 13:25, Matthew Auld wrote:
> > On Fri, 18 Mar 2022 at 08:18, Andi Shyti wrote:
> > >
> > > >• igt@i915_selftest@mock@requests:
> > > >
> > > >□ shard-kbl: PASS -> DMESG-FAIL
> > > >
> > > >□ shard-tglb: PASS -> DMESG-FAIL
> > > >
> > >
On Fri, Mar 18, 2022 at 02:27:53PM +0200, Souza, Jose wrote:
> On Fri, 2022-03-18 at 05:22 -0700, José Roberto de Souza wrote:
> > On Fri, 2022-03-18 at 10:52 +0200, Stanislav Lisovskiy wrote:
> > > We are currently getting FIFO underruns, in particular
> > > when PSR2 is enabled. There seem to be
On Fri, Mar 18, 2022 at 02:21:10PM +0200, Souza, Jose wrote:
> On Fri, 2022-03-18 at 10:52 +0200, Stanislav Lisovskiy wrote:
> > We are currently getting FIFO underruns, in particular
> > when PSR2 is enabled. There seem to be no existing workaround
> > or patches, which can fix that issue(were
On Fri, Mar 18, 2022 at 01:19:18PM +, Matthew Auld wrote:
> On 18/03/2022 02:10, Andi Shyti wrote:
> > Now that we have tiles we want each of them to have its own
> > interface. A directory "gt/" is created under "cardN/" that will
> > contain as many diroctories as the tiles.
> >
> > In the
On 18/03/2022 13:25, Matthew Auld wrote:
On Fri, 18 Mar 2022 at 08:18, Andi Shyti wrote:
• igt@i915_selftest@mock@requests:
□ shard-kbl: PASS -> DMESG-FAIL
□ shard-tglb: PASS -> DMESG-FAIL
□ shard-apl: PASS -> DMESG-FAIL
□ shard-glk: PASS -> DMESG-FAIL
On Fri, 18 Mar 2022 at 08:18, Andi Shyti wrote:
>
> > • igt@i915_selftest@mock@requests:
> >
> > □ shard-kbl: PASS -> DMESG-FAIL
> >
> > □ shard-tglb: PASS -> DMESG-FAIL
> >
> > □ shard-apl: PASS -> DMESG-FAIL
> >
> > □ shard-glk: PASS -> DMESG-FAIL
> >
> > □
On 18/03/2022 02:10, Andi Shyti wrote:
Now that we have tiles we want each of them to have its own
interface. A directory "gt/" is created under "cardN/" that will
contain as many diroctories as the tiles.
In the coming patches tile related interfaces will be added. For
now the sysfs gt
On 18.03.2022 03:10, Andi Shyti wrote:
From: Sujaritha Sundaresan
This patch adds the following new sysfs frequency attributes:
- punit_req_freq_mhz
- throttle_reason_status
- throttle_reason_pl1
- throttle_reason_pl2
- throttle_reason_pl4
-
On 18.03.2022 03:10, Andi Shyti wrote:
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source
== Series Details ==
Series: drm/i915/adl_p: Increase CDCLK by 15% if PSR2 is used
URL : https://patchwork.freedesktop.org/series/101533/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11380_full -> Patchwork_22612_full
On Fri, 2022-03-18 at 05:22 -0700, José Roberto de Souza wrote:
> On Fri, 2022-03-18 at 10:52 +0200, Stanislav Lisovskiy wrote:
> > We are currently getting FIFO underruns, in particular
> > when PSR2 is enabled. There seem to be no existing workaround
> > or patches, which can fix that issue(were
On Fri, 2022-03-18 at 10:52 +0200, Stanislav Lisovskiy wrote:
> We are currently getting FIFO underruns, in particular
> when PSR2 is enabled. There seem to be no existing workaround
> or patches, which can fix that issue(were expecting some recent
> selective fetch update and DBuf bw/SAGV fixes
== Series Details ==
Series: drm/i915/adl_p: Increase CDCLK by 15% if PSR2 is used
URL : https://patchwork.freedesktop.org/series/101533/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11380 -> Patchwork_22612
Summary
== Series Details ==
Series: Separate panel orientation property creating and value setting
URL : https://patchwork.freedesktop.org/series/101530/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11380_full -> Patchwork_22608_full
On Thu, Mar 17, 2022 at 06:52:28PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 17, 2022 at 06:33:53PM +0200, Stanislav Lisovskiy wrote:
> > Whenever we are not able to get enough timeslots
> > for required PBN, let's try to allocate those
> > using DSC, just same way as we do for SST.
> >
> > Those
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix renamed struct field (rev2)
URL : https://patchwork.freedesktop.org/series/101448/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11380 -> Patchwork_22611
On 18/03/2022 09:38, Lionel Landwerlin wrote:
Hey Matthew, all,
This sounds like a good thing to have.
There are a number of DG2 machines where we have a small BAR and this is
causing more apps to fail.
Anv currently reports 3 memory heaps to the app :
- local device only (not host
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix renamed struct field (rev2)
URL : https://patchwork.freedesktop.org/series/101448/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix renamed struct field (rev2)
URL : https://patchwork.freedesktop.org/series/101448/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b789e48254b8 drm/i915: Fix renamed struct field
-:28: CHECK:MACRO_ARG_REUSE:
== Series Details ==
Series: Async flip optimization for DG2 (rev10)
URL : https://patchwork.freedesktop.org/series/98981/
State : failure
== Summary ==
Applying: drm/i915: Pass plane to watermark calculation functions
Using index info to reconstruct a base tree...
M
== Series Details ==
Series: Async flip optimization for DG2 (rev10)
URL : https://patchwork.freedesktop.org/series/98981/
State : failure
== Summary ==
Applying: drm/i915: Pass plane to watermark calculation functions
Using index info to reconstruct a base tree...
M
Hi,
On Thu, 2022-03-17 at 18:21 +, Bloomfield, Jon wrote:
> +@Vetter, Daniel
>
> Let's not start re-inventing this on the fly again. That's how we got
> into trouble in the past. The SAS/Whitepaper does currently require
> the SMEM+LMEM placement for mappable, for good reasons.
Just to
On Fri, 18 Mar 2022, Ville Syrjälä wrote:
> On Thu, Mar 17, 2022 at 09:02:46PM +0200, Jani Nikula wrote:
>> On Thu, 17 Mar 2022, Ville Syrjala wrote:
>> > From: Ville Syrjälä
>> >
>> > Make a copy of each VB data block with a guaranteed minimum
>> > size. The extra (if any) will just be left
On 18/03/2022 07:39, Kasireddy, Vivek wrote:
Hi Tvrtko,
On 17/03/2022 07:23, Vivek Kasireddy wrote:
On platforms capable of allowing 8K (7680 x 4320) modes, pinning 2 or
more framebuffers/scanout buffers results in only one that is mappable/
fenceable. Therefore, pageflipping between these
Hey Matthew, all,
This sounds like a good thing to have.
There are a number of DG2 machines where we have a small BAR and this is
causing more apps to fail.
Anv currently reports 3 memory heaps to the app :
- local device only (not host visible) -> mapped to lmem
- device/cpu ->
== Series Details ==
Series: Separate panel orientation property creating and value setting
URL : https://patchwork.freedesktop.org/series/101530/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11380 -> Patchwork_22608
== Series Details ==
Series: Add GuC Error Capture Support
URL : https://patchwork.freedesktop.org/series/101527/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11380_full -> Patchwork_22607_full
Summary
---
On Thu, 17 Mar 2022, Lucas De Marchi wrote:
> On Thu, Mar 17, 2022 at 08:36:17PM +0200, Jani Nikula wrote:
>>Register the DMC debugfs file only on platforms that support
>>DMC. There's no point in having a no-op debugfs file.
>
> It seems this would not change much the behavior (fail on open vs
On 17.3.2022 13.55, Matthew Auld wrote:
On Wed, 16 Mar 2022 at 22:23, Juha-Pekka Heikkila
wrote:
Add fallback smem allocation for dpt if stolen memory
allocation failed.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_dpt.c | 18 ++
1 file
On Thu, 17 Mar 2022, Lucas De Marchi wrote:
> On Thu, Mar 17, 2022 at 08:36:16PM +0200, Jani Nikula wrote:
>>i915_reg_t is supposed to be a somewhat opaque data type, not to be
>>looked inside.
>>
>>Signed-off-by: Jani Nikula
>
>
> Reviewed-by: Lucas De Marchi
>
> but maybe also already clean
On Thu, 17 Mar 2022, Lucas De Marchi wrote:
> On Thu, Mar 17, 2022 at 08:36:14PM +0200, Jani Nikula wrote:
>>Start localizing DMC register and data access to intel_dmc.c.
>>
>>Signed-off-by: Jani Nikula
>>---
>> drivers/gpu/drm/i915/display/intel_display_power.c | 12
>>
== Series Details ==
Series: Separate panel orientation property creating and value setting
URL : https://patchwork.freedesktop.org/series/101530/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Separate panel orientation property creating and value setting
URL : https://patchwork.freedesktop.org/series/101530/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e49373f13754 gpu: drm: separate panel orientation property creating and value
We are currently getting FIFO underruns, in particular
when PSR2 is enabled. There seem to be no existing workaround
or patches, which can fix that issue(were expecting some recent
selective fetch update and DBuf bw/SAGV fixes to help,
which unfortunately didn't).
Current idea is that it looks
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