Re: [Intel-gfx] [PATCH 1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS

On 3/24/22 18:21, Matthew Auld wrote: We only need this when allocating device local-memory, where this influences the drm_buddy. Currently there is some funny behaviour where an "in limbo" system memory object is lacking the relevant placement flags etc. before we first allocate the ttm_tt, le

Re: [Intel-gfx] [PATCH 2/2] drm/i915/migrate: move the sanity check

On 3/24/22 18:21, Matthew Auld wrote: Move the sanity check that both src and dst are never both system memory, which should never happen on discrete, and likely means we have a bug. The only exception is on integrated where we trigger this path in the selftests. Signed-off-by: Matthew Auld C

Re: [Intel-gfx] [PATCH i-g-t 4/4] tests/gem_lmem_swapping: reduce the timeout

On 3/24/22 15:26, Matthew Auld wrote: 300s is way too much for some BAT test. Drop it down to 45s. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Nirmoy Das --- tests/i915/gem_lmem_swapping.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/i915/gem_lmem_sw

Re: [Intel-gfx] [PATCH i-g-t 1/4] test/gem_lmem_swapping: account for object rounding

On Thu, 2022-03-24 at 14:26 +, Matthew Auld wrote: > On DG2 the object size might be rounded when allocating lmem. Make > sure > we account for any rounding up. > > Signed-off-by: Matthew Auld > Cc: Thomas Hellström > Cc: Nirmoy Das Reviewed-by: Thomas Hellström > --- >  tests/i915/gem_lm

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 3/4] tests/gem_lmem_swapping: limit lmem to 4G

On 24/03/2022 17:47, Dixit, Ashutosh wrote: On Thu, 24 Mar 2022 07:26:20 -0700, Matthew Auld wrote: @@ -554,6 +560,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL) igt_fixture { free(regions); close(i915); + igt_i915_driver_

Re: [Intel-gfx] [RFC] drm/i915: Split out intel_vtd_active and run_as_guest to own header

On 24/03/2022 18:57, Jani Nikula wrote: On Thu, 24 Mar 2022, Tvrtko Ursulin wrote: On 24/03/2022 11:57, Jani Nikula wrote: On Thu, 24 Mar 2022, Tvrtko Ursulin wrote: On 24/03/2022 09:31, Jani Nikula wrote: On Tue, 22 Mar 2022, Tvrtko Ursulin wrote: From: Tvrtko Ursulin ... Signed-off

[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS (rev2) URL : https://patchwork.freedesktop.org/series/101749/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.

Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch

On Thu, 2022-03-24 at 11:13 -0700, José Roberto de Souza wrote: > Following up what was done in commit 804f46885317 ("drm/i915/psr: Set > "SF Partial Frame Enable" also on full update") and also setting > partial frame enable when psr_force_hw_tracking_exit() is called. Reviewed-by: Jouni Högander

[Intel-gfx] [PATCH i-g-t v2 1/3] test/gem_lmem_swapping: account for object rounding

On DG2 the object size might be rounded when allocating lmem. Make sure we account for any rounding up. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Nirmoy Das Reviewed-by: Thomas Hellström Reviewed-by: Ashutosh Dixit --- tests/i915/gem_lmem_swapping.c | 10 +- 1 file changed

[Intel-gfx] [PATCH i-g-t v2 2/3] test/gem_lmem_swapping: fix physical engine usage

During execbuf DG2 currently just hits: "execbuf with unknown ring: 5" It looks like the fix is to convert the test over to using the non-legacy API where we instead fill the ctx with all the physical engines and then engine/ring becomes the index into this. v2: - Make sure we destroy

[Intel-gfx] [PATCH i-g-t v2 3/3] tests/gem_lmem_swapping: reduce the timeout

300s is way too much for some BAT test. Drop it down to 45s. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Nirmoy Das Reviewed-by: Thomas Hellström --- tests/i915/gem_lmem_swapping.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/i915/gem_lmem_swapping.c b/te

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS (rev2) URL : https://patchwork.freedesktop.org/series/101749/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22677 =

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS (rev2)

On 25/03/2022 09:22, Patchwork wrote: *Patch Details* *Series:* series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS (rev2) *URL:* https://patchwork.freedesktop.org/series/101749/ *State:*failure *Detail

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for lmem_size modparam

On 24/03/2022 20:15, Patchwork wrote: *Patch Details* *Series:* lmem_size modparam *URL:* https://patchwork.freedesktop.org/series/101744/ *State:*failure *Details:* https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22671/index.

[Intel-gfx] [PATCH] drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB

From: Tvrtko Ursulin UAPI with absolutely no documentation should not have been added - clarify blob format and content will be described externally. Fixes: 78e1fb3112c0 ("drm/i915/uapi: Add query for hwconfig blob") Signed-off-by: Tvrtko Ursulin Co-developed-by: Jordan Justen Cc: Jon Bloomfie

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Remove check for ComboPHY I/O voltage for DP source rate (rev5)

Hello Lakshmi, The below regressions are known issue and are not related patches: * igt@gem_exec_whisper@basic-fds-forked-all: * shard-kbl: NOTRUN -> INCOMPLETE https://g

Re: [Intel-gfx] [PATCH] drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB

On Fri, Mar 25, 2022 at 09:49:16AM +, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > UAPI with absolutely no documentation should not have been added - > clarify blob format and content will be described externally. > > Fixes: 78e1fb3112c0 ("drm/i915/uapi: Add query for hwconfig blob") > S

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 3/4] tests/gem_lmem_swapping: limit lmem to 4G

On Fri, Mar 25, 2022 at 08:40:45AM +, Matthew Auld wrote: > On 24/03/2022 17:47, Dixit, Ashutosh wrote: > > On Thu, 24 Mar 2022 07:26:20 -0700, Matthew Auld wrote: > > > > > > @@ -554,6 +560,7 @@ igt_main_args("", long_options, help_str, > > > opt_handler, NULL) > > > igt_fixture { > > >

Re: [Intel-gfx] [PATCH 1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS

On 3/25/2022 8:16 AM, Thomas Hellström wrote: On 3/24/22 18:21, Matthew Auld wrote: We only need this when allocating device local-memory, where this influences the drm_buddy. Currently there is some funny behaviour where an "in limbo" system memory object is lacking the relevant placement fl

Re: [Intel-gfx] [PATCH 1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS

On 3/25/2022 11:03 AM, Das, Nirmoy wrote: Reviewed-by: Nirmoy Das Sorry, I meant this r-b for the  2nd patch and for this one Acked-by: Nirmoy Das

Re: [Intel-gfx] [PATCH 1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS

On 3/25/2022 11:05 AM, Das, Nirmoy wrote: On 3/25/2022 11:03 AM, Das, Nirmoy wrote: Reviewed-by: Nirmoy Das Sorry, I meant this r-b for the  2nd patch and for this one Acked-by: Nirmoy Das hmm old habit, please use : Acked-by: Nirmoy Das

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB

== Series Details == Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB URL : https://patchwork.freedesktop.org/series/101781/ State : warning == Summary == $ dim checkpatch origin/drm-tip 398e62e3146a drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB -:11: WARNING:BAD_SIGN_OFF: C

Re: [Intel-gfx] [PATCH 1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS

On 3/25/2022 11:06 AM, Das, Nirmoy wrote: On 3/25/2022 11:05 AM, Das, Nirmoy wrote: On 3/25/2022 11:03 AM, Das, Nirmoy wrote: Reviewed-by: Nirmoy Das Sorry, I meant this r-b for the  2nd patch and for this one Acked-by: Nirmoy Das hmm old habit, please use : Acked-by: Nirmoy Das Same f

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB

== Series Details == Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB URL : https://patchwork.freedesktop.org/series/101781/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH i-g-t 3/4] tests/gem_lmem_swapping: limit lmem to 4G

Reviewed-by: Nirmoy Das On 3/24/2022 3:26 PM, Matthew Auld wrote: From: CQ Tang On some systems lmem can be as large as 16G, which seems to trigger various CI timeouts, and in the best case just takes a long time. For the purposes of the test we should be able to limit to 4G, without any big

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB

== Series Details == Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB URL : https://patchwork.freedesktop.org/series/101781/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not f

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 3/4] tests/gem_lmem_swapping: limit lmem to 4G

On Thu, Mar 24, 2022 at 02:26:20PM +, Matthew Auld wrote: > From: CQ Tang > > On some systems lmem can be as large as 16G, which seems to trigger > various CI timeouts, and in the best case just takes a long time. For > the purposes of the test we should be able to limit to 4G, without any >

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 3/4] tests/gem_lmem_swapping: limit lmem to 4G

On 25/03/2022 10:18, Petri Latvala wrote: On Thu, Mar 24, 2022 at 02:26:20PM +, Matthew Auld wrote: From: CQ Tang On some systems lmem can be as large as 16G, which seems to trigger various CI timeouts, and in the best case just takes a long time. For the purposes of the test we should be

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Extend DP HDR support to hsw+ (rev4)

From: Patchwork Sent: Thursday, March 24, 2022 10:43 PM To: Shankar, Uma Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.IGT: failure for drm/i915/display: Extend DP HDR support to hsw+ (rev4) Patch Details Series: drm/i915/display: Extend DP HDR support to hsw+ (rev4) URL: https://pa

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB

== Series Details == Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB URL : https://patchwork.freedesktop.org/series/101781/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22678 Summary ---

Re: [Intel-gfx] [PATCH] drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB

On 25/03/2022 09:53, Daniel Vetter wrote: On Fri, Mar 25, 2022 at 09:49:16AM +, Tvrtko Ursulin wrote: From: Tvrtko Ursulin UAPI with absolutely no documentation should not have been added - clarify blob format and content will be described externally. Fixes: 78e1fb3112c0 ("drm/i915/uapi

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: fix one mem leak in mmap_offset_attach() (rev5)

== Series Details == Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev5) URL : https://patchwork.freedesktop.org/series/100532/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' n

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: fix one mem leak in mmap_offset_attach() (rev5)

== Series Details == Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev5) URL : https://patchwork.freedesktop.org/series/100532/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22679 Summary --

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)

== Series Details == Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2) URL : https://patchwork.freedesktop.org/series/101781/ State : warning == Summary == $ dim checkpatch origin/drm-tip e3f9a29e30e4 drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB -:11: WARNING:BAD_SIGN

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)

== Series Details == Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2) URL : https://patchwork.freedesktop.org/series/101781/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)

== Series Details == Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2) URL : https://patchwork.freedesktop.org/series/101781/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable'

Re: [Intel-gfx] [RFC] drm/i915: Split out intel_vtd_active and run_as_guest to own header

On Fri, 25 Mar 2022, Tvrtko Ursulin wrote: > On 24/03/2022 18:57, Jani Nikula wrote: >> On Thu, 24 Mar 2022, Tvrtko Ursulin wrote: >>> On 24/03/2022 11:57, Jani Nikula wrote: On Thu, 24 Mar 2022, Tvrtko Ursulin wrote: > On 24/03/2022 09:31, Jani Nikula wrote: >> On Tue, 22 Mar 2022,

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2)

== Series Details == Series: drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB (rev2) URL : https://patchwork.freedesktop.org/series/101781/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22680 Summary

[Intel-gfx] [PATCH 0/9] drm/edid: constify EDID parsing

Remove accidental (?) EDID modification while parsing, and constify EDID in most places during EDID parsing. In the future I'll want more clarity on who modifies the EDID and where, and I'll want the compiler to help. The EDID is still mutable in places that do validity checking and try to fix it

[Intel-gfx] [PATCH 1/9] drm/edid: don't modify EDID while parsing

We'll want to keep the EDID immutable while parsing. Stop modifying the EDID because of the quirks. In theory, this does have userspace implications, but the userspace is supposed to use the modes exposed via KMS API, not by parsing the EDID directly. Cc: Ville Syrjälä Signed-off-by: Jani Nikula

[Intel-gfx] [PATCH 2/9] drm/edid: pass a timing pointer to is_display_descriptor()

Use struct member access instead of direct offsets to avoid lots of casts all over the place. Use BUILD_BUG_ON() for sanity check. Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_edid.c | 26 +++--- 1 file changed, 15 insertions(+), 11 deletions(-) dif

[Intel-gfx] [PATCH 3/9] drm/edid: use struct detailed_timing member access in is_rb()

Use struct detailed_timing member access instead of direct offsets to avoid casting. Use BUILD_BUG_ON() for sanity check. Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- Note: Why can we use range.formula.cvt.flags directly in is_rb() while gtf2 functions check for range.flags == 0x02 first

[Intel-gfx] [PATCH 5/9] drm/edid: constify struct detailed_timing in lower level parsing

Start constifying the struct detailed_timing pointers being passed around from bottom up. Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_edid.c | 40 +++--- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/drm_

[Intel-gfx] [PATCH 4/9] drm/edid: use struct detailed_timing member access in gtf2 functions

Use struct detailed_timing member access instead of direct offsets to avoid casting. Use BUILD_BUG_ON() for sanity check. Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_edid.c | 57 +- 1 file changed, 37 insertions(+), 20 deletions(-)

[Intel-gfx] [PATCH 6/9] drm/edid: constify struct detailed_timing in parsing callbacks

Moving one level higher, constify struct detailed_timing pointers in callbacks. Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_edid.c | 40 -- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/d

[Intel-gfx] [PATCH 7/9] drm/edid: constify struct edid passed to detailed blocks

Constify the first level of struct edid in detailed timing parsing. Also switch to struct edid instead of u8. Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_edid.c | 48 ++ 1 file changed, 23 insertions(+), 25 deletions(-) diff --git a/

[Intel-gfx] [PATCH 8/9] drm/edid: constify struct edid passed around in callbacks and closure

Finalize detailed timing parsing constness by making struct edid also const in callbacks and closure. Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_edid.c | 48 +++--- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/

[Intel-gfx] [PATCH 9/9] drm/edid: add more general struct edid constness in the interfaces

With this, the remaining non-const parts are the ones that actually modify the EDID, for example to fix corrupt EDID. Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/drm_edid.c | 21 +++-- include/drm/drm_edid.h | 10 +- 2 files changed, 16 insertion

[Intel-gfx] [PATCH 01/13] drm/i915: Make .get_dplls() return int

From: Ville Syrjälä Get rid of the confusing back and forth between bools and ints in the .get_dplls() stuff. Just make everything return an int. Initial conversion done with cocci, with some manual fixups on top: @find@ identifier func !~ "get_hw_state|_is_|needed"; typedef bool; parameter list

[Intel-gfx] [PATCH 03/13] drm/i915: Remove pointless dpll_funcs checks

From: Ville Syrjälä All platforms have dpll_funcs. Remove the pointless NULL checks. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH 05/13] drm/i915: Move stuff into intel_dpll_crtc_compute_clock()

From: Ville Syrjälä Move some checks into intel_dpll_crtc_compute_clock() from the caller. Avoids the caller from having to worry about all this crap. We'll also reorder the hw.enable vs. shared_dpll checks since it makes sense to sanity check that we've cleared out the old shared_dpll even if t

[Intel-gfx] [PATCH 00/13] drm/i915: Start reordering modeset clock calculations

From: Ville Syrjälä Start reordering when we do the clock/dpll calculations during the atomic check. The eventual goals are: - back feed the actually calculated clock into the crtc state so that stuff that depends on it (eg. watermarks) will be calculated based on the actual hardware state we

[Intel-gfx] [PATCH 07/13] drm/i915: Clear the dpll_hw_state when disabling a pipe

From: Ville Syrjälä Clear the dpll_hw_state when we're about disable the pipe. Previously it looks like we just left the old junk in there. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dpll.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drive

[Intel-gfx] [PATCH 06/13] drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()

From: Ville Syrjälä All .crtc_compute_clock() implementations do the same memset() to clear the dpll_hw_state (since we preserve it across intel_crtc_prepare_cleared_state()). Move the memset() to the common wrapper. Also clear it when we're about disable the pipe. Previously it looks like we ju

[Intel-gfx] [PATCH 08/13] drm/i915: Split out dg2_crtc_compute_clock()

From: Ville Syrjälä DG2 doesn't currently used the shared_dpll stuff so let's just split it out from hsw_crtc_compute_clock() entirely. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dpll.c | 22 ++ 1 file changed, 18 insertions(+), 4 deletions(-) diff

[Intel-gfx] [PATCH 12/13] drm/i915: Clean up DPLL related debugs

From: Ville Syrjälä The debugs in lower level DPLL code don't really provide any useful extra information AFAICS. Better just streamline the code and just put the necessary debugs (to identify at which step the modeset failed) into the higher level code. In addition we'll get the full state dump

[Intel-gfx] [PATCH 02/13] drm/i915: Pass dev_priv to intel_shared_dpll_init()

From: Ville Syrjälä Stop passing around the drm_device and just pass the dev_priv instead. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 9 - drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 +--

[Intel-gfx] [PATCH 13/13] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()

From: Ville Syrjälä Only reassign the pipe's DPLL if it's going through a full .compute_config() cycle. If OTOH it's just getting modeset eg. in order to change cdclk there doesn't seem much point in picking a new DPLL for it. This should also prevent .get_dplls() from seeing a funky port_clock

[Intel-gfx] [PATCH 09/13] drm/i915: Add crtc .crtc_get_shared_dpll()

From: Ville Syrjälä Start splitting the .compute_crtc_clock() into two parts; one part does the computation, the second part does the shared dpll assignment. I want to move the actual computation part much earlier into the compute_config() phase. Signed-off-by: Ville Syrjälä --- drivers/gpu/dr

[Intel-gfx] [PATCH 10/13] drm/i915: Split shared dpll .get_dplls() into compute and get phases

From: Ville Syrjälä Split the DPLL state computation into a separate function from the current .get_dplls() which currently serves a dual duty by also reserving the shared DPLLs. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dpll.c | 14 +- drivers/gpu/drm/i915/displ

[Intel-gfx] [PATCH 04/13] drm/i915: Adjust .crtc_compute_clock() calling convention

From: Ville Syrjälä Pass the full atomic state+crtc rather than the redundant crtc+crtc_state pair. We already need the full atomic state in the hsw+ codepath anyway. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll.

Re: [Intel-gfx] [PATCH 1/9] drm/edid: don't modify EDID while parsing

On Fri, Mar 25, 2022 at 02:25:23PM +0200, Jani Nikula wrote: > We'll want to keep the EDID immutable while parsing. Stop modifying the > EDID because of the quirks. > > In theory, this does have userspace implications, but the userspace is > supposed to use the modes exposed via KMS API, not by pa

Re: [Intel-gfx] [PATCH 2/9] drm/edid: pass a timing pointer to is_display_descriptor()

On Fri, Mar 25, 2022 at 02:25:24PM +0200, Jani Nikula wrote: > Use struct member access instead of direct offsets to avoid lots of > casts all over the place. > > Use BUILD_BUG_ON() for sanity check. > > Cc: Ville Syrjälä > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/drm_edid.c | 26 +++

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: fix one mem leak in mmap_offset_attach() (rev6)

== Series Details == Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev6) URL : https://patchwork.freedesktop.org/series/100532/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' n

[Intel-gfx] [PATCH 11/13] drm/i915: Do .crtc_compute_clock() earlier

From: Ville Syrjälä Currently we calculate a lot of things (pixel rate, watermarks, cdclk) trusting that the DPLL can generate the exact frequency we ask it. In practice that is not true and there can be certain amount of rounding involved. To allows us to eventually get accurate numbers for all

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: constify EDID parsing

== Series Details == Series: drm/edid: constify EDID parsing URL : https://patchwork.freedesktop.org/series/101787/ State : warning == Summary == $ dim checkpatch origin/drm-tip c7362ef166c6 drm/edid: don't modify EDID while parsing 4d7e2d1d7ed8 drm/edid: pass a timing pointer to is_display_de

Re: [Intel-gfx] [PATCH 3/9] drm/edid: use struct detailed_timing member access in is_rb()

On Fri, Mar 25, 2022 at 02:25:25PM +0200, Jani Nikula wrote: > Use struct detailed_timing member access instead of direct offsets to > avoid casting. > > Use BUILD_BUG_ON() for sanity check. > > Cc: Ville Syrjälä > Signed-off-by: Jani Nikula > > --- > > Note: Why can we use range.formula.cvt.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: fix one mem leak in mmap_offset_attach() (rev6)

== Series Details == Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev6) URL : https://patchwork.freedesktop.org/series/100532/ State : success == Summary == CI Bug Log - changes from CI_DRM_11404 -> Patchwork_22681 Summary --

Re: [Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in dsb_prepare()

> -Original Message- > From: Das, Nirmoy > Sent: Thursday, March 24, 2022 2:39 PM > To: Manna, Animesh ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in > dsb_prepare() > > > On 3/24/2022 8:43 AM, Animesh Manna wrote: > > The

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/edid: constify EDID parsing

== Series Details == Series: drm/edid: constify EDID parsing URL : https://patchwork.freedesktop.org/series/101787/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/gpu/dr

Re: [Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in dsb_prepare()

On 3/25/2022 2:22 PM, Manna, Animesh wrote: -Original Message- From: Das, Nirmoy Sent: Thursday, March 24, 2022 2:39 PM To: Manna, Animesh ; intel- g...@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in dsb_prepare() On 3/24/2022 8:43 AM,

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: constify EDID parsing

== Series Details == Series: drm/edid: constify EDID parsing URL : https://patchwork.freedesktop.org/series/101787/ State : success == Summary == CI Bug Log - changes from CI_DRM_11404 -> Patchwork_22682 Summary --- **SUCCESS** No

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start reordering modeset clock calculations

== Series Details == Series: drm/i915: Start reordering modeset clock calculations URL : https://patchwork.freedesktop.org/series/101789/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3b931b51817a drm/i915: Make .get_dplls() return int 1b2d4a4a599e drm/i915: Pass dev_priv to in

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Start reordering modeset clock calculations

== Series Details == Series: drm/i915: Start reordering modeset clock calculations URL : https://patchwork.freedesktop.org/series/101789/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/psr: Use continuos full frame to handle frontbuffer invalidations

Hello Jose, See my comments below. On Thu, 2022-03-24 at 11:13 -0700, José Roberto de Souza wrote: > Instead of exit PSR when a frontbuffer invalidation happens, we can > enable the PSR2 selective fetch continuous full frame, that will keep > the panel updated like PSR was disabled but without ke

[Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_22014226127

New DG2 workaround added to specification. BSpec: 54077 BSpec: 66622 BSpec: 54833 Cc: Matt Roper Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + 2 files changed, 6 insertions(+) diff --git a/driv

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Start reordering modeset clock calculations

== Series Details == Series: drm/i915: Start reordering modeset clock calculations URL : https://patchwork.freedesktop.org/series/101789/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not

[Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in dsb_prepare()

The request to aqquire gem resources is failing for DSB in rare scenario where it is busy and the register programming will be done through mmio fallback path. DSB has extra advantage of faster register programming which may go away through mmio path. Adding wait for gem resource also may not be r

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_22014226127

On Fri, Mar 25, 2022 at 07:22:49AM -0700, José Roberto de Souza wrote: > New DG2 workaround added to specification. > > BSpec: 54077 > BSpec: 66622 > BSpec: 54833 > Cc: Matt Roper > Signed-off-by: José Roberto de Souza Reviewed-by: Matt Roper > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Start reordering modeset clock calculations

== Series Details == Series: drm/i915: Start reordering modeset clock calculations URL : https://patchwork.freedesktop.org/series/101789/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22683 Summary --

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dg2: Add Wa_22014226127

== Series Details == Series: drm/i915/dg2: Add Wa_22014226127 URL : https://patchwork.freedesktop.org/series/101792/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/gpu/d

Re: [Intel-gfx] [PATCH 2/2] drm/i915/display/psr: Use continuos full frame to handle frontbuffer invalidations

On Fri, 2022-03-25 at 14:21 +, Hogander, Jouni wrote: > Hello Jose, > > See my comments below. > > On Thu, 2022-03-24 at 11:13 -0700, José Roberto de Souza wrote: > > Instead of exit PSR when a frontbuffer invalidation happens, we can > > enable the PSR2 selective fetch continuous full frame,

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: fix one mem leak in mmap_offset_attach() (rev6)

== Series Details == Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev6) URL : https://patchwork.freedesktop.org/series/100532/ State : success == Summary == CI Bug Log - changes from CI_DRM_11404_full -> Patchwork_22681_full

Re: [Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in dsb_prepare()

On 3/25/2022 3:28 PM, Animesh Manna wrote: The request to aqquire gem resources is failing for DSB in rare scenario where it is busy and the register programming will be done through mmio fallback path. DSB has extra advantage of faster register programming which may go away through mmio path.

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_22014226127

== Series Details == Series: drm/i915/dg2: Add Wa_22014226127 URL : https://patchwork.freedesktop.org/series/101792/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22684 Summary --- **FAILURE** S

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dsb: modified to drm_info in dsb_prepare() (rev2)

== Series Details == Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev2) URL : https://patchwork.freedesktop.org/series/101723/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable'

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS (rev2) URL : https://patchwork.freedesktop.org/series/101749/ State : success == Summary == CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22677 =

[Intel-gfx] [PATCH] docs: gpu: i915.rst: Update DRRS functions names

intel_drrs_enable and intel_drrs_disable where renamed to intel_drrs_activate and intel_drrs_deactivate in commit 54903c7a6b40 ("drm/i915: s/enable/active/ for DRRS"). Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- Documentation/gpu/i915.rst | 4 ++-- 1 file changed, 2 insertions(+)

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/ttm: limit where we apply TTM_PL_FLAG_CONTIGUOUS (rev2)

Regression on RKL is related to https://gitlab.freedesktop.org/drm/intel/-/issues/4418 Thanks, Lakshmi. -Original Message- From: Auld, Matthew Sent: Friday, March 25, 2022 2:49 AM To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana Subject: Re: ✗ Fi.CI.BAT: failure for series

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsb: modified to drm_info in dsb_prepare() (rev2)

== Series Details == Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev2) URL : https://patchwork.freedesktop.org/series/101723/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22685 Summary -

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dg2: Add Wa_22014226127 (rev2)

== Series Details == Series: drm/i915/dg2: Add Wa_22014226127 (rev2) URL : https://patchwork.freedesktop.org/series/101792/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./driver

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/edid: constify EDID parsing

== Series Details == Series: drm/edid: constify EDID parsing URL : https://patchwork.freedesktop.org/series/101787/ State : success == Summary == CI Bug Log - changes from CI_DRM_11404_full -> Patchwork_22682_full Summary --- **SUCCE

Re: [Intel-gfx] Commit messages

Dear Christian, dear Daniel, dear Alex, Am 23.03.22 um 16:32 schrieb Christian König: Am 23.03.22 um 16:24 schrieb Daniel Stone: On Wed, 23 Mar 2022 at 15:14, Alex Deucher wrote: On Wed, Mar 23, 2022 at 11:04 AM Daniel Stone wrote: That's not what anyone's saying here ... No-one's demandi

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Add Wa_22014226127 (rev2)

== Series Details == Series: drm/i915/dg2: Add Wa_22014226127 (rev2) URL : https://patchwork.freedesktop.org/series/101792/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22686 Summary --- **FAILURE

[Intel-gfx] ✓ Fi.CI.IGT: success for Remove check for ComboPHY I/O voltage for DP source rate (rev5)

== Series Details == Series: Remove check for ComboPHY I/O voltage for DP source rate (rev5) URL : https://patchwork.freedesktop.org/series/96293/ State : success == Summary == CI Bug Log - changes from CI_DRM_11398_full -> Patchwork_22655_full =

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Remove check for ComboPHY I/O voltage for DP source rate (rev5)

Filed a new issue and re-reported. https://gitlab.freedesktop.org/drm/intel/-/issues/5436 igt@gem_exec_whisper@basic-fds-(forked|priority)-all - incomplete - general protection fault, probably for non-canonical address 0x6b6b6b6b6b6b7c33 From: Nautiyal, Ankit K Sent: Friday, March 25, 2022 2:50

[Intel-gfx] [PATCH] drm/i915/dsb: modified to drm_info in dsb_prepare()

The request to aqquire gem resources is failing for DSB in rare scenario where it is busy and the register programming will be done through mmio fallback path. DSB has extra advantage of faster register programming which may go away through mmio path. Adding wait for gem resource also may not be r

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Extend DP HDR support to hsw+ (rev4)

== Series Details == Series: drm/i915/display: Extend DP HDR support to hsw+ (rev4) URL : https://patchwork.freedesktop.org/series/101708/ State : success == Summary == CI Bug Log - changes from CI_DRM_11401_full -> Patchwork_22670_full Sum

[Intel-gfx] ✗ Fi.CI.BAT: failure for docs: gpu: i915.rst: Update DRRS functions names

== Series Details == Series: docs: gpu: i915.rst: Update DRRS functions names URL : https://patchwork.freedesktop.org/series/101795/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11405 -> Patchwork_22687 Summary ---

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Extend DP HDR support to hsw+ (rev4)

Re-reported. From: Shankar, Uma Sent: Friday, March 25, 2022 3:35 AM To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana Subject: RE: ✗ Fi.CI.IGT: failure for drm/i915/display: Extend DP HDR support to hsw+ (rev4) From: Patchwork mailto:patchw...@emeril.freedesktop.org>> Sent: Thu

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