On 20.10.2022 17:20, Anusha Srivatsa wrote:
> No functional changes. The series is more of a prep series
> for the mid_cdclk_config series:
> https://patchwork.freedesktop.org/series/109694/
>
> Main change:
> - Change usage of "crawler" and "squasher". Use crawling and
> squashing instead.
> -
On 20.10.2022 17:20, Anusha Srivatsa wrote:
> No functional change. Introduce dg2_cdclk_squash_programming and
> move squash_ctl register programming bits to this.
>
> Cc: Balasubramani Vivekanandan
> Cc: Ville Syrjälä
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel
On 20.10.2022 17:20, Anusha Srivatsa wrote:
> Driver had discrepancy in how cdclk squash and crawl support
> were checked. Like crawl, add squash as a 1 bit feature flag
> to the display section of DG2.
>
> Cc: Balasubramani Vivekanandan
> Cc: Ville Syrjälä
> Signed-off-by: Anusha Srivatsa
> --
> -Original Message-
> From: Intel-gfx On Behalf Of Suraj
> Kandpal
> Sent: Thursday, October 20, 2022 4:17 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [Intel-gfx] [PATCH v3 0/1] Remove Connector iterator macro
>
> Remove connector iterator macro (for_each_c
On 20/10/2022 16:10, Matthew Auld wrote:
We rely on page_sizes.sg in setup_scratch_page() reporting the correct
value if the underlying sgl is not contiguous, however in
get_pages_internal() we are only looking at the layout of the created
pages when calculating the sg_page_sizes, and not the f
== Series Details ==
Series: drm/i915/psr: Remove inappropriate DSC slice alignment warning
URL : https://patchwork.freedesktop.org/series/109983/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12270 -> Patchwork_109983v1
Su
On 20/10/2022 12:03, Christoph Hellwig wrote:
From: Robert Beckett
swiotlb_max_segment used to return either the maximum size that swiotlb
could bounce, or for Xen PV PAGE_SIZE even if swiotlb could bounce buffer
larger mappings. This made i915 on Xen PV work as it bypasses the
coherency asp
On Mon, 2022-10-17 at 10:03 -0700, Alan Previn Teres Alexis wrote:
> >
> > On Thu, 2022-10-13 at 13:48 -0700, Ceraolo Spurio, Daniele wrote:
> > > >
> > > > On 10/5/2022 9:38 PM, Alan Previn wrote:
> > > > > > In preparation for future MTL-PXP feature support, PXP control
> > > > > > context sh
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, October 21, 2022 8:49 AM
> To: Intel-gfx@lists.freedesktop.org
> Cc: Hogander, Jouni ; Souza, Jose
> ; Kahola, Mika ; Gupta,
> Anshuman
> Subject: [PATCH] drm/i915/psr: Remove inappropriate DSC slice alignment
> warning
>
> Sel
On Thu, 20 Oct 2022, Imre Deak wrote:
> This is v2 of [1] addressing the review comments from Jani.
Did not do detailed review,
Acked-by: Jani Nikula
>
> [1]
> https://lore.kernel.org/intel-gfx/y1barftah%2fl+x...@ideak-desk.fi.intel.com/T/#t
>
> Cc: Jani Nikula
> Cc: Ville Syrjälä
>
> Imre
On Thu, 20 Oct 2022, Anusha Srivatsa wrote:
> No functional change. Moving segments out to simplify
> bxt_set_cdlck()
>
> Cc: Balasubramani Vivekanandan
> Cc: Ville Syrjälä
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++
> 1 file
From: Kees Cook
Implement a robust overflows_type() macro to test if a variable or
constant value would overflow another variable or type. This can be
used as a constant expression for static_assert() (which requires a
constant expression[1][2]) when used on constant values. This must be
construc
On Thu, 20 Oct 2022, Anusha Srivatsa wrote:
> No functional change. Introduce dg2_cdclk_squash_programming and
> move squash_ctl register programming bits to this.
>
> Cc: Balasubramani Vivekanandan
> Cc: Ville Syrjälä
> Signed-off-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel
On 27/10/2021 01:48, Umesh Nerlige Ramappa wrote:
[snip]
+static void guc_timestamp_ping(struct work_struct *wrk)
+{
+ struct intel_guc *guc = container_of(wrk, typeof(*guc),
+timestamp.work.work);
+ struct intel_uc *uc = container_of(gu
On Fri, 21 Oct 2022, Balasubramani Vivekanandan
wrote:
> On 20.10.2022 17:20, Anusha Srivatsa wrote:
>> No functional changes. The series is more of a prep series
>> for the mid_cdclk_config series:
>> https://patchwork.freedesktop.org/series/109694/
>>
>> Main change:
>> - Change usage of "cra
On Fri, 21 Oct 2022, Balasubramani Vivekanandan
wrote:
> On 20.10.2022 17:20, Anusha Srivatsa wrote:
>> Driver had discrepancy in how cdclk squash and crawl support
>> were checked. Like crawl, add squash as a 1 bit feature flag
>> to the display section of DG2.
>>
>> Cc: Balasubramani Vivekanan
== Series Details ==
Series: drm/i915: stop abusing swiotlb_max_segment (rev2)
URL : https://patchwork.freedesktop.org/series/109946/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Hi Matthew,
On 20.10.2022 17:10, Matthew Auld wrote:
We rely on page_sizes.sg in setup_scratch_page() reporting the correct
value if the underlying sgl is not contiguous, however in
get_pages_internal() we are only looking at the layout of the created
pages when calculating the sg_page_sizes, an
On Thu, 20 Oct 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On BDW+ we have just the one set of DP M/N registers. The
> values we write into said registers depends on whether we
> want DRRS to be in high or low gear. This causes issues
> for the state checker which currently has to assume
== Series Details ==
Series: drm/i915: stop abusing swiotlb_max_segment (rev2)
URL : https://patchwork.freedesktop.org/series/109946/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12271 -> Patchwork_109946v2
Summary
---
On Thu, 20 Oct 2022, Ville Syrjälä wrote:
> On Sat, Sep 24, 2022 at 03:02:34PM +0200, Greg KH wrote:
>> On Sun, Sep 11, 2022 at 11:28:43PM -0600, Jim Cromie wrote:
>> > hi Greg, Dan, Jason, DRM-folk,
>> >
>> > heres follow-up to V6:
>> > rebased on driver-core/driver-core-next for -v6 applied b
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjälä
> Sent: torstai 20. lokakuuta 2022 19.21
> To: Jani Nikula
> Cc: Sarvela, Tomi P ;
> intel-gfx@lists.freedesktop.org;
> dri-de...@lists.freedesktop.org; Vivi, Rodrigo
> Subject: Re: [Intel-gfx] Random submitter ch
== Series Details ==
Series: drm/i915/dg1: Remove require_force_probe protection (rev3)
URL : https://patchwork.freedesktop.org/series/100601/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12270_full -> Patchwork_100601v3_full
==
Runtime pm is not really per GT, therefore it make sense to
move lmem_userfault_list, lmem_userfault_lock and
userfault_wakeref from intel_gt to intel_runtime_pm structure,
which is embedded to i915.
No functional change.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_mman.
We had already grabbed the rpm wakeref at obj destruction path,
but it also required to grab the wakeref when object moves.
When i915_gem_object_release_mmap_offset() gets called by
i915_ttm_move_notify(), it will release the mmap offset without
grabbing the wakeref. We want to avoid that therefore
On Wed, 19 Oct 2022, "Taylor, Clinton A" wrote:
> Replace internal with discrete on dgfx platforms
Please use the imperative mood in the commit subject, i.e. "update" not
"updated".
>
> Signed-off-by: Taylor, Clinton A
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
> 1 file chan
== Series Details ==
Series: drm/i915/psr: Remove inappropriate DSC slice alignment warning
URL : https://patchwork.freedesktop.org/series/109983/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12270_full -> Patchwork_109983v1_full
==
On 19/10/2022 22:59, Andrzej Hajda wrote:
Since almost all calls to i915_vma_move_to_active are prepended with
i915_request_await_object, let's call the latter from
_i915_vma_move_to_active by default and add flag allowing bypassing it.
Adjust all callers accordingly.
The patch should not intro
== Series Details ==
Series: overflow: Introduce overflows_type() and castable_to_type() (rev3)
URL : https://patchwork.freedesktop.org/series/109076/
State : warning
== Summary ==
Error: dim checkpatch failed
89eeed59f1ab overflow: Introduce overflows_type() and castable_to_type()
-:88: CHECK
== Series Details ==
Series: overflow: Introduce overflows_type() and castable_to_type() (rev3)
URL : https://patchwork.freedesktop.org/series/109076/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: overflow: Introduce overflows_type() and castable_to_type() (rev3)
URL : https://patchwork.freedesktop.org/series/109076/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12273 -> Patchwork_109076v3
== Series Details ==
Series: drm/i915: Activate DRRS after state readout (rev2)
URL : https://patchwork.freedesktop.org/series/109950/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12273 -> Patchwork_109950v2
Summary
--
== Series Details ==
Series: drm/i915: refactor i915_vma_move_to_active (rev2)
URL : https://patchwork.freedesktop.org/series/109910/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12273 -> Patchwork_109910v2
Summary
---
== Series Details ==
Series: drm/i915: stop abusing swiotlb_max_segment (rev2)
URL : https://patchwork.freedesktop.org/series/109946/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12271_full -> Patchwork_109946v2_full
Summa
== Series Details ==
Series: drm/i915: Clean up crtc state flag checks (rev2)
URL : https://patchwork.freedesktop.org/series/109949/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12273 -> Patchwork_109949v2
Summary
---
Hi Andrzej,
[...]
> +static inline int __must_check
> +igt_vma_move_to_active_unlocked(struct i915_vma *vma, struct i915_request
> *rq,
> + unsigned int flags)
> +{
> + int err;
> +
> + i915_vma_lock(vma);
> + err = _i915_vma_move_to_active(vma, rq, &rq->f
Hi Andrzej,
(at first I r-b'ed this patch, but then I wanted to think on some
more "simplification" (if it really simplifies things). Please
read the review in patch 2 first )
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
Hi Gwan-gyeong,
On Fri, Oct 21, 2022 at 11:33:33AM +0300, Gwan-gyeong Mun wrote:
> From: Kees Cook
>
> Implement a robust overflows_type() macro to test if a variable or
> constant value would overflow another variable or type. This can be
> used as a constant expression for static_assert() (whi
On Wed, 19 Oct 2022 16:37:19 -0700, Ashutosh Dixit wrote:
>
> From: Badal Nilawar
>
> Update CAGF functions for MTL to get actual resolved frequency of 3D and
> SAMedia.
>
> v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
> Move MTL branches in cagf functions to top (MattR)
>
On Wed, Oct 19, 2022 at 04:37:17PM -0700, Ashutosh Dixit wrote:
> Instead of masks/shifts settle on REG_FIELD_GET as the standard way to
> extract reg fields. This allows future patches touching this code to also
> consistently use REG_FIELD_GET and friends.
>
> Suggested-by: Rodrigo Vivi
> Signe
On Wed, Oct 19, 2022 at 04:37:18PM -0700, Ashutosh Dixit wrote:
> From: Don Hiatt
>
> On GEN12+ use GEN12_RPSTAT register to get actual resolved GT
> freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if
> GT is in RC6.
>
> v2:
> - Fixed review comments(Ashutosh)
> - Adde
On Fri, Oct 21, 2022 at 09:02:03AM -0700, Dixit, Ashutosh wrote:
> On Wed, 19 Oct 2022 16:37:19 -0700, Ashutosh Dixit wrote:
> >
> > From: Badal Nilawar
> >
> > Update CAGF functions for MTL to get actual resolved frequency of 3D and
> > SAMedia.
> >
> > v2: Update MTL_MIRROR_TARGET_WP1 position/f
On Wed, Oct 19, 2022 at 04:37:20PM -0700, Ashutosh Dixit wrote:
> Previously RC6 residency functions directly accepted RC6 residency register
> MMIO offsets (there are four RC6 residency registers). This worked but
> required an assumption on the residency register layout so was not future
> proof.
From: Ville Syrjälä
Some cleanups for checking whether the crtc was flagged for
modesets/fastsets/color update.
v2: Handle {connectors,active}_changed, and convert one
more fastset check in fbc code
Ville Syrjälä (4):
drm/i915: Introduce intel_crtc_needs_fastset()
drm/i915: Remove some
From: Ville Syrjälä
Replace the somewhat obscure crtc_state.update_pipe checks
with a more descriptive thing. Also nicely matches the
intel_crtc_needs_modeset() counterpart for full modesets.
v2: Handle one more case in the fbc code
Reviewed-by: Jani Nikula #v1
Signed-off-by: Ville Syrjälä
--
From: Ville Syrjälä
These 'mode_changed' booleans aren't very helpful. Just
replace them with direct intel_crtc_needs_modeset() calls
which is more descriptive.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 14 ++
1 file c
From: Ville Syrjälä
Be consistent in whether we flag a full modeset or a
fastset for the pipe. intel_modeset_all_pipes() would
seem to be the only codepath not getting this right.
The other case is when we flag the fastset initially,
currently we just clear the mode_changed flag and set
the upda
From: Ville Syrjälä
Add a common helper to answer the question "do we need
to update color management stuff?".
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/hsw_ips.c | 6 ++
drivers/gpu/drm/i915/display/intel_crtc.c | 3 +--
drivers
with the removal of pxptee_iface_owner and the separation of a global-pxp check
vs a per-gt pxp (is enabled) check, this
patch will get dropped as the latter change would appear in earlier in the
series
On Wed, 2022-10-05 at 21:38 -0700, Alan Previn wrote:
> pxptee_iface_owner
On Fri, Sep 23, 2022 at 09:35:14AM +0200, Nirmoy Das wrote:
> i915_gem_drain_freed_objects() might not be enough to
> free all the objects and RCU delayed work might get
> scheduled after the i915 device struct gets freed.
>
> Call i915_gem_drain_workqueue() to catch all RCU delayed work.
shard-s
On Wed, Oct 19, 2022 at 04:37:21PM -0700, Ashutosh Dixit wrote:
> From: Badal Nilawar
>
> Add support for C6 residency and C state type for MTL SAMedia. Also add
> mtl_drpc.
I believe this patch deserves a slip between the actual support and
the debugfs, but I'm late to the review, so feel free
On Mon, Aug 22, 2022 at 01:18:22PM +0200, Peter Zijlstra wrote:
> +#ifdef CONFIG_LOCKDEP
> + /*
> + * It's dangerous to freeze with locks held; there be dragons there.
> + */
> + if (!(state & __TASK_FREEZABLE_UNSAFE))
> + WARN_ON_ONCE(debug_locks && p->lockdep_depth);
== Series Details ==
Series: drm/i915: Clean up crtc state flag checks (rev3)
URL : https://patchwork.freedesktop.org/series/109949/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12275 -> Patchwork_109949v3
Summary
---
MTL has two tiles that is represented by the intel_gt structure in the i915
code. The PXP feature has a control-structure that contains the PXP context
and this hangs of the intel_gt structure. In MTL, the standalone media tile
(i.e. not the root tile) contains the VDBOX and KCR engine which is wh
Make intel_pxp_is_enabled a global check and implicitly find the
PXP-owning-GT.
PXP feature support is a device-config flag. In preparation for MTL
PXP control-context shall reside on of the two GT's. That said,
update intel_pxp_is_enabled to take in i915 as its input and internally
find the right
In preparation for future MTL-PXP feature support, PXP control
context should only valid on the correct gt tile. Depending on the
device-info this depends on which tile owns the VEBOX and KCR.
PXP is still a global feature though (despite its control-context
located in the owning GT structure). Add
Make intel_pxp_is_active a global check and implicitly find
the PXP-owning-GT.
As per prior two patches, callers of this function shall now
pass in i915 since PXP is a global GPU feature. Make
intel_pxp_is_active implicitly find the right gt so it's transparent
for global view callers (like displa
Ensure i915_pxp_tee_component_bind / unbind implicitly sorts out
getting the correct per-GT PXP control-context from the PXP-owning-GT
when establishing or ending connection. Thus, replace _i915_to_pxp_gt
with intel_pxp_get_owning_gt (also takes in i915).
Signed-off-by: Alan Previn
---
drivers/g
Make intel_pxp_key_check implicitly find the PXP-owning-GT.
Callers of this function shall now pass in i915 since PXP
is a global GPU feature. Make intel_pxp_key_check implicitly
find the right gt to verify pxp session key establishment count
so it's transparent to the callers.
Signed-off-by: Alan
Make intel_pxp_is_start implicitly find the PXP-owning-GT.
Callers of this function shall now pass in i915 since PXP
is a global GPU feature. Make intel_pxp_start implicitly
find the right gt to start PXP arb session so
it's transparent to the callers.
Signed-off-by: Alan Previn
---
drivers/gpu/
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev9)
URL : https://patchwork.freedesktop.org/series/108156/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev9)
URL : https://patchwork.freedesktop.org/series/108156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12275 -> Patchwork_108156v9
Summary
---
**SU
On 10/20/2022 4:36 PM, Dixit, Ashutosh wrote:
On Thu, 20 Oct 2022 13:16:00 -0700, Belgaumkar, Vinay wrote:
On 10/20/2022 11:33 AM, Dixit, Ashutosh wrote:
On Wed, 19 Oct 2022 17:29:44 -0700, Vinay Belgaumkar wrote:
Hi Vinay,
Waitboost (when SLPC is enabled) results in a H2G message. This can
Hi Andrzej,
On Wed, Oct 19, 2022 at 04:38:17PM +0200, Andrzej Hajda wrote:
> This patch replaces all occurences of the form
> intel_uncore_write(reg, intel_uncore_read(reg) OP val)
> with intel_uncore_rmw.
>
> Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
There are some lines that go o
Hi Andrzej,
On Wed, Oct 19, 2022 at 04:38:18PM +0200, Andrzej Hajda wrote:
> This patch replaces all occurences of the form
> intel_uncore_write(reg, intel_uncore_read(reg) OP val)
> with intel_uncore_rmw.
>
> Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
Thanks,
Andi
== Series Details ==
Series: drm/i915/pxp: Prepare intel_pxp entry points for MTL (rev3)
URL : https://patchwork.freedesktop.org/series/109429/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12275 -> Patchwork_109429v3
Summa
On Fri, 21 Oct 2022 11:24:42 -0700, Belgaumkar, Vinay wrote:
>
>
> On 10/20/2022 4:36 PM, Dixit, Ashutosh wrote:
> > On Thu, 20 Oct 2022 13:16:00 -0700, Belgaumkar, Vinay wrote:
> >> On 10/20/2022 11:33 AM, Dixit, Ashutosh wrote:
> >>> On Wed, 19 Oct 2022 17:29:44 -0700, Vinay Belgaumkar wrote:
> >
On 10/19/2022 00:29, Alan Previn wrote:
We missed this at initial upstream because at that time
none of the GuC enabled platforms had a compute engine.
Add this now.
Signed-off-by: Alan Previn
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 4
1 file
On 10/19/2022 00:29, Alan Previn wrote:
If GuC is being used and we initialized GuC-error-capture,
we need to be warning if we don't provide an error-capture
register list in the firmware ADS, for valid GT engines.
A warning makes sense as this would impact debugability
without realizing why a re
== Series Details ==
Series: overflow: Introduce overflows_type() and castable_to_type() (rev3)
URL : https://patchwork.freedesktop.org/series/109076/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12273_full -> Patchwork_109076v3_full
==
== Series Details ==
Series: Add DG2 OA support (rev9)
URL : https://patchwork.freedesktop.org/series/107584/
State : warning
== Summary ==
Error: dim checkpatch failed
54115be03fa0 drm/i915/perf: Fix OA filtering logic for GuC mode
404934d8ea75 drm/i915/perf: Add 32-bit OAG and OAR formats fo
== Series Details ==
Series: Add DG2 OA support (rev9)
URL : https://patchwork.freedesktop.org/series/107584/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
> -Original Message-
> From: Jani Nikula
> Sent: Friday, October 21, 2022 1:47 AM
> To: Vivekanandan, Balasubramani
> ; Srivatsa, Anusha
> ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce
> HAS_CDCLK_SQUASH macro
>
> On Fri, 21 Oct 202
> -Original Message-
> From: Jani Nikula
> Sent: Friday, October 21, 2022 1:41 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Cc: Vivekanandan, Balasubramani
>
> Subject: Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl
> register programming to its own f
> -Original Message-
> From: Jani Nikula
> Sent: Friday, October 21, 2022 1:32 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Cc: Vivekanandan, Balasubramani
>
> Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code
> out of bxt_set_cdclk()
>
> O
> -Original Message-
> From: Vivekanandan, Balasubramani
>
> Sent: Friday, October 21, 2022 12:08 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Cc: Ville Syrjälä
> Subject: Re: [PATCH 4/4] drm/i915/display: Move squash_ctl register
> programming to its own function
>
Replace internal with discrete of dgfx platforms.
v2: commit title reword (Jani)
Cc: Jani Nikula
Signed-off-by: Taylor, Clinton A
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/d
== Series Details ==
Series: drm/i915: Activate DRRS after state readout (rev2)
URL : https://patchwork.freedesktop.org/series/109950/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12273_full -> Patchwork_109950v2_full
Summ
No functional changes. The series is more of a prep series
for the mid_cdclk_config series:
https://patchwork.freedesktop.org/series/109694/
Main change:
- Change usage of "crawler" and "squasher". Use crawling and
squashing instead.
- Handle both squash and crawl similar in terms of checking
if
Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +
No functional change. Moving segments out to simplify
bxt_set_cdlck()
v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++
1
No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.
v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)
Cc: Jani Nikula
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/d
No functional changes. Changing terminolgy in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.
Cc: Balasubramani Vivekanandan
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 16 ---
== Series Details ==
Series: drm/i915/hdmi: SPD infoframe updated for discrete (rev2)
URL : https://patchwork.freedesktop.org/series/109908/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12277 -> Patchwork_109908v2
Summary
== Series Details ==
Series: Prep series - CDCLK code churn (rev2)
URL : https://patchwork.freedesktop.org/series/109974/
State : warning
== Summary ==
Error: dim checkpatch failed
750f09e493d8 drm/i915/display: Change terminology for cdclk actions
7e35fba6b197 drm/i915/display: Introduce HAS_
On 10/21/2022 11:40 AM, Dixit, Ashutosh wrote:
On Fri, 21 Oct 2022 11:24:42 -0700, Belgaumkar, Vinay wrote:
On 10/20/2022 4:36 PM, Dixit, Ashutosh wrote:
On Thu, 20 Oct 2022 13:16:00 -0700, Belgaumkar, Vinay wrote:
On 10/20/2022 11:33 AM, Dixit, Ashutosh wrote:
On Wed, 19 Oct 2022 17:29:44
== Series Details ==
Series: Prep series - CDCLK code churn (rev2)
URL : https://patchwork.freedesktop.org/series/109974/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12277 -> Patchwork_109974v2
Summary
---
**FAILUR
== Series Details ==
Series: drm/i915: refactor i915_vma_move_to_active (rev2)
URL : https://patchwork.freedesktop.org/series/109910/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12273_full -> Patchwork_109910v2_full
Summa
Previously, we only used PXP FW interface version-42 structures for
PXP arbitration session on ADL/TGL products and version-43 for HuC
authentication on DG2. With MTL, we'll need both these capabilities
side by side with these older platform feature support. That said,
let's create separate files t
== Series Details ==
Series: series starting with [1/1] drm/i915/pxp: Separate PXP FW interface
structures for both v42 and 43
URL : https://patchwork.freedesktop.org/series/110013/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/110013/revisions/1
The introduction of the media GT brings a few changes for GuC/HuC. The
main difference between the 2 GTs is that only the media one has the
HuC, while both have the GuC. Also, the fact that both GTs use the same
G-unit and GGTT means we now have parallel interrupt/communication
paths. Lastly, WOPCM
The media GT shares the G-unit with the root GT, so a second set of
communication registers is required for the media GuC.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John Harrison
Cc: Alan Previn
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 14 ++
dri
From: Aravind Iddamsetty
With MTL standalone media architecture the wopcm layout has changed with
separate partitioning in WOPCM for GCD/GT GuC and SA Media GuC. The size
of WOPCM is 4MB with lower 2MB for SA Media and upper 2MB for GCD/GT.
+=+===> ++ <== WOPCM TOP
The FW binaries are independently loaded on each GT. On MTL, the memory
is shared so we could potentially re-use a single allocation, but on
discrete multi-gt platforms we are going to need independent copies,
so it is easier to do the same on MTL as well, given that the amount
of duplicated memory
Our current FW loading process is the same for all FWs:
- Pin FW to GGTT at the start of the ggtt->uc_fw node
- Load the FW
- Unpin
This worked because we didn't have a case where 2 FWs would be loaded on
the same GGTT at the same time. On MTL, however, this can happen if both
GTs are reset at th
On MTL the primary GT doesn't have any media capabilities, so no video
engines and no HuC. We must therefore skip the HuC fetch and load on
that specific case. Given that other multi-GT platforms might have HuC
on the primary GT, we can't just check for that and it is easier to
instead check for th
From: Stuart Summers
MTL supports GuC deprivilege. Add the feature flag to this platform.
Signed-off-by: Stuart Summers
Cc: Radhakrishna Sripada
Cc: John Harrison
Cc: Alan Previn
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --gi
The render and media GuCs share the same interrupt enable register, so
we can no longer disable interrupts when we disable communication for
one of the GuCs as this would impact the other GuC. Instead, we keep the
interrupts always enabled in HW and use a variable in the GuC structure
to determine
On Fri, Oct 21, 2022 at 09:42:53AM +0100, Tvrtko Ursulin wrote:
On 27/10/2021 01:48, Umesh Nerlige Ramappa wrote:
[snip]
+static void guc_timestamp_ping(struct work_struct *wrk)
+{
+ struct intel_guc *guc = container_of(wrk, typeof(*guc),
+tim
== Series Details ==
Series: drm/i915: prepare for uC loading on MTL (rev3)
URL : https://patchwork.freedesktop.org/series/108925/
State : warning
== Summary ==
Error: dim checkpatch failed
23e8682ebaac drm/i915/huc: only load HuC on GTs that have VCS engines
-:44: WARNING:AVOID_BUG: Do not cr
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