[Intel-gfx] [PATCH 0/1] Add selftest for slpc tile interaction

This tests runs a workload on tiles simultaneously by requesting for RP0 frequency and fails if there is a throttling error Riana Tauro (1): drm/i915/guc/slpc: Add selftest for slpc tile-tile interaction drivers/gpu/drm/i915/gt/selftest_slpc.c | 63 + 1 file changed,

[Intel-gfx] [PATCH 1/1] drm/i915/guc/slpc: Add selftest for slpc tile-tile interaction

Run a workload on tiles simultaneously by requesting for RP0 frequency. Pcode can however limit the frequency being granted due to throttling reasons. This test fails if there is any throttling Signed-off-by: Riana Tauro --- drivers/gpu/drm/i915/gt/selftest_slpc.c | 63 +

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Add selftest for slpc tile interaction

== Series Details == Series: Add selftest for slpc tile interaction URL : https://patchwork.freedesktop.org/series/110248/ State : failure == Summary == Error: make failed CALLscripts/checksyscalls.sh DESCEND objtool CC [M] drivers/gpu/drm/i915/gt/intel_rps.o In file included from d

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk (rev2) URL : https://patchwork.freedesktop.org/series/110199/ State : success == Summary == CI Bug Log - changes from CI_DRM_12311_full -> Patchwork_110199v2_full ===

Re: [Intel-gfx] [PATCH 3/5] drm/i915/mtl: add GSC CS interrupt support

On 27/10/2022 23:15, Daniele Ceraolo Spurio wrote: The GSC CS re-uses the same interrupt bits that the GSC used in older platforms. This means that we can now have an engine interrupt coming out of OTHER_CLASS, so we need to handle that appropriately. Signed-off-by: Daniele Ceraolo Spurio Cc:

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

On Fri, 28 Oct 2022, Gwan-gyeong Mun wrote: > Resend, because some content was accidentally omitted from the previous > reply. > Please ignore the previous email. > > Hi all, > > I should have written the original commit message more accurately, but > it seems that it was written inaccurately. >

Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk

On Wed, Oct 26, 2022 at 04:22:56PM -0700, Anusha Srivatsa wrote: > From: Ville Syrjälä > > For MTL, changing cdclk from between certain frequencies has > both squash and crawl. Use the current cdclk config and > the new(desired) cdclk config to construtc a mid cdclk config. > Set the cdclk twice:

Re: [Intel-gfx] [PATCH v5 18/19] drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode

Hi Niranjana, [...] > +/* > + * VM_BIND feature version supported. > + * > + * The following versions of VM_BIND have been defined: > + * > + * 0: No VM_BIND support. > + * > + * 1: In VM_UNBIND calls, the UMD must specify the exact mappings created > + *previously with VM_BIND, the ioctl wil

[Intel-gfx] [PATCH v2] drm/i915/guc: add CAT error handler

Bad GPU memory accesses can result in catastrophic error notifications being send from the GPU to the KMD via the GuC. Add a handler to process the notification by printing a kernel message and dumping the related engine state (if appropriate). Since the same CAT error can be reported twice, log on

[Intel-gfx] [PATCH v5 0/9] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes

This series fixes issues faced when an HDMI2.1 sink that does not support DSC is connected via HDMI2.1PCON. It also includes other minor HDMI2.1 PCON fixes/refactoring. Patch 1-2 Have minor fixes/cleanups. Patch 3-6 Pull the decision making to use DFP conversion capabilities for every mode during

[Intel-gfx] [PATCH v5 2/9] drm/i915/display: Add new member in intel_dp to store ycbcr420 passthrough cap

New member to store the YCBCR20 Pass through capability of the DP sink. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/inte

[Intel-gfx] [PATCH v5 6/9] drm/i915/dp: Avoid DSC with output_format YCBC420

Currently, DSC with YCBCR420 is not supported. Return -EINVAL when trying with DSC with output_format as YCBCR420. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/

[Intel-gfx] [PATCH v5 3/9] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format

The decision to use DFP output format conversion capabilities should be during compute_config phase. This patch uses the members of intel_dp->dfp to only store the format conversion capabilities of the DP device and uses the crtc_state sink_format member, to program the protocol-converter for colo

[Intel-gfx] [PATCH v5 1/9] drm/i915/display: Add new member to configure PCON color conversion

The decision to use DFP output format conversion capabilities should be during compute_config phase. This patch adds new member to crtc_state to represent the final output_format to the sink. In case of a DFP this can be different than the output_format, as per the format conversion done via the P

[Intel-gfx] [PATCH v5 4/9] drm/i915/display: Use sink_format instead of ycbcr420_output flag

Start passing the sink_format, to all functions that take a bool ycbcr420_output as parameter. This will make the functions generic, and will serve as a slight step towards 4:2:2 support later. Suggested-by: Ville Syrj_l_ Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c

[Intel-gfx] [PATCH v5 8/9] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP

During FRL bandwidth check for downstream HDMI2.1 sink, the min BPC supported is incorrectly taken for DP, and the check does not consider ybcr420 only modes. This patch fixes the bandwidth calculation similar to the TMDS case, by taking min 8Bpc and considering Ycbcr420 only modes. v2: Rebase S

[Intel-gfx] [PATCH v5 7/9] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC

Currently we use the highest input BPC supported by DP sink while using DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same input BPC that is used between Source and the PCON without DSC, which might not work

[Intel-gfx] [PATCH v5 5/9] drm/i915/display: Add helper function to check if sink_format is 420

Add an inline helper function to check if the sink_format is set to YCBCR420 format. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++ drivers/gpu/drm/i915/display/intel_dp.c| 4 ++-- drivers/gpu/drm/i915/display/intel_hdmi.c |

[Intel-gfx] [PATCH v5 9/9] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints

Add a wrapper function to check dp_downstream clock/bandwidth constraints. Based on whether the sink supports FRL/TMDS the wrapper calls the appropriate FRL/TMDS functions. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 51 +++-- 1 file changed, 2

[Intel-gfx] [PATCH v2 0/1] Add selftest for slpc tile interaction

This test runs a workload on tiles simultaneously by requesting for RP0 frequency and fails if there is a throttling error. Rev2 : Fix build error Riana Tauro (1): drm/i915/guc/slpc: Add selftest for slpc tile-tile interaction drivers/gpu/drm/i915/gt/selftest_slpc.c | 63

[Intel-gfx] [PATCH v2 1/1] drm/i915/guc/slpc: Add selftest for slpc tile-tile interaction

Run a workload on tiles simultaneously by requesting for RP0 frequency. Pcode can however limit the frequency being granted due to throttling reasons. This test fails if there is any throttling v2: Fix build error Signed-off-by: Riana Tauro --- drivers/gpu/drm/i915/gt/selftest_slpc.c | 63 +

Re: [Intel-gfx] [PATCH v2] drm/i915/guc: add CAT error handler

Hi, I can't really provide feedback on the GuC interactions so only some superficial comments below. On 28/10/2022 10:34, Andrzej Hajda wrote: Bad GPU memory accesses can result in catastrophic error notifications being send from the GPU to the KMD via the GuC. Add a handler to process the

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915/guc/slpc: Add selftest for slpc tile-tile interaction

Hi, I peeked inside from curiosity and was pleasantly surprise to see kthread_work is used! Some comments below. On 28/10/2022 10:50, Riana Tauro wrote: Run a workload on tiles simultaneously by requesting for RP0 frequency. Pcode can however limit the frequency being granted due to throttl

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/guc: add CAT error handler (rev2)

== Series Details == Series: drm/i915/guc: add CAT error handler (rev2) URL : https://patchwork.freedesktop.org/series/109865/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/i915_perf_types.h:319: warning: Function parameter or member 'lock' not de

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev5)

== Series Details == Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev5) URL : https://patchwork.freedesktop.org/series/107550/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./a

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: add CAT error handler (rev2)

== Series Details == Series: drm/i915/guc: add CAT error handler (rev2) URL : https://patchwork.freedesktop.org/series/109865/ State : success == Summary == CI Bug Log - changes from CI_DRM_12314 -> Patchwork_109865v2 Summary --- **S

[Intel-gfx] [PATCH 1/8] drm/dp_helper: Add helper to check if the sink supports given format with DSC

From: Ankit Nautiyal Add helper function to check if the DP sink supports DSC with the given output format. Signed-off-by: Ankit Nautiyal --- include/drm/display/drm_dp_helper.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display

[Intel-gfx] [PATCH v5 0/8] Enable YCbCr420 for VDSC

This patch series aims to enable the YCbCr420 format for DSC. Changes are mostly compute params related for hdmi,dp and dsi along with the addition of new rc_tables for native_420 and corresponding changes to macros used to fetch them. ---v2 -adding fields missed for vdsc_cfg [Vandita] -adding cor

[Intel-gfx] [PATCH v4 3/8] drm/i915: Adding the new registers for DSC

From: Suraj Kandpal Adding new DSC register which are introducted MTL onwards Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/i915_reg.h | 28 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h ind

[Intel-gfx] [PATCH 6/8] drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420

DSC_YCBCR420_Sink_Support entry is added to i915_dsc_fec_support_show to depict if sink supports DSC YCbCr420. Also, new debugfs entry is created to enforce YCbCr420 output format. This is required because of our driver policy. If a mode is supported in both RGB and YCbCr420 output formats by the s

[Intel-gfx] [PATCH 7/8] drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from debugfs

If force_dsc_ycbcr420_en is set through debugfs allow DSC iff output_format is INTEL_OUTPUT_FORMAT_YCBCR420. Signed-off-by: Swati Sharma --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i

[Intel-gfx] [PATCH v2 2/8] drm/i915/dp: Check if DSC supports the given output_format

From: Ankit Nautiyal Go with DSC only if the given output_format is supported. v2: Use drm helper to get DSC format support for sink. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 28 + 1 file changed, 28 insertions(+) diff --git a/driver

[Intel-gfx] [PATCH v4 5/8] drm/i915: Fill in native_420 field

From: Suraj Kandpal Now that we have laid the groundwork for YUV420 Enablement we fill up native_420 field in vdsc_cfg and add appropriate checks wherever required. ---v2 -adding native_422 field as 0 [Vandita] -filling in second_line_bpg_offset, second_line_offset_adj and nsl_bpg_offset in vds_

[Intel-gfx] [PATCH 8/8] drm/i915: Code styling fixes

Removed extra newlines and did few styling fixes. Signed-off-by: Swati Sharma --- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/in

[Intel-gfx] [PATCH v4 4/8] drm/i915: Enable YCbCr420 for VDSC

From: Suraj Kandpal Implementation of VDSC for YCbCr420. Signed-off-by: Suraj Kandpal --- .../gpu/drm/i915/display/intel_qp_tables.c| 187 -- .../gpu/drm/i915/display/intel_qp_tables.h| 4 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +- 3 files changed, 180

[Intel-gfx] ✓ Fi.CI.BAT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev5)

== Series Details == Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev5) URL : https://patchwork.freedesktop.org/series/107550/ State : success == Summary == CI Bug Log - changes from CI_DRM_12314 -> Patchwork_107550v5

[Intel-gfx] ✗ Fi.CI.DOCS: warning for Add selftest for slpc tile interaction (rev2)

== Series Details == Series: Add selftest for slpc tile interaction (rev2) URL : https://patchwork.freedesktop.org/series/110248/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/i915_perf_types.h:319: warning: Function parameter or member 'lock' not

[Intel-gfx] ✓ Fi.CI.BAT: success for Add selftest for slpc tile interaction (rev2)

== Series Details == Series: Add selftest for slpc tile interaction (rev2) URL : https://patchwork.freedesktop.org/series/110248/ State : success == Summary == CI Bug Log - changes from CI_DRM_12315 -> Patchwork_110248v2 Summary ---

Re: [Intel-gfx] [PATCH v2] drm/i915/guc: add CAT error handler

On 28.10.2022 12:06, Tvrtko Ursulin wrote: Hi, I can't really provide feedback on the GuC interactions so only some superficial comments below. On 28/10/2022 10:34, Andrzej Hajda wrote: Bad GPU memory accesses can result in catastrophic error notifications being send from the GPU to the KMD

[Intel-gfx] [PATCH v2] drm/i915/userptr: restore probe_range behaviour

The conversion looks harmless, however the addr value is updated inside the loop with the previous vm_end, which then incorrectly leads to for_each_vma_range() iterating over stuff outside the range we care about. Fix this by storing the end value separately. Also fix the case where the range doesn

Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests: add igt_vma_move_to_active_unlocked

On 24.10.2022 17:08, Andi Shyti wrote: Hi Andrzej, On Mon, Oct 24, 2022 at 04:05:57PM +0200, Andrzej Hajda wrote: On 21.10.2022 17:39, Andi Shyti wrote: Hi Andrzej, [...] +static inline int __must_check +igt_vma_move_to_active_unlocked(struct i915_vma *vma, struct i915_request *rq, +

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC

== Series Details == Series: Enable YCbCr420 for VDSC URL : https://patchwork.freedesktop.org/series/110253/ State : warning == Summary == Error: dim checkpatch failed 725469674e5e drm/dp_helper: Add helper to check if the sink supports given format with DSC -:20: CHECK:LINE_SPACING: Please u

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable YCbCr420 for VDSC

== Series Details == Series: Enable YCbCr420 for VDSC URL : https://patchwork.freedesktop.org/series/110253/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce the GSC CS

== Series Details == Series: Introduce the GSC CS URL : https://patchwork.freedesktop.org/series/110237/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12313_full -> Patchwork_110237v1_full Summary --- **FAILURE**

Re: [Intel-gfx] [PATCH v2] drm/i915/userptr: restore probe_range behaviour

* Matthew Auld [221028 09:07]: > The conversion looks harmless, however the addr value is updated inside > the loop with the previous vm_end, which then incorrectly leads to > for_each_vma_range() iterating over stuff outside the range we care > about. Fix this by storing the end value separately.

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dmabuf: fix sg_table handling in map_dma_buf

>-Original Message- >From: Intel-gfx On Behalf Of >Matthew Auld >Sent: Thursday, October 27, 2022 11:27 AM >To: intel-gfx@lists.freedesktop.org >Subject: [Intel-gfx] [PATCH 1/2] drm/i915/dmabuf: fix sg_table handling in >map_dma_buf > >We need to iterate over the original entries here for

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable YCbCr420 for VDSC

== Series Details == Series: Enable YCbCr420 for VDSC URL : https://patchwork.freedesktop.org/series/110253/ State : success == Summary == CI Bug Log - changes from CI_DRM_12316 -> Patchwork_110253v1 Summary --- **SUCCESS** No reg

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/userptr: restore probe_range behaviour (rev3)

== Series Details == Series: drm/i915/userptr: restore probe_range behaviour (rev3) URL : https://patchwork.freedesktop.org/series/110083/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/i915_perf_types.h:319: warning: Function parameter or member '

Re: [Intel-gfx] [PATCH v2] drm/i915/userptr: restore probe_range behaviour

On 28.10.2022 15:06, Matthew Auld wrote: The conversion looks harmless, however the addr value is updated inside the loop with the previous vm_end, which then incorrectly leads to for_each_vma_range() iterating over stuff outside the range we care about. Fix this by storing the end value separate

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/userptr: restore probe_range behaviour (rev3)

== Series Details == Series: drm/i915/userptr: restore probe_range behaviour (rev3) URL : https://patchwork.freedesktop.org/series/110083/ State : success == Summary == CI Bug Log - changes from CI_DRM_12316 -> Patchwork_110083v3 Summary --

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/dmabuf: fix sg_table handling in map_dma_buf (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/dmabuf: fix sg_table handling in map_dma_buf (rev2) URL : https://patchwork.freedesktop.org/series/110229/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/110229/revisions/2/mbox/ not

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dmabuf: fix sg_table handling in map_dma_buf

On 28/10/2022 14:55, Ruhl, Michael J wrote: -Original Message- From: Intel-gfx On Behalf Of Matthew Auld Sent: Thursday, October 27, 2022 11:27 AM To: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 1/2] drm/i915/dmabuf: fix sg_table handling in map_dma_buf We need to iterat

[Intel-gfx] [PATCH v2 1/4] drm/i915/dmabuf: fix sg_table handling in map_dma_buf

We need to iterate over the original entries here for the sg_table, pulling out the struct page for each one, to be remapped. However currently this incorrectly iterates over the final dma mapped entries, which is likely just one gigantic sg entry if the iommu is enabled, leading to us only mapping

[Intel-gfx] [PATCH v2 2/4] drm/i915/selftests: exercise GPU access from the importer

Using PAGE_SIZE here potentially hides issues so bump that to something larger. This should also make it possible for iommu to coalesce entries for us. With that in place verify we can write from the GPU using the importers sg_table, followed by checking that our writes match when read from the CPU

[Intel-gfx] [PATCH v2 3/4] drm/i915/dmabuf: dmabuf cleanup

From: "Michael J. Ruhl" Some minor cleanup of some variables for consistency. Normalize struct sg_table to sgt. Normalize struct dma_buf_attachment to attach. checkpatch issues sizeof(), !NULL updates. Cc: Tvrtko Ursulin Signed-off-by: Michael J. Ruhl Signed-off-by: Matthew Auld --- drivers

[Intel-gfx] [PATCH v2 4/4] drm/i915/dmabuf: Use scatterlist for_each_sg API

From: "Michael J. Ruhl" Update open coded for loop to use the standard scatterlist for_each_sg API. Cc: Tvrtko Ursulin Signed-off-by: Michael J. Ruhl Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --gi

Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/dmabuf: Use scatterlist for_each_sg API

On Fri, 28 Oct 2022 at 16:51, Matthew Auld wrote: > > From: "Michael J. Ruhl" > > Update open coded for loop to use the standard scatterlist > for_each_sg API. > > Cc: Tvrtko Ursulin > Signed-off-by: Michael J. Ruhl Reviewed-by: Matthew Auld > Signed-off-by: Matthew Auld > --- > drivers/gpu

Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/dmabuf: dmabuf cleanup

On Fri, 28 Oct 2022 at 16:51, Matthew Auld wrote: > > From: "Michael J. Ruhl" > > Some minor cleanup of some variables for consistency. > > Normalize struct sg_table to sgt. > Normalize struct dma_buf_attachment to attach. > checkpatch issues sizeof(), !NULL updates. > > Cc: Tvrtko Ursulin > Sig

Re: [Intel-gfx] Developing a new backlight driver for specific OLED screen

Hi, I come back on my problem regarding the development of a specific driver which controls the brightness of my OLED device. > If it's eDP and uses some proprietary DPCD brightness control mechanism, > I think in practice it usually is somewhat dependent on the GPU. > > (OTOH I realize you do

Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/dmabuf: fix sg_table handling in map_dma_buf

>-Original Message- >From: Auld, Matthew >Sent: Friday, October 28, 2022 11:50 AM >To: intel-gfx@lists.freedesktop.org >Cc: Landwerlin, Lionel G ; Tvrtko Ursulin >; Ville Syrjälä >; >Ruhl, Michael J >Subject: [PATCH v2 1/4] drm/i915/dmabuf: fix sg_table handling in >map_dma_buf > >We ne

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Send update also on invalidate

== Series Details == Series: drm/i915/psr: Send update also on invalidate URL : https://patchwork.freedesktop.org/series/110037/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12280 -> Patchwork_110037v1 Summary --- *

Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/selftests: exercise GPU access from the importer

>-Original Message- >From: Auld, Matthew >Sent: Friday, October 28, 2022 11:50 AM >To: intel-gfx@lists.freedesktop.org >Cc: Landwerlin, Lionel G ; Tvrtko Ursulin >; Ville Syrjälä >; >Ruhl, Michael J >Subject: [PATCH v2 2/4] drm/i915/selftests: exercise GPU access from the >importer > >Us

Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/selftests: exercise GPU access from the importer

On 28/10/2022 17:10, Ruhl, Michael J wrote: -Original Message- From: Auld, Matthew Sent: Friday, October 28, 2022 11:50 AM To: intel-gfx@lists.freedesktop.org Cc: Landwerlin, Lionel G ; Tvrtko Ursulin ; Ville Syrjälä ; Ruhl, Michael J Subject: [PATCH v2 2/4] drm/i915/selftests: exercise

Re: [Intel-gfx] [PATCH 3/5] drm/i915/mtl: add GSC CS interrupt support

On 10/28/2022 1:38 AM, Tvrtko Ursulin wrote: On 27/10/2022 23:15, Daniele Ceraolo Spurio wrote: The GSC CS re-uses the same interrupt bits that the GSC used in older platforms. This means that we can now have an engine interrupt coming out of OTHER_CLASS, so we need to handle that appropriat

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Send update also on invalidate (rev2)

== Series Details == Series: drm/i915/psr: Send update also on invalidate (rev2) URL : https://patchwork.freedesktop.org/series/110037/ State : success == Summary == CI Bug Log - changes from CI_DRM_12311 -> Patchwork_110037v2 Summary -

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/4] drm/i915/dmabuf: fix sg_table handling in map_dma_buf

== Series Details == Series: series starting with [v2,1/4] drm/i915/dmabuf: fix sg_table handling in map_dma_buf URL : https://patchwork.freedesktop.org/series/110261/ State : success == Summary == CI Bug Log - changes from CI_DRM_12317 -> Patchwork_110261v1 ==

Re: [Intel-gfx] [PATCH 5/5] drm/i915/mtl: don't expose GSC command streamer to the user

On 10/27/2022 8:40 PM, Matt Roper wrote: On Thu, Oct 27, 2022 at 03:15:54PM -0700, Daniele Ceraolo Spurio wrote: There is no userspace user for this CS yet, we only need it for internal kernel ops (e.g. HuC, PXP), so don't expose it. Signed-off-by: Daniele Ceraolo Spurio Cc: Matt Roper Si

Re: [Intel-gfx] [PATCH v1 1/7] vfio/ccw: create a parent struct

On Fri, 2022-10-28 at 12:51 -0400, Matthew Rosato wrote: > On 10/19/22 12:21 PM, Eric Farman wrote: > > Move the stuff associated with the mdev parent (and thus the > > subchannel struct) into its own struct, and leave the rest in > > the existing private structure. > > > > The subchannel will poi

Re: [Intel-gfx] [PATCH 5/5] drm/i915/mtl: don't expose GSC command streamer to the user

On Fri, Oct 28, 2022 at 10:14:05AM -0700, Ceraolo Spurio, Daniele wrote: > > > On 10/27/2022 8:40 PM, Matt Roper wrote: > > On Thu, Oct 27, 2022 at 03:15:54PM -0700, Daniele Ceraolo Spurio wrote: > > > There is no userspace user for this CS yet, we only need it for internal > > > kernel ops (e.g.

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: add CAT error handler (rev2)

== Series Details == Series: drm/i915/guc: add CAT error handler (rev2) URL : https://patchwork.freedesktop.org/series/109865/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12314_full -> Patchwork_109865v2_full Summary

[Intel-gfx] [PULL] drm-intel-next

Hi Dave and Daniel, Here goes the first chunk of drm-intel-next targeting 6.2 The highlight goes to Ville with many display related clean-up and improvement, some other MTL enabling work and many other fixes and small clean-ups. drm-intel-next-2022-10-28: - Hotplug code clean-up and organization

Re: [Intel-gfx] [PATCH 04/10] vfio: Move storage of allow_unsafe_interrupts to vfio_main.c

On Wed, Oct 26, 2022 at 03:24:42PM -0600, Alex Williamson wrote: > On Tue, 25 Oct 2022 15:17:10 -0300 > Jason Gunthorpe wrote: > > > This legacy module knob has become uAPI, when set on the vfio_iommu_type1 > > it disables some security protections in the iommu drivers. Move the > > storage for t

Re: [Intel-gfx] [PATCH 10/10] iommufd: Allow iommufd to supply /dev/vfio/vfio

On Wed, Oct 26, 2022 at 03:31:33PM -0600, Alex Williamson wrote: > On Tue, 25 Oct 2022 15:50:45 -0300 > Jason Gunthorpe wrote: > > > If the VFIO container is compiled out, give a kconfig option for iommufd > > to provide the miscdev node with the same name and permissions as vfio > > uses. > > >

Re: [Intel-gfx] [PATCH v1 3/7] vfio/ccw: move private initialization to callback

On Fri, 2022-10-28 at 14:52 -0400, Matthew Rosato wrote: > On 10/19/22 12:21 PM, Eric Farman wrote: > > There's already a device initialization callback that is > > used to initialize the release completion workaround. > > As discussed off-list, maybe clarify what callback you're talking > about h

[Intel-gfx] [PATCH] drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia

This workaround is added for Media Tile of MTL A step. It is to help pcode workaround which handles the hardware bug seen on CXL splitter during package C2/C3 transitins due to MC6 entry/exit. As a part of workaround pcode expect kmd to send mailbox message "media busy" when components of Media til

[Intel-gfx] ✗ Fi.CI.IGT: failure for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev5)

== Series Details == Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes (rev5) URL : https://patchwork.freedesktop.org/series/107550/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12314_full -> Patchwork_107550v5_full ==

[Intel-gfx] [PATCH 0/2] Fix for two GuC issues

From: John Harrison Fix for a deadlock issue between the GuC busyness stats worker and GT resets. Also fix kernel contexts not getting the correct scheduling priority at start of day. Signed-off-by: John Harrison John Harrison (2): drm/i915/guc: Properly initialise kernel contexts drm/i91

[Intel-gfx] [PATCH 2/2] drm/i915/guc: Don't deadlock busyness stats vs reset

From: John Harrison The engine busyness stats has a worker function to do things like 64bit extend the 32bit hardware counters. The GuC's reset prepare function flushes out this worker function to ensure no corruption happens during the reset. Unforunately, the worker function has an infinite wai

[Intel-gfx] [PATCH 1/2] drm/i915/guc: Properly initialise kernel contexts

From: John Harrison If a context has already been registered prior to first submission then context init code was not being called. The noticeable effect of that was the scheduling priority was left at zero (meaning super high priority) instead of being set to normal. This would occur with kernel

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia

== Series Details == Series: drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia URL : https://patchwork.freedesktop.org/series/110268/ State : warning == Summary == Error: dim checkpatch failed 33ed282c8b12 drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia -:118: CHECK:MACRO_ARG_REUSE: Macro argu

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia

== Series Details == Series: drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia URL : https://patchwork.freedesktop.org/series/110268/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Fix for two GuC issues

== Series Details == Series: Fix for two GuC issues URL : https://patchwork.freedesktop.org/series/110269/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk

> -Original Message- > From: Ville Syrjälä > Sent: Friday, October 28, 2022 2:05 AM > To: Srivatsa, Anusha > Cc: intel-gfx@lists.freedesktop.org; Vivekanandan, Balasubramani > > Subject: Re: [PATCH 1/2] drm/i915/display: Do both crawl and squash when > changing cdclk > > On Wed, Oct

[Intel-gfx] [PATCH 1/2] drm/i915/display: Do both crawl and squash when changing cdclk

From: Ville Syrjälä For MTL, changing cdclk from between certain frequencies has both squash and crawl. Use the current cdclk config and the new(desired) cdclk config to construtc a mid cdclk config. Set the cdclk twice: - Current cdclk -> mid cdclk - mid cdclk -> desired cdclk v2: Add check in

[Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL

As per bSpec MTL has 38.4 MHz Reference clock. Addin gthe cdclk tables and cdclk_funcs that MTL will use. v2: Revert to using bxt_get_cdclk() BSpec: 65243 Cc: Clint Taylor Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +- 1 file changed

Re: [Intel-gfx] [PATCH 2/2] drm/i915/dg2: Introduce Wa_18019271663

On Thu, Oct 27, 2022 at 02:28:53PM -0300, Gustavo Sousa wrote: > On Tue, Oct 25, 2022 at 11:03:35AM -0700, Matt Atwood wrote: > > Wa_18019271663 applies to all DG2 steppings and skus. > > > > Bspec:45809 > > Could we also add the reference to the BSpec containing the WA description? Good catch bs

[Intel-gfx] [PATCH] drm/i915: Set PROBE_PREFER_ASYNCHRONOUS

This driver often takes a good 100ms to start, but in some particularly bad cases takes more than 1 second. In surveying risk for this driver, I poked around for cross-device shared state, which can be a source of race conditions. GVT support (intel_gvt_devices) seems potentially suspect, but it h

Re: [Intel-gfx] [RFC] i915: make the probe asynchronous

Hi, On Thu, Aug 16, 2018 at 03:40:38PM +0800, Feng Tang wrote: > On Tue, Aug 14, 2018 at 11:39:48AM +0200, Takashi Iwai wrote: > > FYI, the upcoming 4.19 will have the completion in audio side binding, > > so this problem should be solved there. > > Really a great news! thanks for sharing For th

[Intel-gfx] [PATCH] drm/i915/mtl: Add missing steering table terminators

The termination entries were missing for a couple of the recently-added MTL steering tables. Fixes: f32898c94a10 ("drm/i915/xelpg: Add multicast steering") Fixes: a7ec65fc7e83 ("drm/i915/xelpmp: Add multicast steering for media GT") Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_gt_

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add selftest for slpc tile interaction (rev2)

== Series Details == Series: Add selftest for slpc tile interaction (rev2) URL : https://patchwork.freedesktop.org/series/110248/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12315_full -> Patchwork_110248v2_full Summary -

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/mtl: Add missing steering table terminators

== Series Details == Series: drm/i915/mtl: Add missing steering table terminators URL : https://patchwork.freedesktop.org/series/110279/ State : warning == Summary == Error: make htmldocs had i915 warnings ./drivers/gpu/drm/i915/i915_perf_types.h:319: warning: Function parameter or member 'lo

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Add missing steering table terminators

On Fri, Oct 28, 2022 at 03:40:22PM -0700, Matt Roper wrote: The termination entries were missing for a couple of the recently-added MTL steering tables. Fixes: f32898c94a10 ("drm/i915/xelpg: Add multicast steering") Fixes: a7ec65fc7e83 ("drm/i915/xelpmp: Add multicast steering for media GT") I

Re: [Intel-gfx] [PULL] drm-intel-next

On Fri, Oct 28, 2022 at 02:22:33PM -0400, Rodrigo Vivi wrote: > Hi Dave and Daniel, > > Here goes the first chunk of drm-intel-next targeting 6.2 > > The highlight goes to Ville with many display related clean-up > and improvement, some other MTL enabling work and many other > fixes and small cle

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia

== Series Details == Series: drm/i915/mtl: Add MC6 Wa_14017210380 for SAMedia URL : https://patchwork.freedesktop.org/series/110268/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12317 -> Patchwork_110268v1 Summary ---

[Intel-gfx] ✗ Fi.CI.BAT: failure for Fix for two GuC issues

== Series Details == Series: Fix for two GuC issues URL : https://patchwork.freedesktop.org/series/110269/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12317 -> Patchwork_110269v1 Summary --- **FAILURE** Serious

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk

== Series Details == Series: series starting with [1/2] drm/i915/display: Do both crawl and squash when changing cdclk URL : https://patchwork.freedesktop.org/series/110275/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12317 -> Patchwork_110275v1

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Set PROBE_PREFER_ASYNCHRONOUS

== Series Details == Series: drm/i915: Set PROBE_PREFER_ASYNCHRONOUS URL : https://patchwork.freedesktop.org/series/110277/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12317 -> Patchwork_110277v1 Summary --- **FAIL

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Add missing steering table terminators

== Series Details == Series: drm/i915/mtl: Add missing steering table terminators URL : https://patchwork.freedesktop.org/series/110279/ State : success == Summary == CI Bug Log - changes from CI_DRM_12317 -> Patchwork_110279v1 Summary

Re: [Intel-gfx] [PATCH] drm/i915/mtl: Add missing steering table terminators

On Fri, Oct 28, 2022 at 04:04:18PM -0700, Lucas De Marchi wrote: > On Fri, Oct 28, 2022 at 03:40:22PM -0700, Matt Roper wrote: > > The termination entries were missing for a couple of the recently-added > > MTL steering tables. > > > > Fixes: f32898c94a10 ("drm/i915/xelpg: Add multicast steering")

[Intel-gfx] ✗ Fi.CI.IGT: failure for Enable YCbCr420 for VDSC

== Series Details == Series: Enable YCbCr420 for VDSC URL : https://patchwork.freedesktop.org/series/110253/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12316_full -> Patchwork_110253v1_full Summary --- **FAILURE**

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