[Intel-gfx] [PATCH v3] drm/i915/rpl: Update pci ids for RPL P/U

Update pci device ids as per bspec for RPL P/U. Bpsec: 55376 v2: - Append new id's instead of replacing the existing in device id list define v3: - Fixed the commit messege with revision details. Signed-off-by: Dnyaneshwar Bhadane --- include/drm/i915_pciids.h | 8 ++-- 1 file changed, 6 i

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Define a final failure state when link training fails

== Series Details == Series: Define a final failure state when link training fails URL : https://patchwork.freedesktop.org/series/122644/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/122644/revisions/1/mbox/ not applied Applying: drm/i915/dp_lin

[Intel-gfx] [PATCH v2] drm/i915/rpl: Update pci ids for RPL P/U

Update pci device ids as per bspec for RPL P/U. Bpsec: 55376 Signed-off-by: Dnyaneshwar Bhadane --- include/drm/i915_pciids.h | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index e1e10dfbb661..21faa73db7ec 100644

Re: [Intel-gfx] [PATCH 10/42] drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()

> From: Luca Coelho > > It is irrelevant for the caller that the max lane count is being derived from > a FIA > register, so having "fia" in the function name is irrelevant. Rename the > function accordingly. > LGTM. Reviewed-by: Suraj Kandpal > Signed-off-by: Luca Coelho > Reviewed-by: Luc

Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()

> It is irrelevant for the caller that the max lane count is being derived from > a FIA > register, so having "fia" in the function name is irrelevant. Rename the > function accordingly. > > Signed-off-by: Luca Coelho LGTM. Reviewed-by: Suraj Kandpal > --- > drivers/gpu/drm/i915/display/int

Re: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func

> -Original Message- > From: Intel-gfx On Behalf Of Lucas > De Marchi > Sent: Wednesday, August 23, 2023 10:37 PM > To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org > Cc: Coelho, Luciano > Subject: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the >

Re: [Intel-gfx] [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd

> Subject: [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for > planar yuv on xe2lpd > > From: Juha-Pekka Heikkilä > > Enable odd size and panning for planar yuv formats. > > Cc: Suraj Kandpal > Signed-off-by: Juha-Pekka Heikkilä > Signed-off-by: Lucas De Marchi Maybe add the Bsp

[Intel-gfx] ✓ Fi.CI.BAT: success for Panel replay phase1 implementation (rev6)

== Series Details == Series: Panel replay phase1 implementation (rev6) URL : https://patchwork.freedesktop.org/series/94470/ State : success == Summary == CI Bug Log - changes from CI_DRM_13558 -> Patchwork_94470v6 Summary --- **SUCC

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation (rev6)

== Series Details == Series: Panel replay phase1 implementation (rev6) URL : https://patchwork.freedesktop.org/series/94470/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Panel replay phase1 implementation (rev6)

== Series Details == Series: Panel replay phase1 implementation (rev6) URL : https://patchwork.freedesktop.org/series/94470/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory

[Intel-gfx] ✓ Fi.CI.BAT: success for eDP DSC fixes (rev2)

== Series Details == Series: eDP DSC fixes (rev2) URL : https://patchwork.freedesktop.org/series/122792/ State : success == Summary == CI Bug Log - changes from CI_DRM_13558 -> Patchwork_122792v2 Summary --- **SUCCESS** No regress

[Intel-gfx] [PATCH v2 6/6] drm/i915/dp_link_training: Emit a link-status=Bad uevent with trigger property

When a link-training attempt fails, emit a uevent to user space that includes the trigger property, which in this case will be link-statue=Bad. This will allow userspace to parse the uevent property and better understand the reason for the previous modeset failure. Signed-off-by: Gil Dekel V2:

[Intel-gfx] [PATCH v2 5/6] drm/i915/dp_link_training: Set all downstream MST ports to BAD before retrying

Before sending a uevent to userspace in order to trigger a corrective modeset, we change the failing connector's link-status to BAD. However, the downstream MST branch ports are left in their original GOOD state. This patch utilizes the drm helper function drm_dp_set_mst_topology_link_status() to

[Intel-gfx] [PATCH v2 4/6] drm/i915: Move DP modeset_retry_work into intel_dp

Currently, link-training fallback is only implemented for SST, so having modeset_retry_work in intel_connector makes sense. However, we hope to implement link training fallback for MST in a follow-up patchset, so moving modeset_retry_work to indel_dp will make handling both SST and MST connectors s

[Intel-gfx] [PATCH v2 3/6] drm/dp_mst: Add drm_dp_set_mst_topology_link_status()

Unlike SST, MST can support multiple displays connected to a single connector. However, this also means that if the DisplayPort link to the top-level MST branch device becomes unstable, then every single branch device has an unstable link. Since there are multiple downstream ports per connector, s

[Intel-gfx] [PATCH v2 2/6] drm/i915/dp_link_training: Add a final failing state to link training fallback for MST

Currently, MST link training has no fallback. This means that if an MST base connector fails to link-train once, the training completely fails, which makes this case significantly more common than a complete SST link training failure. Similar to the final failure state of SST, this patch zeros out

[Intel-gfx] [PATCH v2 1/6] drm/i915/dp_link_training: Add a final failing state to link training fallback

Instead of silently giving up when all link-training fallback values are exhausted, this patch modifies the fallback's failure branch to reduces both max_link_lane_count and max_link_rate to zero (0) and continues to emit uevents until userspace stops attempting to modeset. By doing so, we ensure

[Intel-gfx] [PATCH v2 0/6] drm/i915/dp_link_training: Define a final failure state when link training fails

Next version of https://patchwork.freedesktop.org/series/122643/ Reorganize into: 1) Add for final failure state for SST and MST link training fallback. 2) Add a DRM helper for setting downstream MST ports' link-status state. 3) Make handling SST and MST connectors simpler via intel_dp. 4) Update

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for eDP DSC fixes (rev2)

== Series Details == Series: eDP DSC fixes (rev2) URL : https://patchwork.freedesktop.org/series/122792/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for eDP DSC fixes (rev2)

== Series Details == Series: eDP DSC fixes (rev2) URL : https://patchwork.freedesktop.org/series/122792/ State : warning == Summary == Error: dim checkpatch failed a622a8c6cd95 drm/display/dp: Default 8 bpc support when DSC is supported -:26: ERROR:SPACING: space required before the open paren

[Intel-gfx] [PATCH v4 6/6] drm/i915/panelreplay: enable/disable panel replay

TRANS_DP2_CTL register is programmed to enable panel replay from source and sink is enabled through panel replay dpcd configuration address. Bspec: 1407940617 v1: Initial version. v2: - Use pr_* flags instead psr_* flags. [Jouni] - Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jo

[Intel-gfx] [PATCH v4 5/6] drm/i915/panelreplay: Enable panel replay dpcd initialization for DP

Due to similarity panel replay dpcd initialization got added in psr function which is specific for edp panel. This patch enables panel replay initialization for dp connector. Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ 1 file changed, 3 insertions(+) diff

[Intel-gfx] [PATCH v4 2/6] drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro

Platforms having Display 13 and above will support panel replay feature of DP 2.0 monitor. Added a HAS_PANEL_REPLAY() macro to check for panel replay capability. v1: Initial version. v2: DISPLAY_VER() removed as HAS_DP20() is having platform check. [Jouni] Cc: Jouni Högander Signed-off-by: Anime

[Intel-gfx] [PATCH v4 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay

Modify existing PSR implementation to enable panel replay feature of DP 2.0 which is similar to PSR feature of EDP panel. There is different DPCD address to check panel capability compare to PSR and vsc sdp header is different. v1: Initial version. v2: - Set source_panel_replay_support flag under

[Intel-gfx] [PATCH v4 3/6] drm/i915/psr: Move psr specific dpcd init into own function

From: Jouni Högander This patch is preparing adding panel replay specific dpcd init. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 39 +--- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.

[Intel-gfx] [PATCH v4 1/6] drm/panelreplay: dpcd register definition for panelreplay

DPCD register definition added to check and enable panel replay capability of the sink. Cc: Jouni Högander Signed-off-by: Animesh Manna --- include/drm/display/drm_dp.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h i

[Intel-gfx] [PATCH v4 0/6] Panel replay phase1 implementation

Panel Replay is a power saving feature for DP 2.0 monitor and similar to PSR on EDP. These patches are basic enablement patches added on top of existing psr framework to enable full-screen live active frame update mode of panel replay. Panel replay also can be enabled in selective update mode whic

[Intel-gfx] [PATCH 1/2] drm/display/dp: Default 8 bpc support when DSC is supported

As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah. Apparently some panels that do support DSC, are not setting the bit for 8bpc. So always assume 8bpc support by DSC decoder, when DSC is claimed to be supported. v2: Use helper to check dsc support. (Ankit) Signed-off-by: Ankit

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/vrr: Compute VRR min/max based on highest clock mode for DRRS panel

== Series Details == Series: drm/i915/display/vrr: Compute VRR min/max based on highest clock mode for DRRS panel URL : https://patchwork.freedesktop.org/series/122812/ State : success == Summary == CI Bug Log - changes from CI_DRM_13558 -> Patchwork_122812v1 =

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display/vrr: Compute VRR min/max based on highest clock mode for DRRS panel

== Series Details == Series: drm/i915/display/vrr: Compute VRR min/max based on highest clock mode for DRRS panel URL : https://patchwork.freedesktop.org/series/122812/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dim

[Intel-gfx] [PATCH] drm/i915/display/vrr: Compute VRR min/max based on highest clock mode for DRRS panel

In case of a DRRS panel, there is a preferred panel mode and there is a downclock mode with lower pixel clock. But the Vtotal for both remains the same. This means even in downclocking mode the VRR Vtotal min/max should remain the same. So in this case always use the highest clock mode to compute V

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add missing CCS documentation.

== Series Details == Series: drm/i915: Add missing CCS documentation. URL : https://patchwork.freedesktop.org/series/122807/ State : success == Summary == CI Bug Log - changes from CI_DRM_13555 -> Patchwork_122807v1 Summary --- **SUC

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Add missing CCS documentation.

== Series Details == Series: drm/i915: Add missing CCS documentation. URL : https://patchwork.freedesktop.org/series/122807/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add missing CCS documentation.

== Series Details == Series: drm/i915: Add missing CCS documentation. URL : https://patchwork.freedesktop.org/series/122807/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory

Re: [Intel-gfx] [PATCH] drm/i915: Add missing CCS documentation.

On Wed, Aug 23, 2023 at 05:39:01PM -0400, Rodrigo Vivi wrote: > Let's introduce the basic documentation about CCS. > While doing that, also removed the legacy execution flag name. That flag > simply doesn't exist for CCS and it is not needed on current context > submission. Those flag names are onl

Re: [Intel-gfx] [Intel-xe] [PATCH 34/42] drm/i915/lnl: Start using CDCLK through PLL

On Wed, Aug 23, 2023 at 10:07:32AM -0700, Lucas De Marchi wrote: > From: Stanislav Lisovskiy > > Introduce correspondent definitions and for choosing between CD2X CDCLK > and PLL CDCLK as a source. > > Signed-off-by: Stanislav Lisovskiy > Signed-off-by: Lucas De Marchi > --- > drivers/gpu/drm

[Intel-gfx] [PATCH] drm/i915: Add missing CCS documentation.

Let's introduce the basic documentation about CCS. While doing that, also removed the legacy execution flag name. That flag simply doesn't exist for CCS and it is not needed on current context submission. Those flag names are only needed on legacy context, while on new ones we only need to pass the

Re: [Intel-gfx] [Intel-xe] [PATCH 33/42] drm/i915/lnl: Add CDCLK table

On Wed, Aug 23, 2023 at 10:07:31AM -0700, Lucas De Marchi wrote: > From: Stanislav Lisovskiy > > Add a new Lunar Lake CDCLK table from BSpec and also a helper function > in order to be able to find lowest possible CDCLK, which has required > MDCLK for the correspodent pixel rate. > > Bspec: 6886

[Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2)

== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 (rev2) URL : https://patchwork.freedesktop.org/series/122804/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13554 -> Patchwork_122804v2 Summary --- *

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Apply Wa_16018031267 / Wa_16018063123 (rev2)

== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 (rev2) URL : https://patchwork.freedesktop.org/series/122804/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123 (rev2)

== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 (rev2) URL : https://patchwork.freedesktop.org/series/122804/ State : warning == Summary == Error: dim checkpatch failed 00f4bda3e3b0 drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 -:11: WARNING:BAD_SIGN_OFF: Co-de

Re: [Intel-gfx] [Intel-xe] [PATCH 32/42] drm/i915/lnl: Introduce MDCLK

On Wed, Aug 23, 2023 at 10:07:30AM -0700, Lucas De Marchi wrote: > From: Stanislav Lisovskiy > > In Lunar Lake we now separate MDCLK from CDLCK, which used to be before > always 2 times CDCLK. Now we might afford lower CDCLK, while having > higher memory clock, so improving bandwidth and power c

Re: [Intel-gfx] [Intel-xe] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support

On Wed, Aug 23, 2023 at 10:07:29AM -0700, Lucas De Marchi wrote: > LNL's south display uses the same table as MTP. Check for LNL's fake PCH > to make it consistent with the other checks. > > The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in > other cases, uses the same as the

Re: [Intel-gfx] [Intel-xe] [PATCH 30/42] drm/i915/xe2lpd: Extend Wa_15010685871

On Wed, Aug 23, 2023 at 10:07:28AM -0700, Lucas De Marchi wrote: > Xe2_LPD also needs workaround 15010685871. > > Signed-off-by: Lucas De Marchi > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915

Re: [Intel-gfx] [Intel-xe] [PATCH 29/42] drm/i915/xe2lpd: Add support for HPD

On Wed, Aug 23, 2023 at 10:07:27AM -0700, Lucas De Marchi wrote: > From: Gustavo Sousa > > Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the > extra programming for hotplug inversion and DDI HPD filter duration is > not necessary anymore. As mtp_hpd_irq_setup() is reasonably sma

Re: [Intel-gfx] [Intel-xe] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM

On Wed, Aug 23, 2023 at 10:07:25AM -0700, Lucas De Marchi wrote: > From: Luca Coelho > > Starting from display version 20, we need to read the pin assignment > from the IOM TCSS_DDI_STATUS register instead of reading it from the > FIA. > > We use the pin assignment to decide the maximum lane cou

Re: [Intel-gfx] [Intel-xe] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels

On Wed, Aug 23, 2023 at 01:01:44PM -0700, Matt Roper wrote: On Wed, Aug 23, 2023 at 10:07:23AM -0700, Lucas De Marchi wrote: From: Gustavo Sousa The location of aux channels registers for Xe2 display changed w.r.t. the previous version. This is another case of "PICA register ordering where '

Re: [Intel-gfx] [Intel-xe] [PATCH 26/42] drm/i915/xe2lpd: Handle port AUX interrupts

On Wed, Aug 23, 2023 at 10:07:24AM -0700, Lucas De Marchi wrote: > From: Gustavo Sousa > > Differently from previous version, Xe2_LPD groups all port AUX interrupt > bits into PICA interrupt registers. > > BSpec: 68958, 69697 > Signed-off-by: Gustavo Sousa > Signed-off-by: Lucas De Marchi > --

Re: [Intel-gfx] [Intel-xe] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels

On Wed, Aug 23, 2023 at 10:07:23AM -0700, Lucas De Marchi wrote: > From: Gustavo Sousa > > The location of aux channels registers for Xe2 display changed w.r.t. > the previous version. This is another case of "PICA register ordering where 'A' comes after 'TC4.'" We should probably consolidate o

Re: [Intel-gfx] [Intel-xe] [PATCH 24/42] drm/i915/display: Remove FBC capability from fused off pipes

On Wed, Aug 23, 2023 at 10:07:22AM -0700, Lucas De Marchi wrote: > From: Clint Taylor > > If a particular pipe is disabled by fuse also remove the FBC for that > pipe. > > Bspec: 69464 > Cc: Anusha Srivatsa > Cc: Gustavo Sousa > Signed-off-by: Clint Taylor > Signed-off-by: Lucas De Marchi R

Re: [Intel-gfx] [Intel-xe] [PATCH 23/42] drm/i915/xe2lpd: FBC is now supported on all pipes

On Wed, Aug 23, 2023 at 10:07:21AM -0700, Lucas De Marchi wrote: > From: Matt Roper > > FBC is no longer limited by pipe. It looks like we lost the part of this patch that adds this to the xe2_lpd_display device info structure. Matt > > Bspec: 68881, 68904 > Signed-off-by: Matt Roper > Sign

Re: [Intel-gfx] [Intel-xe] [PATCH 21/42] drm/i915/xe2lpd: Add display power well

On Wed, Aug 23, 2023 at 12:44:56PM -0700, Matt Roper wrote: > On Wed, Aug 23, 2023 at 10:07:19AM -0700, Lucas De Marchi wrote: > > From: Ravi Kumar Vodapalli > > > > Add Display Power Well for LNL platform, mostly it is same as MTL > > platform so reused the code > > > > Changes are: > > 1. AUX_

Re: [Intel-gfx] [Intel-xe] [PATCH 21/42] drm/i915/xe2lpd: Add display power well

On Wed, Aug 23, 2023 at 10:07:19AM -0700, Lucas De Marchi wrote: > From: Ravi Kumar Vodapalli > > Add Display Power Well for LNL platform, mostly it is same as MTL > platform so reused the code > > Changes are: > 1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra >logic xel

Re: [Intel-gfx] [REGRESSION] HDMI connector detection broken in 6.3 on Intel(R) Celeron(R) N3060 integrated graphics

On Mon, Aug 21, 2023 at 11:27:29AM +0200, Maxime Ripard wrote: > On Tue, Aug 15, 2023 at 11:12:46AM +0300, Jani Nikula wrote: > > On Mon, 14 Aug 2023, Imre Deak wrote: > > > On Sun, Aug 13, 2023 at 03:41:30PM +0200, Linux regression tracking > > > (Thorsten Leemhuis) wrote: > > > Hi, > > > > > >>

Re: [Intel-gfx] [Intel-xe] [PATCH 20/42] drm/i915/xe2lpd: Register DE_RRMR has been removed

On Wed, Aug 23, 2023 at 10:07:18AM -0700, Lucas De Marchi wrote: > From: Clint Taylor > > Do not read DE_RRMR register after display version 20. This register > contains display state information during GFX state dumps. > > Bspec: 69456 > Cc: Anusha Srivatsa > Cc: Gustavo Sousa > Signed-off-by

Re: [Intel-gfx] [Intel-xe] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA

On Wed, Aug 23, 2023 at 10:07:16AM -0700, Lucas De Marchi wrote: > Some registers for DDI A/B moved to PICA and now follow the same format > as the ones for the PORT_TC ports. The wrapper here deals with 2 issues: > > - Share the implementation between xe2lpd and previous > platforms

[Intel-gfx] [PATCH v2 1/2] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123

From: Nirmoy Das Apply WABB blit for Wa_16018031267 / Wa_16018063123. Additionally, update the lrc selftest to exercise the new WABB changes. Signed-off-by: Jonathan Cavitt Co-developed-by: Nirmoy Das --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 + drivers/gpu/drm/i915/gt/intel_gt_ty

[Intel-gfx] [PATCH v2 2/2] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123

From: Nirmoy Das Set copy engine arbitration into round robin mode for part of Wa_16018031267 / Wa_16018063123 mitigation. Signed-off-by: Nirmoy Das Signed-off-by: Jonathan Cavitt --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++

[Intel-gfx] [PATCH v2 0/2] Apply Wa_16018031267 / Wa_16018063123

Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a fastcolor blit as WABB and setting the copy engine arbitration to round-robin mode. v2: - Rename old platform check in second patch to match declaration in first patch. - Refactor second patch name to match first patch. Sign

Re: [Intel-gfx] [Intel-xe] [PATCH 16/42] drm/i915/xe2lpd: Move D2D enable/disable

On Wed, Aug 23, 2023 at 10:07:14AM -0700, Lucas De Marchi wrote: > Bits to enable/disable and check state for D2D moved from > XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL. Make the functions As of Xe2, DDI_BUF_CTL is now renamed to "DDI_CTL_DE" in the spec, so you might want to toss a mention of the new r

[Intel-gfx] [PATCH 0/2] Apply Wa_16018031267 / Wa_16018063123

Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a fastcolor blit as WABB and setting the copy engine arbitration to round-robin mode. Signed-off-by: Nirmoy Das Signed-off-by: Jonathan Cavitt CC: Joonas Lahtinen CC: Rodrigo Vivi CC: Tomasz Mistat CC: Gregory F Germano CC:

[Intel-gfx] [PATCH 1/2] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123

From: Nirmoy Das Apply WABB blit for Wa_16018031267 / Wa_16018063123. Additionally, update the lrc selftest to exercise the new WABB changes. Signed-off-by: Jonathan Cavitt Co-developed-by: Nirmoy Das --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 + drivers/gpu/drm/i915/gt/intel_gt_ty

[Intel-gfx] [PATCH 2/2] drm/i915: Set copy engine arbitration for pipeblit WA

From: Nirmoy Das Set copy engine arbitration into round robin mode for part of Wa_16018031267 / Wa_16018063123 mitigation. Signed-off-by: Nirmoy Das Signed-off-by: Jonathan Cavitt --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++

[Intel-gfx] PR for GSC FW release 102.0.0.1655 for MTL

The following changes since commit 0e048b061bde79ad735c7b7b5161ee1bd3400150: Merge branch 'for-upstream' of https://github.com/CirrusLogic/linux-firmware (2023-08-14 13:03:41 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware mtl_gsc_1655 for you

Re: [Intel-gfx] [Intel-xe] [PATCH 15/42] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation

On Wed, Aug 23, 2023 at 10:07:13AM -0700, Lucas De Marchi wrote: > From: Stanislav Lisovskiy > > We now start calculating relative plane data rate for sursor plane as s/sursor/cursor/ > well, as instructed by BSpec and also treat cursor plane same way as > other planes, when doing allocation, i

Re: [Intel-gfx] [Intel-xe] [PATCH 14/42] drm/i915/lnl: Add fake PCH

On Wed, Aug 23, 2023 at 10:07:12AM -0700, Lucas De Marchi wrote: > From: Gustavo Sousa > > LNL has south display on the same SoC. As such, define a new fake PCH > entry for it. As mentioned on the earlier patches, either matching on display IP or PICA ID might be more appropriate than matching o

Re: [Intel-gfx] [Intel-xe] [PATCH 13/42] drm/i915: Re-order if/else ladder in intel_detect_pch()

On Wed, Aug 23, 2023 at 10:07:11AM -0700, Lucas De Marchi wrote: > Follow the convention of checking the last platform first and reword the > comment to convey there are more platforms than just DG1. > > Signed-off-by: Lucas De Marchi Reviewed-by: Matt Roper > --- > drivers/gpu/drm/i915/soc/i

Re: [Intel-gfx] [Intel-xe] [PATCH 12/42] drm/i915/lnl: Add display definitions

On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote: > From: Balasubramani Vivekanandan > > Add Lunar Lake platform definitions for i915 display. The support for > LNL will be added to the xe driver, with i915 only driving the display > side. Therefore define IS_LUNARLAKE to 0 to disa

Re: [Intel-gfx] [Intel-xe] [PATCH 11/42] drm/xe/lnl: Add IS_LUNARLAKE

On Wed, Aug 23, 2023 at 10:07:09AM -0700, Lucas De Marchi wrote: > From: Balasubramani Vivekanandan > > Add IS_LUNARLAKE in the compat-i915-headers. That macro, to be used by > the xe driver, checks for the platform, whereas the macro on the i915 > side is always false. Stepping back, do we real

Re: [Intel-gfx] [PATCH v5] drm/i915: Avoid circular locking dependency when flush delayed work on gt reset

On 8/23/2023 09:00, Daniel Vetter wrote: On Tue, Aug 22, 2023 at 11:53:24AM -0700, John Harrison wrote: On 8/11/2023 11:20, Zhanjun Dong wrote: This attempts to avoid circular locking dependency between flush delayed work and intel_gt_reset. When intel_gt_reset was called, task will hold a lock

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable Lunar Lake display

== Series Details == Series: Enable Lunar Lake display URL : https://patchwork.freedesktop.org/series/122799/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/122799/revisions/1/mbox/ not applied Applying: drm/i915: Start using plane scale factor fo

[Intel-gfx] ✗ Fi.CI.IGT: failure for HDCP MST aux issue fix (rev3)

== Series Details == Series: HDCP MST aux issue fix (rev3) URL : https://patchwork.freedesktop.org/series/122267/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13549_full -> Patchwork_122267v3_full Summary --- **FAIL

[Intel-gfx] [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd

From: Juha-Pekka Heikkilä Enable odd size and panning for planar yuv formats. Cc: Suraj Kandpal Signed-off-by: Juha-Pekka Heikkilä Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/

[Intel-gfx] [PATCH 35/42] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf

From: Stanislav Lisovskiy When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that change. Previsouly DBuf state and CDCLK were not anyhow coupled together. Now at compute stage when we know which CDCLK/MDCLK we ar

[Intel-gfx] [PATCH 34/42] drm/i915/lnl: Start using CDCLK through PLL

From: Stanislav Lisovskiy Introduce correspondent definitions and for choosing between CD2X CDCLK and PLL CDCLK as a source. Signed-off-by: Stanislav Lisovskiy Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_cdclk.c | 14 -- drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels

From: Gustavo Sousa The location of aux channels registers for Xe2 display changed w.r.t. the previous version. BSpec: 69010 Signed-off-by: Gustavo Sousa Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 43 - 1 file changed, 42 insertions(+)

[Intel-gfx] [PATCH 38/42] drm/i915/lnl: Serialize global state if mdclk/cdclk ratio changes.

From: Stanislav Lisovskiy mdclk_cdclk_ratio is a part of dbuf_state and if it changes, it requires hw to be poked, so we must serialize the global state in that case. Signed-off-by: Stanislav Lisovskiy Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_cdclk.c | 19

[Intel-gfx] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA

Some registers for DDI A/B moved to PICA and now follow the same format as the ones for the PORT_TC ports. The wrapper here deals with 2 issues: - Share the implementation between xe2lpd and previous platforms: there are minor layout changes, it's mostly the register lo

[Intel-gfx] [PATCH 41/42] drm/i915/xe2lpd: Update mbus on post plane updates

From: Stanislav Lisovskiy According to BSpec we need to write the MBUS CTL and DBUF CTL both for increasing CDCLK case (pre plane) and for decreasing CDCLK case (post plane). Make sure those updates are in place for Xe2-LPD. Since the mbus update is not only on pre-enable anymore, also rename th

[Intel-gfx] [PATCH 39/42] drm/i915/lnl: Add pll table for LNL platform

From: Ravi Kumar Vodapalli Add PLL Table for Lunar Lake platform. BSpec: 68862 Cc: Clint Taylor Cc: Anusha Srivatsa Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 411 ++- 1 file changed, 406 insertions(+

[Intel-gfx] [PATCH 42/42] drm/xe/lnl: Enable the display support

From: Balasubramani Vivekanandan Enable the display support for LUNARLAKE Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/xe_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 7fb00ea410a6..f723e19e8ca5 100

[Intel-gfx] [PATCH 19/42] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST

From: Matt Roper Since Xe2LPD technically has FlatCCS, it doesn't have AuxCCS registers like PLANE_AUX_DIST. However we currently have HAS_FLAT_CCS hardcoded to 0 since compression isn't ready; we need to make sure this doesn't cause the display code to go back to trying to write this register.

[Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func

From: Luca Coelho This makes the code a bit more symmetric and readable, especially when we start adding more display version-specific alternatives. Signed-off-by: Luca Coelho Link: https://lore.kernel.org/r/2023072121.369227-4-luciano.coe...@intel.com --- drivers/gpu/drm/i915/display/inte

[Intel-gfx] [PATCH 37/42] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane

From: Stanislav Lisovskiy Previously we always updated DBuf MBUS CTL and DBUF CTL regs after CDCLK has been changed(CDCLK_CTL), however for Xe2-LPD we can't do like that anymore. According to BSpec, we have to first update DBuf regs and then write CDCLK regs, when CDCLK is decreased, which we do

[Intel-gfx] [PATCH 40/42] drm/i915/lnl: Add support to check c10 phy link rate

From: Ravi Kumar Vodapalli Add support to check c10 phy link rate for LNL in intel_c10_phy_check_hdmi_link_rate() function. BSpec: 68862 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 --- 1 file changed, 8 inse

[Intel-gfx] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM

From: Luca Coelho Starting from display version 20, we need to read the pin assignment from the IOM TCSS_DDI_STATUS register instead of reading it from the FIA. We use the pin assignment to decide the maximum lane count. So, to support this change, add a new lnl_tc_port_get_max_lane_count() fun

[Intel-gfx] [PATCH 30/42] drm/i915/xe2lpd: Extend Wa_15010685871

Xe2_LPD also needs workaround 15010685871. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 420786

[Intel-gfx] [PATCH 16/42] drm/i915/xe2lpd: Move D2D enable/disable

Bits to enable/disable and check state for D2D moved from XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL. Make the functions mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic to work with multiple reg location and bitfield layout. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_ddi

[Intel-gfx] [PATCH 32/42] drm/i915/lnl: Introduce MDCLK

From: Stanislav Lisovskiy In Lunar Lake we now separate MDCLK from CDLCK, which used to be before always 2 times CDCLK. Now we might afford lower CDCLK, while having higher memory clock, so improving bandwidth and power consumption at the same time. This is prep work required to enable that. S

[Intel-gfx] [PATCH 29/42] drm/i915/xe2lpd: Add support for HPD

From: Gustavo Sousa Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the extra programming for hotplug inversion and DDI HPD filter duration is not necessary anymore. As mtp_hpd_irq_setup() is reasonably small, prefer to fork it into a new function for Xe2_LPD instead of adding a p

[Intel-gfx] [PATCH 17/42] drm/i915/xe2lpd: D2D Enable preserve bits in DDI_BUF_CTL

From: Clint Taylor Display Ver 20 moved the D2D Enable bit to DDI_BUF_CTL(DDI_CTL_DE) register. We used multiple variables for HDMI and DisplayPort copies of this register. Consolidate the various locations to use intel_digital_port saved_port_bits. Cc: Anusha Srivatsa Cc: Gustavo Sousa Cc: Ra

[Intel-gfx] [PATCH 33/42] drm/i915/lnl: Add CDCLK table

From: Stanislav Lisovskiy Add a new Lunar Lake CDCLK table from BSpec and also a helper function in order to be able to find lowest possible CDCLK, which has required MDCLK for the correspodent pixel rate. Bspec: 68861 Signed-off-by: Stanislav Lisovskiy Signed-off-by: Lucas De Marchi --- driv

[Intel-gfx] [PATCH 08/42] drm/i915/tc: make intel_tc_port_get_lane_mask() static

From: Luca Coelho This function is only used locally, so make it static and remove the definition from the header file. Signed-off-by: Luca Coelho Reviewed-by: Suraj Kandpal Link: https://lore.kernel.org/r/2023072121.369227-3-luciano.coe...@intel.com --- drivers/gpu/drm/i915/display/intel

[Intel-gfx] [PATCH 14/42] drm/i915/lnl: Add fake PCH

From: Gustavo Sousa LNL has south display on the same SoC. As such, define a new fake PCH entry for it. Signed-off-by: Gustavo Sousa Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/soc/intel_pch.c | 5 - drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++ 2 files changed, 6 insertions(+)

[Intel-gfx] [PATCH 26/42] drm/i915/xe2lpd: Handle port AUX interrupts

From: Gustavo Sousa Differently from previous version, Xe2_LPD groups all port AUX interrupt bits into PICA interrupt registers. BSpec: 68958, 69697 Signed-off-by: Gustavo Sousa Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++- drivers/gpu/drm/i915/

[Intel-gfx] [PATCH 10/42] drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()

From: Luca Coelho It is irrelevant for the caller that the max lane count is being derived from a FIA register, so having "fia" in the function name is irrelevant. Rename the function accordingly. Signed-off-by: Luca Coelho Reviewed-by: Lucas De Marchi Link: https://lore.kernel.org/r/20230721

[Intel-gfx] [PATCH 36/42] drm/i915/lnl: Add support for CDCLK initialization sequence

From: Ravi Kumar Vodapalli Add CDCLK initialization sequence changes and CDCLK set frequency sequence for LNL platform. CDCLK frequency change sequence is different for LNL compared to MTL when a change in mdclk/cdclk ratio is observed. Below are changes to be made: 1. In MBUS_CTL register tran

[Intel-gfx] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support

LNL's south display uses the same table as MTP. Check for LNL's fake PCH to make it consistent with the other checks. The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in other cases, uses the same as the previous platform. Bspec: 68971, 20124 Cc: Anusha Srivatsa Signed-off-by:

[Intel-gfx] [PATCH 20/42] drm/i915/xe2lpd: Register DE_RRMR has been removed

From: Clint Taylor Do not read DE_RRMR register after display version 20. This register contains display state information during GFX state dumps. Bspec: 69456 Cc: Anusha Srivatsa Cc: Gustavo Sousa Signed-off-by: Clint Taylor Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_gpu_

[Intel-gfx] [PATCH 22/42] drm/i915/xe2lpd: Add DC state support

From: Matt Roper Xe2_LPD supports DC5, DC6, and DC9 (DC3CO no longer exists). The overall programming and requirements to enter DC states are similar to those of Xe_LPD+ although AUX transactions do not require DC5/DC6 exit as they did previously. Bspec: 68851, 68857, 68886, 69115 Cc: Anusha Sr

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