> -Original Message-
> From: Intel-xe On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, May 22, 2024 11:04 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Maarten Lankhorst
> ; Borah, Chaitanya Kumar
>
> Subject: [v6 1/3] drm: Add drm_vblank_work_flush_
This reverts commit 86167183a17e03ec77198897975e9fdfbd53cb0b.
The commit moved igc_ptp_init() which initializes spinlocks after
igt_reset() which ends up using the adapter->ptp_tx_lock. Lockdep isn't
happy:
<3>[ 10.648947] INFO: trying to register non-static key.
<3>[ 10.648950] The code is f
> -Original Message-
> From: Intel-xe On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, May 22, 2024 11:04 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Ville Syrjälä
> ;
> Maarten Lankhorst
> Subject: [v6 2/3] drm/i915: Use vblank worker to unpin old
> -Original Message-
> From: Intel-xe On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, May 22, 2024 11:04 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Maarten Lankhorst
>
> Subject: [v6 3/3] drm/i915: Use the same vblank worker for atomic unpin
>
>
> -Original Message-
> From: Intel-xe On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, May 22, 2024 11:04 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org; Maarten Lankhorst
>
> Subject: [v6 0/3] Fix cursor FB unpinning.
>
> Hopefully last attempt.
> Sma
On Tue, 28 May 2024, "Borah, Chaitanya Kumar"
wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Jani
>> Nikula
>> Sent: Monday, May 27, 2024 4:41 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani
>> Subject: [PATCH 00/11] drm/i915: pass dev_priv explicitly to DIP
On Tue, 28 May 2024, "Borah, Chaitanya Kumar"
wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Jani
>> Nikula
>> Sent: Monday, May 27, 2024 4:12 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani ; ville.syrj...@linux.intel.com
>> Subject: [PATCH 0/6] drm/i915/pps:
The dispcnlunit1_cp_xosc_clk should be de-asserted in display off
and only asserted in display on. But during observation it found
clk remains active in display OFF. As workaround, Display driver
shall execute set-reset sequence at the end of the Initialize
Sequence.
Wa_15013987218
Mitul Golani (
The dispcnlunit1_cp_xosc_clk should be de-asserted in display off
and only asserted in display on. But during observation it found
clk remains active in display OFF. As workaround, Display driver
shall execute set-reset sequence at the end of the Initialize
Sequence.
Wa_15013987218
Signed-off-by:
== Series Details ==
Series: Revert "igc: fix a log entry using uninitialized netdev"
URL : https://patchwork.freedesktop.org/series/134112/
State : warning
== Summary ==
Error: dim checkpatch failed
a37e219fcbae Revert "igc: fix a log entry using uninitialized netdev"
-:16: WARNING:COMMIT_LOG
== Series Details ==
Series: Revert "igc: fix a log entry using uninitialized netdev"
URL : https://patchwork.freedesktop.org/series/134112/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14828 -> Patchwork_134112v1
Summary
On 5/24/2024 3:54 PM, Mitul Golani wrote:
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unr
> -Original Message-
> From: Intel-gfx On Behalf Of Jani
> Nikula
> Sent: Tuesday, May 28, 2024 1:16 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: [core-for-CI PATCH] Revert "igc: fix a log entry using uninitialized
> netdev"
>
> This reverts commit 86167183a1
On 5/24/2024 3:54 PM, Mitul Golani wrote:
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Variable refresh mode
wi
On 5/24/2024 3:54 PM, Mitul Golani wrote:
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
Add prefix : drm/dp, also need to send to dri-devel.
Regards,
Ankit
Signed-off-by: Mitul Golani
Reviewed-by: Arun R
On 5/24/2024 3:54 PM, Mitul Golani wrote:
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 4
1 file changed, 4 insertion
On Tue, 28 May 2024, Patchwork wrote:
> == Series Details ==
>
> Series: Revert "igc: fix a log entry using uninitialized netdev"
> URL : https://patchwork.freedesktop.org/series/134112/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_14828 -> Patchwork_134112v1
> ==
On 5/24/2024 3:54 PM, Mitul Golani wrote:
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/g
Move the handling of the disabling FBC when VT-d is active wa
as part of the intel_fbc_check_plane()
Bspec: 21664
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/drivers/gp
On Tue, 28 May 2024, Vinod Govindapillai wrote:
> Move the handling of the disabling FBC when VT-d is active wa
> as part of the intel_fbc_check_plane()
I can see that from the code.
The commit message must answer the question "why".
BR,
Jani.
>
> Bspec: 21664
> Signed-off-by: Vinod Govindapil
== Series Details ==
Series: Fix cursor FB unpinning. (rev2)
URL : https://patchwork.freedesktop.org/series/133896/
State : warning
== Summary ==
Error: dim checkpatch failed
a371966b2783 drm: Add drm_vblank_work_flush_all().
-:11: WARNING:BAD_SIGN_OFF: 'Co-developed-by:' is the preferred sign
== Series Details ==
Series: Fix cursor FB unpinning. (rev2)
URL : https://patchwork.freedesktop.org/series/133896/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: war
> -Original Message-
> From: Intel-gfx On Behalf Of Suraj
> Kandpal
> Sent: Monday, May 27, 2024 10:51 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Roper,
> Matthew D ; Kandpal, Suraj
>
> Subject: [PATCH] drm/i915/hdcp: Fix IS_METEORLAKE usage for HDCP line
>
Move the handling of the disabling FBC when VT-d is active wa
as part of the intel_fbc_check_plane(). As the hw is still there,
intel_fbc_sanitize should be able to handle the state properly.
v2: update the patch description (Jani Nikula)
Bspec: 21664
Suggested-by: Ville Syrjälä
Signed-off-by: V
== Series Details ==
Series: Fix cursor FB unpinning. (rev2)
URL : https://patchwork.freedesktop.org/series/133896/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14829 -> Patchwork_133896v2
Summary
---
**SUCCESS**
+ drm-core maintainer
Hi,
Could you please have a look and ack this patch.
Received r-b from Jouni on 0th patch for the whole patch series.
Regards,
Animesh
> -Original Message-
> From: Intel-gfx On Behalf Of
> Animesh Manna
> Sent: Monday, May 27, 2024 1:57 PM
> To: intel-gfx@lists.
On Mon, May 13, 2024 at 08:59:36PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Different hardware generations have different scanout alignment
> requirements. Introduce a new vfunc that will allow us to
> make that distinction without horrible if-ladders.
>
> For now we directly plug i
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Tuesday, May 28, 2024 1:48 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH v1 1/1] drm/i915/display: WA for Re-initialize dispcnlunitt1
> xosc
> clock
>
> The dispcnlunit1_cp_xosc_clk should be de-ass
> -Original Message-
> From: Garg, Nemesa
> Sent: Tuesday, May 28, 2024 4:23 PM
> To: Mitul Golani ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [PATCH v1 1/1] drm/i915/display: WA for Re-initialize
> dispcnlunitt1
> xosc clock
>
>
> > -Original Message-
> > From: Intel
On Tue, May 28, 2024 at 10:04:06AM GMT, Manna, Animesh wrote:
> + drm-core maintainer
>
> Hi,
>
> Could you please have a look and ack this patch.
> Received r-b from Jouni on 0th patch for the whole patch series.
Acked-by: Maxime Ripard
Maxime
signature.asc
Description: PGP signature
Jani Nikula (5):
drm/i915/gvt: use proper macros for DP AUX CH CTL registers
drm/i915: remove unused DP AUX CH register macros
drm/i915: rearrange DP AUX register macros
drm/i915: move PCH DP AUX CH regs to intel_dp_aux_regs.h
drm/i915: remove intermediate _PCH_DP_* macros
.../gpu/drm/i
Use the proper helpers for DP AUX CH CTL registers, instead of
reinventing the wheels.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gvt/handlers.c | 35 ++---
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++---
2 files changed, 20 insertions(+), 23 deletions(-)
The intermediate macros are no longer needed.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 14 --
1 file changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index be57812a6b07..989cc5691490 100644
--- a/drivers/
Follow the recommended style for grouping register macros.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_aux_regs.h | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
b/drivers/gpu/drm/i915/displ
Move the macros where they belong.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_aux_regs.h | 8
drivers/gpu/drm/i915/i915_reg.h | 7 ---
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_
The intermediate macros are unused. Remove them.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 06e41afd5c4e..6877e2f0fbc3 10064
On Tue, 28 May 2024, Vinod Govindapillai wrote:
> Move the handling of the disabling FBC when VT-d is active wa
> as part of the intel_fbc_check_plane(). As the hw is still there,
> intel_fbc_sanitize should be able to handle the state properly.
>
> v2: update the patch description (Jani Nikula)
>
On Tue, 2024-05-28 at 14:19 +0300, Jani Nikula wrote:
> On Tue, 28 May 2024, Vinod Govindapillai
> wrote:
> > Move the handling of the disabling FBC when VT-d is active wa
> > as part of the intel_fbc_check_plane(). As the hw is still there,
> > intel_fbc_sanitize should be able to handle the sta
== Series Details ==
Series: WA for Re-initialize dispcnlunitt1 xosc clock
URL : https://patchwork.freedesktop.org/series/134114/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14831 -> Patchwork_134114v1
Summary
---
On Mon, May 13, 2024 at 08:59:37PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Different planes could have different alignment requirements
> even for the same format/modifier. Collect the alignment
> requirements across all planes capable of scanning out the
> fb such that the alignmen
Hi,
Here's a couple of patches to prevent some static analyzer warnings.
They are not really an issue as is, but with these two patches the
code will be cleaner and a bit safer, while at the same time silencing
these warnings.
Plese review.
Cheers,
Luca.
Luca Coelho (2):
drm/i915/bios: doubl
During static analysis, a concern was raised that we may access the
dtd->dtd[] array out of bounds, because we are not checking whether
the index we use is larger than the array.
This should not be a problem as is, because the enumeration that is
used for this index comes from "panel_type", which
In intel_crtc_vblank_work(), we access uapi.event before grabbing the
event_lock spinlock, but modify it inside the spinlock block. This
causes some static analyzers to get confused and issue a warning.
The uapi.event value is not protected by the event_lock, so we can
safely move it out of the p
On Tue, May 28, 2024 at 02:27:58PM +0300, Imre Deak wrote:
> [...]
> > +}
> > +
> > static unsigned int
> > intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state)
> > {
> > struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> > - const struct drm_frameb
On Mon, May 13, 2024 at 08:59:38PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Split intel_cursor_alignment() into per-platform variants.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 40 +++--
> drive
This is a subset of Panel Replay eDP patch set
(https://patchwork.freedesktop.org/series/133684). This contains
debugfs changes and is supposed to be safe to be merged alone Sending
here to get CI result for this subset before merging.
Jouni Högander (5):
drm/i915/psr: Store pr_dpcd in intel_dp
We need pr_dpcd contents for early transport validity check on eDP Panel
Replay and in debugfs interface to dump out panel early transport
capability. Also remove unnecessarily printing out "Panel replay is not
supported by panel"
v2: commit message modified
Signed-off-by: Jouni Högander
Reviewe
Add PANEL_REPLAY_CONFIGURATION_2 register and some missing Panel Replay
bits.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
Acked-by: Maxime Ripard
---
include/drm/display/drm_dp.h | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/include/drm/disp
intel_psr_status has grown and is about to grow even. Let's split it a bit
and move printing PSR mode to an own function.
v2: s/intel_psr_psr_mode/intel_psr_print_mode/
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 26 --
Some PSR2_CTL bits are applicable for eDP panel replay as well.
Dump this register for eDP Panel Replay as well.
Bspec: 68920
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
intel_psr_status has grown and is about to grow even. Let's split it a bit
and move printing sink psr support to an own function.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 22 +++---
1 file changed, 15 insertions(+),
Move the handling of the disabling FBC when VT-d is active wa
as part of the intel_fbc_check_plane(). As the hw is still there,
intel_fbc_sanitize should be able to handle the state properly.
v2: update the patch description (Jani Nikula)
v3: fix the return value in wa handling (Jani Nikula)
Bsp
== Series Details ==
Series: drm/i915/display: update handling of FBC when VT-d active workaround
(rev2)
URL : https://patchwork.freedesktop.org/series/134117/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14831 -> Patchwork_134117v2
==
On Mon, May 13, 2024 at 08:59:39PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Extract the necessary chunks from intel_surf_alignment()
> into per-platform variants for all pre-skl primary/sprite
> planes.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/i9xx_pla
On Mon, May 13, 2024 at 08:59:40PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Now that all pre-skl platforms have their own .min_alignment()
> functions the remainder of intel_surf_alignment() can be hoisted
> into skl_univerals_plane.c (and renamed appropriately).
>
> Signed-off-by:
== Series Details ==
Series: drm/i915: DP AUX CH macro cleanups
URL : https://patchwork.freedesktop.org/series/134123/
State : warning
== Summary ==
Error: dim checkpatch failed
ca25b65c7605 drm/i915/gvt: use proper macros for DP AUX CH CTL registers
f1103051a69e drm/i915: remove unused DP AUX
== Series Details ==
Series: drm/i915: DP AUX CH macro cleanups
URL : https://patchwork.freedesktop.org/series/134123/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14831 -> Patchwork_134123v1
Summary
---
**SUCCESS**
Hi,
commit 7e89efc6e9e402839643cb297bab14055c547f07
Author: Dave Jiang
Date: Thu May 2 09:57:31 2024 -0700
PCI: Lock upstream bridge for pci_reset_function()
introduced the WARN below in the VMD driver, see [1] for the full log.
Not sure if the annotation is incorrect or the VMD driver is
== Series Details ==
Series: drm/i915: prevent some static analyzer warnings
URL : https://patchwork.freedesktop.org/series/134124/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bit
== Series Details ==
Series: drm/i915: prevent some static analyzer warnings
URL : https://patchwork.freedesktop.org/series/134124/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14831 -> Patchwork_134124v1
Summary
---
Acked-by: Maarten Lankhorst
Den 2024-05-27 kl. 09:22, skrev Jouni Högander:
Add PANEL_REPLAY_CONFIGURATION_2 register and some missing Panel Replay
bits.
Signed-off-by: Jouni Högander
---
include/drm/display/drm_dp.h | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
On Mon, May 13, 2024 at 08:59:41PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we still use the SKL+ PLANE_SURF alignment even
> for TGL+ even though the hardware no longer needs it.
> Introduce a separate tgl_plane_min_alignment() and update
> it to more accurately reflect th
kernel test robot writes:
> tree/branch:
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> branch HEAD: 124cfbcd6d185d4f50be02d5f5afe61578916773 Add linux-next
> specific files for 20240521
[...]
> Error/Warning ids grouped by kconfigs:
>
> gcc_recent_errors
[..
On 2024-05-22 09:25:54, Dmitry Baryshkov wrote:
> This panel driver uses DSC PPS functions and as such depends on the
> DRM_DISPLAY_DP_HELPER. Select this symbol to make required functions
Here and in the title: maybe this is a remnant from v2, but you split out a
DRM_DISPLAY_DSC_HELPER and should
On Mon, May 13, 2024 at 08:59:42PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> I don't think the display hardware really has such chroma
> plane tile row alignment requirements as outlined in
> commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar
> UV plane is tile row size aligne
== Series Details ==
Series: Panel Replay eDP debugfs support
URL : https://patchwork.freedesktop.org/series/134125/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
This is a rewitten version of [1]. I think it's good progress overall
though there are still minor issues here and there.
BR,
Jani.
[1] https://lore.kernel.org/all/20240408172315.3418692-1-jani.nik...@intel.com/
Jani Nikula (12):
drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_late
Clarify and unify the logging on not finding PNV CxSR latency config.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
b/drivers/gpu/drm/i915/displa
To simplify further changes, add separate functions for reading the fsb
frequency.
This ends up reading CLKCFG register twice, but it's not a big deal.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 106 +++---
1 file changed, 60 insertions(+), 46 del
Clarify that the function is specific to PNV, making subsequent changes
slightly easier to grasp.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
b/drivers/gpu/
Split out the PNV DDR3 detection to a distinct step instead of
conflating it with mem freq detection.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/dri
Follow the same style in mem freq init as in fsb freq init, returning
the value instead of assigning in multiple places.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 59 ---
1 file changed, 25 insertions(+), 34 deletions(-)
diff --git a/drivers/
We'll want to use fsb frequency for deriving GT clock and rawclk
frequencies in the future. Increase the accuracy by converting to
kHz. Do the same for mem freq to be aligned.
Round the frequencies ending in 666 to 667.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 6
Initialize fsb frequency for more platforms to be able to use it for GT
clock and rawclk frequency initialization.
Note: There's a discrepancy between existing pnv_fsb_freq() and
i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
mobile.
FIXME: What should the default or failure m
Reuse i9xx_fsb_freq() for GT clock frequency initialization instead of
depending on rawclk_freq.
Note: If the init order was changed, we could use i915->fsb_freq
directly. However, GT clock initialization is done in
i915_driver_mmio_probe(), but intel_dram_detect() later in
i915_driver_hw_probe(),
Instead of duplicating the CLKCFG parsing, reuse i9xx_fsb_freq() to
figure out rawclk_freq where applicable.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ++
1 file changed, 3 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/
The rawclk initialization is a bit out of place in
intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a
bit of refactoring on intel_read_rawclk().
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++---
drivers/gpu/drm/i915/displa
It's mostly about display, so move it under display.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_backlight.c | 10 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_device.c| 2 ++
drivers/gpu/
With rawclk_freq moved to display runtime info, xe has no users left for
them.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 -
drivers/gpu/drm/xe/xe_device_types.h | 6 --
2 files changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/xe/co
== Series Details ==
Series: Panel Replay eDP debugfs support
URL : https://patchwork.freedesktop.org/series/134125/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14833 -> Patchwork_134125v1
Summary
---
**SUCCESS**
On 5/28/24 5:36 AM, Imre Deak wrote:
> Hi,
>
> commit 7e89efc6e9e402839643cb297bab14055c547f07
> Author: Dave Jiang
> Date: Thu May 2 09:57:31 2024 -0700
>
> PCI: Lock upstream bridge for pci_reset_function()
>
> introduced the WARN below in the VMD driver, see [1] for the full log.
>
== Series Details ==
Series: drm/i915/display: update handling of FBC when VT-d active workaround
(rev3)
URL : https://patchwork.freedesktop.org/series/134117/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14834 -> Patchwork_134117v3
==
== Series Details ==
Series: drm/i915: mem/fsb/rawclk freq cleanups
URL : https://patchwork.freedesktop.org/series/134145/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: mem/fsb/rawclk freq cleanups
URL : https://patchwork.freedesktop.org/series/134145/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14835 -> Patchwork_134145v1
Summary
---
**SUCCE
On Mon, May 27, 2024 at 04:00:25PM +0100, Andi Shyti wrote:
> On Mon, May 27, 2024 at 11:47:49AM +0100, Andi Shyti wrote:
> > On Fri, May 24, 2024 at 10:07:44AM -0400, Rodrigo Vivi wrote:
> > > On Fri, May 24, 2024 at 01:58:53AM +0200, Andi Shyti wrote:
> > > > Following the guidelines it takes 3 s
On Tue, May 28, 2024 at 02:29:01PM +0300, Luca Coelho wrote:
> In intel_crtc_vblank_work(), we access uapi.event before grabbing the
> event_lock spinlock, but modify it inside the spinlock block. This
> causes some static analyzers to get confused and issue a warning.
>
> The uapi.event value is
On Tue, May 28, 2024 at 02:29:00PM +0300, Luca Coelho wrote:
> During static analysis, a concern was raised that we may access the
> dtd->dtd[] array out of bounds, because we are not checking whether
> the index we use is larger than the array.
>
> This should not be a problem as is, because the
On 5/21/2024 11:25 PM, Dmitry Baryshkov wrote:
Currently the DRM DSC functions are selected by the
DRM_DISPLAY_DP_HELPER Kconfig symbol. This is not optimal, since the DSI
code (both panel and host drivers) end up selecting the seemingly
irrelevant DP helpers. Split the DSC code to be guarded
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 6dc544b66971c7f9909ff038b62149105272d26a Add linux-next specific
files for 20240528
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202405282036.maedo54q-...@intel.com
https
From: Ville Syrjälä
Various parts of the cdclk code need access the full atomic
state. Currently it's being dug out via the cdclk_state->base.state
pointer, which is not great as that pointer isn't always valid.
Instead plumb the full atomic state from the top so that it's
clear that it is in fac
From: Ville Syrjälä
icl_check_nv12_planes() needs the full atomic state. Instead of
digging that out from dubious sources plumb it in explicitly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
dif
From: Ville Syrjälä
skl_ddb_add_affected_planes() needs the full atomic state. Instead
of digging that out from dubious sources plumb it in explicitly.
The wm counterpart (skl_wm_add_affected_planes()) already does
things in the proper way.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i91
From: Ville Syrjälä
A few cleanups around parts what deal with scanline numbers.
Ville Syrjälä (7):
drm/i915: Reuse intel_mode_vblank_start()
drm/i915: Extract intel_mode_vblank_end()
drm/i915: Extract intel_mode_vtotal()
drm/i915: Simplify scanline_offset handling for gen2
drm/i915: M
From: Ville Syrjälä
Replace a few hand rolled copies of intel_mode_vblank_start() with
the real thing.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dsb.c| 10 +++---
drivers/gpu/drm/i915/display/intel_vblank.c | 9 +++--
drivers/gpu/drm/i915/display/intel_vb
From: Ville Syrjälä
We have several copies of code calculating the hardware's
idea of vtotal. Pull that to a helper, similar to
intel_mode_vblank_{start,end}().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vblank.c | 40 +
drivers/gpu/drm/i915/display
From: Ville Syrjälä
Currently intel_crtc_scanline_offset() is careful to always
return a positive offset. That is not actually necessary
as long as we take care of negative values when applying the
offset in __intel_get_crtc_scanline().
This simplifies intel_crtc_scanline_offset(), and makes
the
From: Ville Syrjälä
I want to use intel_crtc_scanline_offset() in
intel_crtc_scanline_to_hw(). Relocate intel_crtc_scanline_offset()
a bit to avoid a forward declaration.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vblank.c | 76 ++---
1 file changed, 38
From: Ville Syrjälä
Extract intel_mode_vblank_end() in the same vein as
intel_mode_vblank_start(). While we have only one use
of this it seems nicer to unify the approach.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_vblank.c | 16
drivers/gpu/drm/i915/d
From: Ville Syrjälä
Currently we switch from out software idea of a scanline
to the hw's idea of a scanline during the commit phase in
_intel_dsb_commit(). While that is slightly easier due to
fastsets fiddling with the timings, we'll also need to
generate proper hw scanline numbers already when
From: Ville Syrjälä
Dotclocks can reach ~1GHz these days, so intel_usecs_to_scanlines(),
with its 32bit maths, is currently limited to a few milliseconds.
I want bigger numbers in DSB selftests, so switch over to 64bit
maths.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_
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