on CPU
> Si used as CPU and PCH can be mixed and matched".
>
> Bspec: 20124
> Cc: Matt Atwood
> Cc: Matt Roper
> Signed-off-by: Clinton Taylor
> Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
> drive
t; Add 12 known PCI device IDs
>
> Bspec: 55376
> Cc: Caz Yokoyama
> Cc: Matt Atwood
> Cc: Matt Roper
> Signed-off-by: Clinton Taylor
> Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
> ---
> include/drm/i915_pciids.h | 20
> 1 file changed,
VT-d is active, the memory bandwidth usage of the display is 5% higher.
> Take this into account when determining whether we can support a display
> configuration.
>
> Bspec: 64631
> Cc: Matt Atwood
> Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
> ---
> driver
> -Original Message-
> From: Roper, Matthew D
> Sent: Thursday, March 11, 2021 2:36 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; Srivatsa, Anusha
> ; De Marchi, Lucas
>
> Subject: [PATCH 08/56] drm/i915/xelpd: Handle proper AUX interrupt
o think about moving watermark
> logic out of intel_pm.c and into watermark-specific files under the display/
> directory.
>
> Signed-off-by: Matt Roper
Any reason Patch 4 and Patch 5 are not one single patch? It looks like both
replace INTEL_GEN() with DISPLAY_VER() where necessary
> -Original Message-
> From: Chris Wilson
> Sent: Monday, February 1, 2021 3:22 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support
>
> Quoting Srivatsa, Anu
> -Original Message-
> From: Chris Wilson
> Sent: Monday, February 1, 2021 3:05 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg1: Add GuC and HuC support
>
> Quoting Anusha Srivatsa (2021-02-01 2
Add support to load GuC and HuC firmware for Dg1.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 984fa79e0fa7..0e63881674a4
Add support to load GuC and HuC firmware for Dg1.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 67b06fde1225..31e24c3a947e
/drm-firmware DG1-guc-huc-ADLS-dmc
for you to fetch changes up to 348d8a9740930e7b8bd83a36baba40c5cfc3f8be:
i915: Add DMC v2.01 for ADL-S (2021-01-29 11:43:12 -0800)
Anusha Srivatsa (3):
i915: Add GuC v49.0.1 for DG1
s/Add display, gt, ctx and ADL-S/ Add display, gt, ctx WA for ADL-S
Anusha
> -Original Message-
> From: Intel-gfx On Behalf Of
> Aditya Swarup
> Sent: Tuesday, November 17, 2020 10:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
&g
;
> BSpec: 49251
> Cc: Lucas De Marchi
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Matt Roper
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Aditya Swarup
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c
Marchi
> Signed-off-by: Matt Roper
> Signed-off-by: Aditya Swarup
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_combo_phy.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_co
by: Matt Roper
> Signed-off-by: Aditya Swarup
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_
: Lucas De Marchi
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Signed-off-by: Tejas Upadhyay
>
> Signed-off-by: Aditya Swarup
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 8
> 1 file changed, 8 insertions(+
> -Original Message-
> From: Ville Syrjälä
> Sent: Monday, November 2, 2020 9:29 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/ehl: Remove invalid PCI ID
>
> On Fri, Oct 30, 2020 at 02:26:14PM -0700, Anusha Sr
Update the EHL PCI IDs from BSpec.
Remove the invalid ones.
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
Reviewed-by: Ville Syrjälä
---
include/drm/i915_pciids.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 7eeecb07c9a1
> -Original Message-
> From: Ville Syrjälä
> Sent: Monday, November 2, 2020 9:29 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/i915/ehl: Remove invalid PCI ID
>
> On Fri, Oct 30, 2020 at 02:26:14PM -0700, Anusha Sr
Update the EHL PCI IDs from BSpec.
Remove the invalid ones.
Cc: Ville Syrjälä
Signed-off-by: Anusha Srivatsa
---
include/drm/i915_pciids.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 3b5ed1e4f3ec..28428e08a8d3 100644
> -Original Message-
> From: Ville Syrjala
> Sent: Friday, October 30, 2020 9:41 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Srivatsa, Anusha
> Subject: [PATCH v2] drm/i915: Sort EHL/JSL PCI IDs
>
> From: Ville Syrjälä
>
> Sort the EHL/JSL PCI IDs
registers may change location in future platforms, but instead of adding
> new locations, it's simpler to just remove them.
>
> Cc: Matt Roper
> Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 1
> -Original Message-
> From: Josh Boyer
> Sent: Friday, October 23, 2020 4:58 AM
> To: Srivatsa, Anusha
> Cc: linux-firmw...@kernel.org; Kyle McMartin ;
> b...@decadent.org.uk; intel-gfx@lists.freedesktop.org
> Subject: Re: i915 Update : DG1 DMC
>
> Pulle
> -Original Message-
> From: Matt Roper
> Sent: Thursday, October 15, 2020 3:01 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; Srivatsa, Anusha
>
> Subject: [PATCH] drm/i915/rkl: Add new cdclk table
>
> A recent bspec update has provide
at: dg1_dmc_v2_02
git://anongit.freedesktop.org/drm/drm-firmware dg1_dmc_v2_02
for you to fetch changes up to a140ef3eb3746aba2c897db16e02ffb5ffa9e7a2:
i915: Add DG1 DMC v2.02 (2020-10-08 12:13:33 -0700)
Anusha Srivatsa (1
/drm-firmware dg1_dmc_v2_02
for you to fetch changes up to a140ef3eb3746aba2c897db16e02ffb5ffa9e7a2:
i915: Add DG1 DMC v2.02 (2020-10-08 12:13:33 -0700)
Anusha Srivatsa (1):
i915: Add DG1 DMC v2.02
WHENCE
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, September 24, 2020 3:46 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 04/14] drm/i915: Add SKL GT1.5 PCI IDs
>
> On Thu, Sep 24, 2020 at 12:37:47AM
he EHL/JSL PCI IDs numerically. Some order seems better than
> randomness.
>
> Cc: Alexei Podtelezhnikov
> Signed-off-by: Ville Syrjälä
Reviewed-by: Anusha Srivatsa
> ---
> include/drm/i915_pciids.h | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
CI IDs numerically. Some order seems better than randomness.
>
> Cc: Alexei Podtelezhnikov
> Signed-off-by: Ville Syrjälä
Reviewed-by: Anusha Srivatsa
> ---
> include/drm/i915_pciids.h | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
>
CI IDs numerically. Some order seems better than
> randomness.
>
> Cc: Alexei Podtelezhnikov
> Signed-off-by: Ville Syrjälä
Reviewed-by: Anusha Srivatsa
> ---
> include/drm/i915_pciids.h | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
CI IDs numerically. Some order seems better than
> randomness.
>
> Cc: Alexei Podtelezhnikov
> Signed-off-by: Ville Syrjälä
Reviewed-by: Anusha Srivatsa
> ---
> include/drm/i915_pciids.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/in
CI IDs numerically. Some order seems better than
> randomness.
>
> Cc: Alexei Podtelezhnikov
> Signed-off-by: Ville Syrjälä
Reviewed-by: Anusha Srivatsa
> ---
> include/drm/i915_pciids.h | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
CI IDs numerically. Some order seems better than
> randomness.
>
> Cc: Alexei Podtelezhnikov
> Signed-off-by: Ville Syrjälä
Reviewed-by: Anusha Srivatsa
> ---
> include/drm/i915_pciids.h | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --gi
CI IDs numerically. Some order seems better than
> randomness.
There are 2 patches - patch 2 and 3 in the series that are reclassifying some
PCI IDs and there is patch 4 that adds a missing ID. All of those with this
patch can be combined to a single patch OR patch 2, 3 and 4 can be squashe
CI IDs numerically. Some order seems better than
> randomness.
I think the sorting, OCD-ness with hex and reclassifying can be combined in one
patch.
Anusha
> Cc: Alexei Podtelezhnikov
> Signed-off-by: Ville Syrjälä
> ---
> include/drm/i915_pciids.h | 34 +-
gt;
> Most of the HSW PCI IDs are upper case hex numbers, but a few are lower
> case. Make it consistent so these don't stick out like a sore thumb.
>
> Cc: Alexei Podtelezhnikov
> Signed-off-by: Ville Syrjälä
Reviewed-by: Anusha Srivatsa
> ---
> include/drm/i915_pciids
: Ville Syrjälä
>
> Bunch of the SKL SKUs currently documented as GT3/4 seem to actually be
> GT3e/4e. Fix up the comments.
>
> Cc: Alexei Podtelezhnikov
> Signed-off-by: Ville Syrjälä
Reviewed-by: Anusha Srivatsa
> ---
> include/drm/i915_pciids.h | 12 ++--
> 1 f
s v2 of the patches then it
goes right after the commit message as:
V2: Split separate changes into separate patches, sort the IDs (Ville)
> Signed-off-by: Ville Syrjälä
The code changes itself look good.
Reviewed-by: Anusha Srivatsa
> ---
> include/drm/i915_pciids.h | 9 +++
Sort the IDs]
> Signed-off-by: Ville Syrjälä
Reviewed-by: Anusha Srivatsa
> ---
> include/drm/i915_pciids.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> d4c054e3b95f..9df
Reclassify 0x0426 as GT3 (GT2+) according to specifications and the second
> least significant digit.
>
> Signed-off-by: Alexei Podtelezhnikov
> [vsyrjala: s/GT2/GT3/ in the comment]
> Signed-off-by: Ville Syrjälä
Reviewed-by: Anusha Srivatsa
> ---
> include/drm/i915_p
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, September 16, 2020 6:51 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pll:
> Centralize PLL_ENABLE register lookup (
static and return type to the same line( Ville, Jani)
Suggested-by: Matt Roper
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 35 ++-
1 file changed, 18 insertions(+), 17 deletions
static and return type to the same line( Ville, Jxani)
Suggested-by: Matt Roper
Cc: Ville Syrjälä
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 35 ++-
1 file changed, 18 insertions(+), 17 deletions
> -Original Message-
> From: Jani Nikula
> Sent: Thursday, September 10, 2020 6:31 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register
> lookup
>
> On Tue, 08 Sep 2
Syrjälä
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915
> -Original Message-
> From: Vivi, Rodrigo
> Sent: Wednesday, September 2, 2020 2:32 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register
> lookup
>
>
>
&
> -Original Message-
> From: Rodrigo Vivi
> Sent: Tuesday, September 1, 2020 12:30 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register
> lookup
>
> On Tue, Sep 0
-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 25 +++
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c9013f8f766f..7440836c5e44 100644
> -Original Message-
> From: Ville Syrjälä
> Sent: Monday, August 31, 2020 6:42 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/pll: Centralize PLL_ENABLE register
> lookup
>
> On Fri, Aug 2
We currenty check for platform at multiple parts in the driver
to grab the correct PLL. Let us begin to centralize it through a
helper function.
Suggested-by: Matt Roper
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 27 ---
1
With the stepping fix mentioned below,
Reviewed-by: Anusha Srivatsa
> -Original Message-
> From: Souza, Jose
> Sent: Thursday, August 27, 2020 3:57 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Cc: Bai, Guangyao ; Lee, Penne Y
>
> Subject:
915_rev_steppings kbl_revids[] = {
> > [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0
> > }, };
> >
> > +const struct i915_rev_steppings tgl_uy_revids[] = {
> > + [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0
> },
> >
Bump TGL DMC version to 2.07. This new version has power
saving enhancements.
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
The latest firmware contains fix for PSR2 power saving.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c
b/drivers/gpu/drm/i915/display
Bump TGL DMC version to 2.07. this new version has power
saving enhancements.
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c
)
Anusha Srivatsa (2):
i915: Upgrade Tigerlake DMC to v2.07
i915: Add RKL dmc v2.02
WHENCE | 6 ++
i915/rkl_dmc_ver2_02.bin | Bin 0 -> 18204 bytes
i915/tgl_dmc_ver2_07.bin | Bin 0 -> 18732 bytes
3 files changed, 6 inse
/* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
> +};
From the bSpec page, the hbr2 values above are incorrect in more than one place.
Anusha
> +
> struct icl_mg_phy_ddi_buf_trans {
> u32 cri_txdeemph_override_11_6;
>
>
> From: Matt Roper
>
> As with RKL, DG1's PHY C acts as a comp master for PHY D.
>
> Bspec: 49291
> Signed-off-by: Matt Roper
> Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
> ---
> drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
> 1 file ch
e PCI device. Ideally we could
> use HAS_PCH_SPLIT(), but that macro is misused all across the code base to
> rather signify a range of gens. So add a fake one for DG1 to be used where
> needed.
>
> Cc: Aditya Swarup
> Signed-off-by: Lucas De Marchi
Reviewed-by: Anush
From: Matt Roper
Reviewed-by: Anusha Srivatsa
>
> The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the
> bspec details for that bit tell us that it need only be set for PHY-A and PHY-
> B. It also turns out that there isn't even an instance of the PHY_MISC
> register for PHY
fe, it is a power-saving feature were
> supported motherboards can use a special voltage swing table that uses
> less power.
>
> So here parsing the VBT to check if this feature is supported.
>
> BSpec: 20150
> Signed-off-by: José Roberto de Souza
Reviewed-by: Anusha Sri
INTEL_VGA_DEVICE(0x4E61, info), \
> INTEL_VGA_DEVICE(0x4E51, info)
There are more PCIIDs missing from this patch. Like 0x4571,0x4551 etc
Anusha
>
> --
> 2.27.0
>
> ___
> Intel-gfx mailin
The latest firmware contains fix for PSR2 power saving.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c
b/drivers/gpu/drm/i915/display
1 and TC2 outputs
>
> When Rocket Lake is paired with a TGP PCH, the last two outputs utilize the
> TC1 and TC2 hpd pins, even though these are combo outputs.
>
> Bspec: 49181
> Cc: Lucas De Marchi
> Signed-off-by: Matt Roper
Looks good.
Reviewed-by: Anusha Srivatsa
>
> -Original Message-
> From: Roper, Matthew D
> Sent: Wednesday, May 6, 2020 10:20 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC
> for PHY's A and B
>
> On
>
> Introduce the basic platform definition, macros, and PCI IDs.
>
> Bspec: 44501
> Cc: Lucas De Marchi
> Cc: Caz Yokoyama
> Cc: Aditya Swarup
> Signed-off-by: Matt Roper
> Acked-by: Caz Yokoyama
Confirmed the info with the BSpec.
Reviewed-by: Anusha Srivatsa
>
ms only expect PHY_MISC to be programmed for PHY-A
> and
> + * PHY-B and may not even have instances of the register for the
> + * other combo PHY's.
> + */
> + if (IS_ELKHARTLAKE(i915) ||
> + IS_ROCKETLAKE(i915))
> + return phy < PH
uses the same stolen memory registers as TGL and ICL.
>
> Bspec: 52055
> Bspec: 49589
> Bspec: 49636
> Cc: Lucas De Marchi
> Signed-off-by: Matt Roper
Confirmed with Spec.
Reviewed-by: Anusha Srivatsa
> ---
> arch/x86/kernel/early-quirks.c | 1 +
> 1 file changed,
C instead.
>
> Bspec: 49291
> Cc: Lucas De Marchi
> Cc: José Roberto de Souza
> Cc: Aditya Swarup
> Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivatsa
> ---
> .../gpu/drm/i915/display/intel_combo_phy.c| 25 +--
> 1 file changed, 23 insert
aries according to which PCH is
> present on the platform: with TGP the pins are remapped into the TC range,
> whereas with CMP they stay in the traditional combo output range.
>
> Bspec: 49181
> Cc: Aditya Swarup
> Signed-off-by: Matt Roper
Reviewed-by: Anusha Srivat
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, May 1, 2020 10:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; Srivatsa, Anusha
>
> Subject: [PATCH 04/23] drm/i915/rkl: Load DMC firmware for Rocket Lake
>
> Cc: Anusha Sriv
> -Original Message-
> From: Roper, Matthew D
> Sent: Friday, May 1, 2020 10:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; Srivatsa, Anusha
>
> Subject: [PATCH 03/23] drm/i915/rkl: Re-use TGL GuC/HuC firmware
>
> RKL uses the same Gu
la
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 887e0dc701f7..7cc8a7fc53c7 100644
---
: Daniele Ceraolo Spurio
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Reviewed-by: Matt Atwood
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b
: Daniele Ceraolo Spurio
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt
> -Original Message-
> From: Roper, Matthew D
> Sent: Thursday, January 30, 2020 12:43 PM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org; Ceraolo Spurio, Daniele
>
> Subject: Re: [PATCH] drm/i915/tgl: Implement Wa_1606931601
>
> On Wed, Jan 2
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index
Disable Early Read and Src Swap by setting the bit 14
and 15 in the chicken register.
BSpec: 46045,52890
v2: Follow the Bspec implementation for the WA.
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h
> -Original Message-
> From: Roper, Matthew D
> Sent: Thursday, January 23, 2020 9:50 AM
> To: Srivatsa, Anusha
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/tgl: Implement Wa_1606931601
>
> On Wed, Jan 22, 2020 at 03:40:27P
Disable Early Read and Src Swap by setting the bit 14
and 15 in the chicken register.
BSpec: 46045,52890
HSDES: 1606931601
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 6 insertions
)
Anusha Srivatsa (9):
drm/i915/firmware: Add v1.09 of DMC for ICL
drm/i915/firmware: Add v2.04 of DMC for TGL
drm/i915/firmware: Add v33 of GuC for CML
drm/i915/firmware: Add v2.0.0 of HuC for Skylake
drm/i915/firmware: Add v4.0.0
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
(Daniele)
Suggested-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Anusha Srivatsa
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 27
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt
(Daniele)
Suggested-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Anusha Srivatsa
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 27
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
at:
git://anongit.freedesktop.org/drm/drm-firmware cml_tgldmc_huc_updates
for you to fetch changes up to e848f4708bcea2fa829cfbfd7e7a1b3a83b91d3e:
drm/i915/firmware: Add v9.0.0 of HuC for Icelake (2019-09-11 15:46:03 -0700)
Anusha
We have a new version of DMC for ICL - v1.09.
This version adds the Half Refresh Rate capability
into DMC.
Cc: José Roberto de Souza
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915
(Daniele)
Suggested-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 27
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/driver
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
/ehl_huc_9.0.0.bin | Bin 0 -> 498880 bytes
2 files changed, 3 insertions(+)
create mode 100644 i915/ehl_huc_9.0.0.bin
Anusha Srivatsa (2):
drm/i915/uc: Update GuC and HuC firmware naming convention
HAX: force enable_guc=2
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c |
> -Original Message-
> From: Ceraolo Spurio, Daniele
> Sent: Tuesday, September 10, 2019 2:05 PM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH 1/2] drm/i915/uc: Update MAKE_HUC_FW_PATH macro
>
>
>
> On 9/9/19 1
BXT - v2.0.0
KBL - v4.0.0
GLK - v4.0.0
CFL - KBL v4.0.0
ICL - v9.0.0
CML - v4.0.0
v2: Remove the separator parameter altogether from
__MAKE_UC_FW_PATH.(Daniele)
- Squash all firmware update patches (Daniele)
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
ate mode 100644 i915/ehl_huc_9.0.0.bin
anusha@anusha:~/drm-firmware$ tsocks git push origin ehl_huc
Enumerating objects: 12, done.
Counting objects: 100% (12/12), done.
Delta compression using up to 4 threads
Compressing objects: 100% (8/8), done.
Writing objects: 100% (8/8), 153.31 KiB | 76.65 Mi
for Icelake (2019-09-06 12:23:56 -0700)
Anusha Srivatsa (6):
drm/i915/firmware: Add v2.0.0 of HuC for Skylake
drm/i915/firmware: Add v4.0.0 of HuC for Kabylake
drm/i915/firmware: Add v2.0.0 of HuC for Broxton
drm/i915
Add support to load the latest version of HuC on ICL.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt
Update MAKE_HUC_FW_PATH macro to follow the same convention
as the MAKE_GUC_FW_PATH with the separator changing from "_" to "."
and removing "ver".
The current convention being:
_uc_..patch.bin
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
-
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
Add support to load the latest version of HuC on CFL.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt
Add support to load the latest version of HuC on KBL.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt
Add support to load the latest version of HuC on BXT.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt
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