Mandate a minimum Hblank symbol cycle count between BS and BE in 8b/10b
MST and 12b/132b mode.
Spec: DP2.1a
v2: Affine calculation/updation of min HBlank to dp_mst (Jani)
Signed-off-by: Arun R Murthy
---
.../drm/i915/display/intel_display_types.h| 2 ++
drivers/gpu/drm/i915/display
Mandate a minimum Hblank symbol cycle count between BS and BE in 8b/10b
MST and 12b/132b mode.
Spec: DP2.1a
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 6 ++
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display
Add the register/bit definitions for global histogram.
Signed-off-by: Arun R Murthy
---
.../drm/i915/display/intel_histogram_reg.h| 54 +++
1 file changed, 54 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_histogram_reg.h
diff --git a/drivers/gpu/drm
The delay counter for histogram does not reset and as a result the
histogram bin never gets updated. Workaround would be to use save and
restore histogram register.
Wa: 14014889975
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_histogram.c | 17 +
.../gpu
ents on patch 1
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_atomic.c | 5 +
drivers/gpu/drm/i915/display/intel_crtc.c | 169 +-
drivers/gpu/drm/i915/display/intel_crtc.h | 5 +
drivers/gpu/drm/i915/display/intel_display.c | 13 ++
.../drm/i915
In Display 20+, new registers are added for setting index, reading
histogram and writing the IET.
v2: Removed duplicate code (Jani)
v3: Moved histogram core changes to earlier patches (Jani/Suraj)
v4: Rebased after addressing comments on patch 1
Signed-off-by: Arun R Murthy
---
.../gpu/drm
)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 2 +
.../gpu/drm/i915/display/intel_histogram.c| 187 ++
.../gpu/drm/i915/display/intel_histogram.h| 35
4 files changed, 225
Histogram added as part of i915/display driver. Adding the same for xe
as well.
Signed-off-by: Arun R Murthy
Reviewed-by: Suraj Kandpal
---
drivers/gpu/drm/xe/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index
ani)
v3: Replaced drm_i915_private with intel_display (Suraj)
Refactored the histogram read code (Jani)
v4: Rebased after addressing comments on patch 1
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_display_irq.c | 6 +-
.../gpu/drm/i915/display/intel_histogram.c|
am is also pushed for review at
https://patchwork.freedesktop.org/series/135789/
Test-with: 20240705091333.328322-1-mohammed.thasl...@intel.com
Arun R Murthy (7):
drm/i915/histogram: Define registers for histogram
drm/i915/histogram: Add support for histogram
drm/xe: Add histogram support to
DPTC LANEx_CHANNEL_EQ_DONE Sequence" of
DP2.1a spec.
Co-developed-by: Srikanth V NagaVenkata
Signed-off-by: Arun R Murthy
Reviewed-by: Suraj Kandpal
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
Figure 3-52: 128b132b DP DPTC LANEx_CHANNEL_EQ_DONE Sequence of
DP2.1a spec.
After reading LANEx_CHANNEL_EQ_DONE, read the FFE presets.
AUX_RD_INTERVAL and then write the new FFE presets.
Co-developed-by: Srikanth V NagaVenkata
Signed-off-by: Arun R Murthy
Reviewed-by: Suraj Kandpal
d from the sink device, hence use flseep.
Co-developed-by: Srikanth V NagaVenkata
Signed-off-by: Arun R Murthy
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/d
Arun R Murthy (3):
drm/i915/dp: use fsleep instead of usleep_range for LT
drm/i915/dp: read Aux RD interval just before setting the FFE preset
drm/i915/dp: Include the time taken by AUX Tx for timeout
.../drm/i915/display/intel_dp_link_training.c | 22 +--
1 file changed
DPTC LANEx_CHANNEL_EQ_DONE Sequence" of
DP2.1a spec.
Co-developed-by: Srikanth V NagaVenkata
Signed-off-by: Arun R Murthy
Reviewed-by: Suraj Kandpal
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
Figure 3-52: 128b132b DP DPTC LANEx_CHANNEL_EQ_DONE Sequence of
DP2.1a spec.
After reading LANEx_CHANNEL_EQ_DONE, read the FFE presets.
AUX_RD_INTERVAL and then write the new FFE presets.
Co-developed-by: Srikanth V NagaVenkata
Signed-off-by: Arun R Murthy
squash 2
Signed-off-by: Arun R
d from the sink device, hence use flseep.
Co-developed-by: Srikanth V NagaVenkata
Signed-off-by: Arun R Murthy
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/d
Arun R Murthy (3):
drm/i915/dp: use fsleep instead of usleep_range for LT
drm/i915/dp: read Aux RD interval just before setting the FFE preset
drm/i915/dp: Include the time taken by AUX Tx for timeout
.../drm/i915/display/intel_dp_link_training.c | 22 +--
1 file changed
DPTC LANEx_CHANNEL_EQ_DONE Sequence" of
DP2.1a spec.
Co-developed-by: Srikanth V NagaVenkata
Signed-off-by: Arun R Murthy
Reviewed-by: Suraj Kandpal
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
Figure 3-52: 128b132b DP DPTC LANEx_CHANNEL_EQ_DONE Sequence of
DP2.1a spec.
During LT, the transmitter shall read DPCD 02216h before DPCD
00202h through 00207h, and 0200Ch through 0200Fh
Co-developed-by: Srikanth V NagaVenkata
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display
d from the sink device, hence use flseep.
Co-developed-by: Srikanth V NagaVenkata
Signed-off-by: Arun R Murthy
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/d
Arun R Murthy (3):
drm/i915/dp: use fsleep instead of usleep_range for LT
drm/i915/dp: read Aux RD interval just before reading the FFE preset
drm/i915/dp: Include the time taken by AUX Tx for timeout
.../drm/i915/display/intel_dp_link_training.c | 20 +--
1 file changed
togram data.
"Global IET" is a crtc property to write the IET binary LUT data.
v2: Read the histogram blob data before sending uevent (Jani)
v3: use drm_property_replace_blob_from_id (Vandita)
Add substruct for histogram in intel_crtc_state (Jani)
Signed-off-by: Arun R Murthy
---
In Display 20+, new registers are added for setting index, reading
histogram and writing the IET.
v2: Removed duplicate code (Jani)
v3: Moved histogram core changes to earlier patches (Jani/Suraj)
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_histogram.c| 111
enhancement factor can be multiplied/added with
the incoming pixel data frame.
v2: forward declaration in header file along with error handling (Jani)
v3: Replaced i915 with intel_display (Suraj)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915
Histogram added as part of i915/display driver. Adding the same for xe
as well.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index edfd812e0f41..2a5e3ed5ea17 100644
ani)
v3: Replaced drm_i915_private with intel_display (Suraj)
Refactored the histogram read code (Jani)
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_display_irq.c | 6 +-
.../gpu/drm/i915/display/intel_histogram.c| 93 +++
.../gpu/drm/i915/disp
The delay counter for histogram does not reset and as a result the
histogram bin never gets updated. Workaround would be to use save and
restore histogram register.
HSD: 14014889975
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_histogram.c | 17 +
.../gpu
am is also pushed for review at
https://patchwork.freedesktop.org/series/135789/
Test-with: 20240705091333.328322-1-mohammed.thasl...@intel.com
Arun R Murthy (6):
drm/i915/histogram: Add support for histogram
drm/xe: Add histogram support to Xe builds
drm/i915/histogram: histogram interrupt hand
NagaVenkata
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index ca179bed46ad
DP Source should be reading AUX_RD interval after we get adjusted
TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting
in DP Source)
Signed-off-by: Srikanth V NagaVenkata
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_dp_link_training.c| 12 ++--
1 file
Aux RD Interval value depends on the value read from the dpcd register
which is updated from the sink device use flseep thereby we adhere to
the Documentation/timers/timers-howto.rst
Signed-off-by: Srikanth V NagaVenkata
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display
Arun R Murthy (3):
drm/i915/dp: use fsleep instead of usleep_rage for LT
drm/i915/dp: read Aux RD interval after reading the FFE preset
drm/i915/dp: Include the time taken by AUX Tx for timeout
.../drm/i915/display/intel_dp_link_training.c | 20 +--
1 file changed, 10
UHBR20 is not supported by battlemage and the maximum link rate
supported is UHBR13.5
v2: Replace IS_DGFX with IS_BATTLEMAGE (Jani)
HSD: 16023263677
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions
UHBR20 is not supported by battlemage and the maximum link rate
supported is UHBR13.5
HSD: 16023263677
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
In LNL+, histogram/IE data and index registers are added which was
included in the control registers in the legacy platforms. The new
registers are used for reading histogram and writing the IET LUT data.
v2: Removed duplicate code (Jani)
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915
enhancement factor can be multiplied/added with
the incoming pixel data frame.
v2: forward declaration in header file along with error handling (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 2
ani)
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_display_irq.c | 6 +-
.../gpu/drm/i915/display/intel_histogram.c| 80 ++-
.../gpu/drm/i915/display/intel_histogram.h| 3 +
drivers/gpu/drm/i915/i915_reg.h | 5 +-
4 files changed,
The delay counter for histogram does not reset and as a result the
histogram bin never gets updated. Woraround would be to use save and
restore histogram register.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_histogram.c | 17 +
drivers/gpu/drm/i915
togram data.
"Global IET" is a crtc property to write the IET binary LUT data.
v2: Read the histogram blob data before sending uevent (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_atomic.c | 5 +
drivers/gpu/drm/i915/display/intel_crtc.c | 202 +
am is also pushed for review at
https://patchwork.freedesktop.org/series/135789/
Test-with: 20240705091333.328322-1-mohammed.thasl...@intel.com
Arun R Murthy (5):
drm/i915/display: Add support for histogram
drm/i915/display: histogram interrupt handling
Add crtc properties for global histogram
poll_enable() to xe_display(Imre)
v3: removed un-wanted comments (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index
poll_enable() to xe_display(Imre)
v3: removed un-wanted comments (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index
poll_enable() to xe_display(Imre)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index 78cccbe28947..989022d21052 100644
--- a/drivers
poll_enable() to xe_display(Imre)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index 78cccbe28947..989022d21052 100644
--- a/drivers
-by: Arun R Murthy
---
drivers/gpu/drm/xe/xe_pm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
index 9f3c14fd9f33..d952b06ebfb4 100644
--- a/drivers/gpu/drm/xe/xe_pm.c
+++ b/drivers/gpu/drm/xe/xe_pm.c
@@ -22,6 +22,7 @@
#include
might a challenge.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/drm_atomic_uapi.c | 3 +++
include/drm/drm_plane.h | 8
include/uapi/drm/drm_mode.h | 20
3 files changed, 31 insertions(+)
=Option 2
diff
Upon enabling histogram an interrupt is trigerred after the generation
of the statistics. This patch registers the histogram interrupt and
handles the interrupt.
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_display_irq.c | 6 +-
.../gpu/drm/i915/display/intel_histogram.c
In LNL+, histogram/IE data and index registers are added which was
included in the control registers in the legacy platforms. The new
registers are used for reading histogram and writing the IET LUT data.
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_histogram.c| 174
The delay counter for histogram does not reset and as a result the
histogram bin never gets updated. Woraround would be to use save and
restore histogram register.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_histogram.c | 17 +
drivers/gpu/drm/i915
togram data.
"Global IET" is a crtc property to write the IET binary LUT data.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_atomic.c | 5 +
drivers/gpu/drm/i915/display/intel_crtc.c | 202 +-
drivers/gpu/drm/i915/display/intel_crtc.h
enhancement factor can be multiplied/added with
the incoming pixel data frame.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 3 +
.../gpu/drm/i915/display/intel_histogram.c| 187
am is also pushed for review at
https://patchwork.freedesktop.org/series/135789/
Test-with: 20240705091333.328322-1-mohammed.thasl...@intel.com
Arun R Murthy (5):
drm/i915/display: Add support for histogram
drm/i915/display: histogram interrupt handling
Add crtc properties for global histogram
uhbr13.5 is not supported on dg2/mtl. This patch removes the pll state
table for synps and c20 PHY.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 26 --
drivers/gpu/drm/i915/display/intel_dp.c | 2 --
drivers/gpu/drm/i915/display
msg (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 163da48bc406..7098ca65701f 100644
--- a/drivers/gpu/drm/i9
UHBR13.5 is not supported in icl+ as well. This has been removed for mtl
by the commit caf3d748f646 ("drm/i915/dp: Remove support for UHBR13.5")
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Use mul_u32_u32 to avoid potential overflow in multiplying two u32 and
store the u64 result.
v2: remove u64 typecast and use mul_u32_u32 (Ville)
v3: Reframe the commit message
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 +-
1 file changed, 5 insertions
Check return value for drmm_mutex_init as it can fail and return on
failure.
v2: Removed nested if (Lucas)
v3: Revert back to nested if (Andi)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 30 -
1 file changed, 24 insertions(+), 6 deletions
Check return value for drmm_mutex_init as it can fail and return on
failure.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe
Check return value for drmm_mutex_init as it can fail and return on
failure.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe
Check return value for drmm_mutex_init as it can fail and return on
failure.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_display.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers
Multiplying XE_PAGE_SIZE with another u32 and the product stored in
u64 can potentially lead to overflow, use mul_u32_u32 instead.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu
Multiplying XE_PAGE_SIZE with another u32 and the product stored in
u64 can potentially lead to overflow. Change one of the value to u64 so
as to perform 64 bit arithmetic operation as the product is u64.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 +-
1
UHBR13.5 is not supported in MTL and also the DP2.1 spec says UHBR13.5
is optional. Hence removing UHBR135 from the supported link rates.
Fixes: https://gitlab.freedesktop.org/drm/intel/-/issues/8686
v2: Reframed the commit message and added link to the the issue.
Signed-off-by: Arun R Murthy
On link training failure retry link training with a lesser link
rate/lane count as specified in the DP spec.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display
: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 16 ++--
drivers/gpu/drm/i915/display/intel_ddi.c | 21 ++---
.../drm/i915/display/intel_ddi_buf_trans.c| 7 +-
drivers/gpu/drm/i915/display/intel_dp.c | 8 +-
drivers/gpu/drm/i915/display/intel_dp.h | 2
On link training failure fallback sequence a hotpplu event was sent to
the user, but this is not requried as we are not changing the mode and
instead only changing the link rate and lane count. User has no
dependency with these parameters.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915
Fallback mandates on DP link training failure. This patch just covers
the DP2.0 fallback sequence.
TODO: Need to implement the DP1.4 fallback.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 92 ++---
1 file changed, 82 insertions(+), 10 deletions
be included in this patch series.
Arun R Murthy (4):
drm/i915/display/dp: Add DP fallback on LT
drm/i915/display/dp: Dont send hotplug event on LT failure
drm/i915/dp: use link rate and lane count in intel_dp struct
drm/i915/display/dp: On LT failure retry LT
drivers/gpu/drm/i915/display
With a value of '0' read from MSTM_CAP register MST to be enabled.
DP2.1 SCR updates the spec for 128/132b DP capable supporting only one
stream and not supporting single stream sideband MSG.
The underlying protocol will be MST to enable use of MTP.
Signed-off-by: Arun R Murthy
---
d
be confused by a corresponding dpcd write.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 38 +++
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display
With a value of '0' read from MSTM_CAP register MST to be enabled.
DP2.1 SCR updates the spec for 128/132b DP capable supporting only one
stream and not supporting single stream sideband MSG.
The underlying protocol will be MST to enable use of MTP.
Signed-off-by: Arun R Murthy
---
d
be confused by a corresponding dpcd write.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 26 +++
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display
With a value of '0' read from MSTM_CAP register MST to be enabled.
DP2.1 SCR updates the spec for 128/132b DP capable supporting only one
stream and not supporting single stream sideband MSG.
The underlying protocol will be MST to enable use of MTP.
Signed-off-by: Arun R Murthy
---
d
By default warn_on are enabled, hence removing this module parameter.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/i915_params.c | 4
drivers/gpu/drm/i915/i915_params.h | 1 -
3 files changed, 1 insertion
By default fastboot is enabled on all Display 9+ platforms and disabled
on older platforms. Its not necessary to retain this as a module
parameter.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ---
drivers/gpu/drm/i915/i915_params.c | 5
The debug print for enabling SDP CRC16 is applicable only for DP2.0, but
this debug print was not within the uhbr check and was always printed.
Fis this by adding proper checks and returning.
Signed-off-by: Arun R Murthy
Reviewed-by: Chaitanya Kumar Borah
---
.../gpu/drm/i915/display
The debug print for enabling SDP CRC16 is applicable only for DP2.0, but
this debug print was not within the uhbr check and was always printed.
Fis this by adding proper checks and returning.
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_dp_link_training.c| 12
.
v2: updated the commit message
v4: check for SEND_BUSY after write (Imre)
v5: reverted the send_ctl to the while loop (Jani)
v6: Fixed the BAT failure
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 36 ++---
1 file changed, 24 insertions(+), 12
.
v2: updated the commit message
v4: check for SEND_BUSY after write (Imre)
v5: reverted the send_ctl to the while loop (Jani)
v6: Fixed the BAT failure
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 36 ++---
1 file changed, 24 insertions(+), 12
For DP2.0 as per the Spec on LT failure we need to reduce the lane count
if the lane count is not equal to 1. If lane count is 1 then need to
retry with reducing the link rate.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++--
1 file changed, 18
.
v2: updated the commit message
v4: check for SEND_BUSY after write (Imre)
v5: reverted the send_ctl to the while loop (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 55 ++---
1 file changed, 25 insertions(+), 30 deletions(-)
diff --git a
.
v2: updated the commit message
v4: check for SEND_BUSY after write (Imre)
v5: reverted the send_ctl to the while loop (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 56 ++---
1 file changed, 26 insertions(+), 30 deletions(-)
diff --git a
As per the DP2.1 Spec support for UHBR13.5 is optional. Hence removing
the support for UHBR13.5
UHBR10 can be used for 6k panels.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
.
v2: updated the commit message
v4: check for SEND_BUSY after write (Imre)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 58 +
1 file changed, 26 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b
On AUX transfer timeout, as per DP spec need to retry for 3 times and
has to be restarted freshly.
v3: handle timeout and dont rely on register value on timeout (Imre)
Signed-off-by: Arun R Murthy
---
.../drm/i915/display/intel_display_types.h| 1 -
drivers/gpu/drm/i915/display
.
v2: updated the commit message
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 50 +
1 file changed, 22 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index
As part of restart on AUX xfer timeout, check for busy status and then
start sending the data.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 50 +
1 file changed, 22 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
For modifier not supporting async flip, print the modifier and display
version. Helps in reading the error message.
v2: Reframe the error message (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions
For modifier not supporting async flip, print the modifier and display
version. Helps in reading the error message.
v2: Reframe the error message (Jani)
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions
For modifier not supporting async flip, print the modifier and display
version. Helps in reading the error message.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915
This patch enables support for selective fetch in global histogram.
User can provide the selective fetch co-ordinates and only that region
will be used in generating the histogram.
Signed-off-by: Arun R Murthy
---
.../gpu/drm/i915/display/intel_global_hist.c | 65 +++
.../gpu
inary histogram data.
"Global IET" is a crtc property to write the IET binary LUT data.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_atomic.c | 5 +
drivers/gpu/drm/i915/display/intel_crtc.c | 200 +-
drivers/gpu/drm/i915/display/intel_c
User can provide the selective fetch co-ordinates for global histogram
using crtc blob property. This patch adds the crtc blob property.
The selective fetch can be done only on the y co-ordinate and cannot be
done on the x co-ordinate.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915
For global histogram the panel should be edp and should have pwm based
backlight controller. Flags are updated accordingly.
Reviewed-by: Uma Shankar
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 12
1 file changed, 12 insertions(+)
diff
table consisiting of pixel data.
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 3 +
.../gpu/drm/i915/display/intel_global_hist.c | 295 ++
.../gpu/drm/i915/display/intel_global_hist.h
With the enablement of global histogram, upon generation of histogram,
an interrupt is triggered. This patch handles the irq.
Reviewed-by: Uma Shankar
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/i915_irq.c | 6 +-
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
2 files changed, 8
For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.
v2: added separate function to avoid code duplication(Jani N)
v3: DP2.1 section 3.5.2.16 is ordered, 3.5.1.2 is unordered and hence
discarding
Signed-off-by: Arun R Murthy
---
.../drm/i915
For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.
v2: added separate function to avoid code duplication(Jani N)
Signed-off-by: Arun R Murthy
---
.../drm/i915/display/intel_dp_link_training.c | 62 +--
1 file changed, 44 insertions
For 128b/132b LT prior to LT DPTX should set power state, DP channel
coding and then link rate.
v2: added separate function to avoid code duplication(Jani N)
Signed-off-by: Arun R Murthy
---
.../drm/i915/display/intel_dp_link_training.c | 62 +--
1 file changed, 44 insertions
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