.kernel.org/patch/9482393/
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 1 +
drivers/gpu/drm/arm/hdlcd_crtc.c| 1 +
drivers/gpu/drm/arm/malidp_planes.c | 2 +-
drivers/gpu/drm/armada/armada_crtc.c| 1 +
drivers/gpu/dr
.
Use this at your discretion, the contents of the error state. although
compressed, are allocated with GFP_ATOMIC (i.e. limited) and kept for all
eternity (until the error state is destroyed).
v2: rebased from Chris's tree on top of drm-tip (Mika)
Based on an earlier patch by Ben Widawsky
S
On 17-01-12 20:32:07, Ville Syrjälä wrote:
On Thu, Jan 12, 2017 at 10:00:55AM -0800, Ben Widawsky wrote:
On 17-01-12 12:51:20, Ville Syrjälä wrote:
>On Wed, Jan 11, 2017 at 04:51:17PM -0800, Ben Widawsky wrote:
>> This was based on a patch originally by Kristian. It has been modified
On 17-01-12 12:51:20, Ville Syrjälä wrote:
On Wed, Jan 11, 2017 at 04:51:17PM -0800, Ben Widawsky wrote:
This was based on a patch originally by Kristian. It has been modified
pretty heavily to use the new callbacks from the previous patch.
Cc: Kristian H. Kristensen
Signed-off-by: Ben
This is expected because it's based on Ville's patch series to define the new
modifiers.
On 17-01-12 01:01:31, Patchwork wrote:
== Series Details ==
Series: GET_PLANE2 w/ i915 implementation
URL : https://patchwork.freedesktop.org/series/17873/
State : failure
== Summary ==
LD [M] sound/p
://lists.freedesktop.org/archives/dri-devel/2016-December/127942.html
Ben Widawsky (3):
drm: Add new DRM_IOCTL_MODE_GETPLANE2
drm/i915: Add format modifiers for Intel
drm/i915: Add support for GET_PLANE2 CCS modifiers
drivers/gpu/drm/arc/arcpgu_crtc.c | 1 +
drivers/gpu/drm/arm
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c | 10 --
drivers/gpu/drm/i915/intel_sprite.c | 2 ++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
e the modifiers
array a sentinel based structure instead of a sized one. Upon discussion
on IRC, it was determined that having an invalid modifier might make
sense in general as well.
References: https://patchwork.kernel.org/patch/9482393/
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/ar
This was based on a patch originally by Kristian. It has been modified
pretty heavily to use the new callbacks from the previous patch.
Cc: Kristian H. Kristensen
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c | 109 ++-
drivers/gpu/drm
On 17-01-11 17:05:04, Ville Syrjälä wrote:
On Thu, Jan 05, 2017 at 02:45:37PM +0100, Christian König wrote:
Am 05.01.2017 um 12:37 schrieb Ville Syrjälä:
> On Wed, Jan 04, 2017 at 07:38:55PM +0100, Rainer Hochecker wrote:
>> From: Rainer Hochecker
>>
>> This adds fourcc codes for 16bit planes r
came from where.
Entire series available here:
git://github.com/vsyrjala/linux.git fb_format_dedup_4_ccs
Cc: Vandana Kannan
Cc: Daniel Vetter
Cc: Ben Widawsky
Cc: Jason Ekstrand
Cc: Laurent Pinchart
In addition to review comments I've left, this series (patch 8 and 9 in
particula
ch case we immediately be
able to tell if any of that stuff changed by just comparing the
pointers. But that does sound a bit wasteful space wise.
v2: Drop the 'dev' argument from the hook
v3: Include the description of the CCS surface layout
Cc: Vandana Kannan
Cc: Daniel Vetter
Cc: Ben
ot supported in combination with
decompression either.
This patch may contain work from at least the following people:
* Vandana Kannan
* Daniel Vetter
* Ben Widawsky
Cc: Vandana Kannan
Cc: Daniel Vetter
Cc: Ben Widawsky
Cc: Jason Ekstrand
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/
x27; to the new hook (Laurent)
Cc: Laurent Pinchart
Cc: Ben Widawsky
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_fb_cma_helper.c | 2 +-
drivers/gpu/drm/drm_fourcc.c | 25 +
drivers/gpu/drm/drm_framebuffer.c| 9 +++--
drivers/gpu/drm/drm_m
On 17-01-03 11:27:52, Rodrigo Vivi wrote:
No functional changes. Apparently spec has been changed
the valid table showing 0x192A as Server GT4
while 0x193A is Server GT4e.
Libdrm and Mesa already have this right. So let's fix the ref here.
Cc: Ben Widawsky
Signed-off-by: Rodrigo
GPU hang
involving this batch.
Use this at your discretion, the contents of the error state. although
compressed, are allocated with GFP_ATOMIC (i.e. limited) and kept for all
eternity (until the error state is destroyed).
Based on an earlier patch by Ben Widawsky
Signed-off-by: Chris Wilson
Cc
Acked-by: Ben Widawsky
On 16-12-06 16:06:50, Tomeu Vizoso wrote:
Add a few subtests that check that lossless compressed render targets
are properly displayed. Also test a few error conditions.
Cc: Ville Syrjälä
Cc: Ben Widawsky
Signed-off-by: Tomeu Vizoso
---
Hi,
this has been tested
On 16-12-29 17:34:19, Ben Widawsky wrote:
On 16-12-06 13:34:02, Paulo Zanoni wrote:
2016-12-01 20:09 GMT-02:00 Ben Widawsky :
From: Ben Widawsky
This patch series ultimately adds support within the i965 driver for
Renderbuffer Decompression with GBM. In short, this feature reduces memory
On 16-12-06 13:34:02, Paulo Zanoni wrote:
2016-12-01 20:09 GMT-02:00 Ben Widawsky :
From: Ben Widawsky
This patch series ultimately adds support within the i965 driver for
Renderbuffer Decompression with GBM. In short, this feature reduces memory
bandwidth by allowing the GPU to work with
appens with the non-CCS Y vs. Yf as well. If
desired, we could potentially return a unique pointer for each
pixel_format+tiling+ccs combination, in which case we immediately be
able to tell if any of that stuff changed by just comparing the
pointers. But that does sound a bit wasteful space wise.
Cc
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
intel/intel_chipset.h | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 514f659..41fc0da 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
On 16-09-15 17:30:10, Mika Kuoppala wrote:
Imre Deak writes:
From: Ben Widawsky
v2: (Imre)
- Access only subslices that are known to exist.
- Reset explictly the MCR selector to slice/sub-slice ID 0 after the
readout.
- Use the subslice INSTDONE bits for the hangcheck/subunits-stuck
add a WARN_ON() if we find
> > > > ourselves with a device without any rings.
> > > >
> > > > Fixes: 73ae478cdf6a ("drm/i915: Replace has_bsd/blt/vebox with a mask")
> > > > Fixes: 88d2ba2e95c8 ("drm/i915: Unify engine init loop")
&g
; | ABS { $$ = 1; }
> > ;
> >
> > -execsize: /* empty */ %prec EMPTEXECSIZE
> > +execsize: %empty /* empty */ %prec EMPTEXECSIZE
> > {
> > $$ = ffs(program_defaults.execute_size) - 1;
> > }
> > @@ -2902,7 +2
On Thu, Apr 14, 2016 at 11:27:25AM +0300, Jani Nikula wrote:
> On Wed, 13 Apr 2016, Ben Widawsky wrote:
> > +module_param_named_unsafe(disable_firmware_loading,
> > i915.disable_firmware_loading, uint, 0400);
> > +MODULE_PARM_DESC(disable_firmware_loading,
> > +
On Thu, Apr 14, 2016 at 07:48:13AM -0700, Ben Widawsky wrote:
> On Thu, Apr 14, 2016 at 11:14:48AM +0300, Jani Nikula wrote:
> > On Thu, 14 Apr 2016, Jani Nikula wrote:
> > > On Wed, 13 Apr 2016, Ben Widawsky wrote:
> > >> The two behavioral changes here are the
On Thu, Apr 14, 2016 at 11:14:48AM +0300, Jani Nikula wrote:
> On Thu, 14 Apr 2016, Jani Nikula wrote:
> > On Wed, 13 Apr 2016, Ben Widawsky wrote:
> >> The two behavioral changes here are the correct detection of the eDRAM
> >> size on
> >> gen9 (SKL + KBL
On Wed, Apr 13, 2016 at 06:45:32PM +0100, Dave Gordon wrote:
> On 13/04/16 17:57, Ben Widawsky wrote:
> > For debug and development purposes only.
> >
> > Cc: Mika Kuoppala
> > Signed-off-by: Ben Widawsky
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c
For debug and development purposes only.
Cc: Mika Kuoppala
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 +
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +++
drivers/gpu/drm/i915/i915_params.c | 6 ++
drivers/gpu/drm/i915/i915_params.h
The two behavioral changes here are the correct detection of the eDRAM size on
gen9 (SKL + KBL), and unconditional printing of the eLLC size.
Cc: Eero Tamminen
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_uncore.c | 16 +---
1 file changed, 13 insertions(+), 3
his with this big
> blanket back then already, as E0 vs F0 discrepancy was suspicious
> enough.
>
> Previously the WaForceEnableNonCoherent has been tied to
> context non-coherence, atleast in relevant hsds. So keep this tie
> and extended this alongside.
>
> Cc: Abdiel
Signed-off-by: Ben Widawsky
---
man/intel_gpu_top.man | 3 +++
tools/intel_gpu_top.c | 25 +
2 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/man/intel_gpu_top.man b/man/intel_gpu_top.man
index d90a7ee..be0f1be 100644
--- a/man/intel_gpu_top.man
+++ b/man
down by default on HSW, and prints a warning. An
upcoming patch will provide an override for the insane.
References:
https://lists.freedesktop.org/archives/mesa-dev/2013-July/041692.html
Signed-off-by: Ben Widawsky
---
man/intel_gpu_top.man | 2 ++
tools/intel_gpu_top.c | 28
Signed-off-by: Ben Widawsky
---
src/i915_pciids.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/i915_pciids.h b/src/i915_pciids.h
index f970209..4d1c11d 100644
--- a/src/i915_pciids.h
+++ b/src/i915_pciids.h
@@ -279,7 +279,8 @@
#define INTEL_SKL_GT3_IDS(info
On Wed, Feb 10, 2016 at 04:23:08PM +, Chris Wilson wrote:
> On Wed, Feb 10, 2016 at 07:42:23AM -0800, Ben Widawsky wrote:
> > Do you guys get the CI mails? This version has regressions. v1 did not. I
> > don't
> > know what to trust.
>
> I didn't even
Do you guys get the CI mails? This version has regressions. v1 did not. I don't
know what to trust.
On Tue, Feb 09, 2016 at 11:44:12AM -0800, Ben Widawsky wrote:
> This behavior of checking for a shmem backed GEM object was introduced here:
> commit 4c914c0c7c787b8f730128a8cdcca
: I manually retyped this from a test machine. So I haven't even compiled
this exact patch.
v2: Use same logic as from a2a4f916c2f (Kristian, Dave Gordon)
Cc: Chris Wilson
Cc: Kristian Høgsberg
Cc: Dave Gordon
Signed-off-by: Ben Widawsky
Tested-by: Jordan Justen (v1)
Reviewed-by: J
On Tue, Feb 09, 2016 at 11:30:34AM +, Dave Gordon wrote:
> On 09/02/16 00:20, Kristian Høgsberg wrote:
> >On Fri, Feb 5, 2016 at 5:48 PM, Ben Widawsky
> > wrote:
> >>This behavior of checking for a shmem backed GEM object was introduced here:
> >>commit 4c914c0
.
NOTE: I manually retyped this from a test machine. So I haven't even compiled
this exact patch.
Cc: Chris Wilson
Cc: Kristian Høgsberg
Cc: Jordan Justen
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/
15/intel_ringbuffer.h
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 566b0ae..62b4e1b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -122,6 +122,8 @@ struct intel_ringbuffer {
>* we can detect new retirements.
>*/
> u32 last_retired_head;
> +
> + int wa_tail_dwords;
> };
>
> struct intel_context;
> --
> 2.4.3
>
--
Ben Widawsky, Intel Open Source Technology Center
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This is safe because right above this, we
already did a modulus operation.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 +++---
drivers/gpu/drm/i915/intel_lrc.c| 15 +--
drivers/gpu/drm/i915/intel_lrc.h| 18 --
3 files changed, 28 ins
This is a useful thing to have around as a function because the mechanism may
change in the future.
There is a net increase in LOC here, and it will continue to be the case on GEN8
and GEN9 - but future GENs may have an alternate mechanism for doing this.
Signed-off-by: Ben Widawsky
3 Status: 0x00010018
Context 4 Status: 0x0001
Context 5 Status: 0x009d0018
hangcheck: hung [40]
bsd command stream:
START: 0x00039000
HEAD: 0x0018
...
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 7 ++-
drivers/gpu
Since we extracted it for use in error state, we may as well use it in debugfs
too.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915
There is no point in emitting a WARN since the backtrace will always be the
same. Errors have actually become easier to spot given the large number of WARNs
which exist today in modesetting paths.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 4 +++-
1 file changed, 3
to land as much as possible - but
I'll live without it.
Ben Widawsky (5):
drm/i915: Cleanup some of the CSB handling
drm/i915: change WARN to ERROR in CSB count
drm/i915: Extract CSB status read
drm/i915: Add basic execlist info to error state
drm/i915: Use CSB helper in debugfs
drive
On Mon, Jan 04, 2016 at 09:12:11PM +0100, Pavel Machek wrote:
> Hi!
>
> > > I then ran a git bissect between v4.0 and v4.1 from Linus's tree and
> > > found the "guilty" commit was
> > >
> > > commit 317b4e903636305cfe702ab3e5b3d68547a69e7
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ca5c0e8..973487a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm
On Fri, Dec 18, 2015 at 10:17:49AM +0200, Mika Kuoppala wrote:
> Ben Widawsky writes:
>
> > Compile tested only.
> >
> > Signed-off-by: Ben Widawsky
> > ---
> > drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deleti
Compile tested only.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 42a7be1..a9bc207 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
On Thu, Dec 17, 2015 at 10:49:24PM +0200, Imre Deak wrote:
> On Thu, 2015-12-17 at 09:49 -0800, Ben Widawsky wrote:
> > It is unclear if this is even required on BXT.
>
> I'm not sure either, I only added it on the premise that it was marked
> as SKL+ originally in BSpec.
It is unclear if this is even required on BXT.
v2: Make sure to set the default value to false. Uncertain how my compiler
doesn't complain with v1.
Cc: Imre Deak
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 16
1 file changed, 8 insertions(
It is unclear if this is even required on BXT.
Cc: Imre Deak
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 519cea32
On Wed, Dec 16, 2015 at 12:18:20AM +, Chris Wilson wrote:
> On Tue, Dec 15, 2015 at 04:13:49PM -0800, Ben Widawsky wrote:
> > This has been incorrect since the original commit from Oscar Mateo here:
> > commit 4da46e1e5bb7e7396fad172cdaffbe496562f3d8
> > Author: Oscar M
ars up the confusion.
NOTE: This patch was compile tested only.
NOTE2: The modern docs call it MI_STORE_DATA_INDEX not MI_STORE_DWORD_INDEX
Cc: Oscar Mateo
Cc: Damien Lespiau
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_lrc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
di
re too.
> u8 subslice_7eu = INTEL_INFO(dev)->sseu.subslice_7eu[s];
>
> stat->eu_total -= hweight8(subslice_7eu);
6 & 7 are:
Reviewed-by: Ben Widawsky
1-7 are also:
Tested-by: Ben Widawsky
--
Ben Widawsky, Intel Open Source Technology Cent
84,8 +784,7 @@ struct intel_csr {
>
> struct sseu_dev_info {
> u8 slice_mask;
> - u8 subslice_total;
> - u8 subslice_per_slice;
> + u8 subslice_mask;
I know we have situations for GT1 parts where the number of subslices per slice
is less than that of the same GEN of a different SKU. AFAIK, this never carries
over into higher GT (ie. GT2 would always have 3 subslices per slice, but GT1
may have 2 subslices per slice). However. I am not certain this is the case - I
hope you've double checked that.
> u8 eu_total;
> u8 eu_per_subslice;
> /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
> @@ -795,6 +794,11 @@ struct sseu_dev_info {
> u8 has_eu_pg:1;
> };
>
> +static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
> *sseu)
> +{
> + return hweight32((sseu)->slice_mask) * hweight32((sseu)->subslice_mask);
hweight8
basically s/hweight32/hweight8 on the whole file
> +}
> +
> struct intel_device_info {
> u32 display_mmio_offset;
> u16 device_id;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 4130ff1..158f008 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2209,7 +2209,7 @@ make_rpcs(struct drm_device *dev)
>
> if (INTEL_INFO(dev)->sseu.has_subslice_pg) {
> rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
> - rpcs |= INTEL_INFO(dev)->sseu.subslice_per_slice <<
> + rpcs |= hweight32(INTEL_INFO(dev)->sseu.subslice_mask) <<
> GEN8_RPCS_SS_CNT_SHIFT;
> rpcs |= GEN8_RPCS_ENABLE;
> }
Reviewed-by: Ben Widawsky
--
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44
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -783,7 +783,7 @@ struct intel_csr {
> #define SEP_SEMICOLON ;
>
> struct sseu_dev_info {
> - u8 slice_total;
> + u8 slice_mask;
> u8 subslice_total;
> u8 subslice_per_slice;
> u8 eu_total;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 8a55f8a..4130ff1 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2202,7 +2202,7 @@ make_rpcs(struct drm_device *dev)
> */
> if (INTEL_INFO(dev)->sseu.has_slice_pg) {
> rpcs |= GEN8_RPCS_S_CNT_ENABLE;
> - rpcs |= INTEL_INFO(dev)->sseu.slice_total <<
> + rpcs |= hweight32(INTEL_INFO(dev)->sseu.slice_mask) <<
^ hweight8?
> GEN8_RPCS_S_CNT_SHIFT;
> rpcs |= GEN8_RPCS_ENABLE;
> }
I'm not positive if hweight32 is actually okay on an 8bit type. I remember Ville
correcting me once on this, but I can't remember it's correct. Assuming
hweight32 is fine to use, with or without my recommendations, this is:
Reviewed-by: Ben Widawsky
--
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On Wed, Oct 21, 2015 at 06:40:33PM +0300, Imre Deak wrote:
> Signed-off-by: Imre Deak
Reviewed-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 55
> +++--
> 1 file changed, 29 insertions(+), 26 deletions(-)
>
> diff --git a
On Wed, Oct 21, 2015 at 06:40:32PM +0300, Imre Deak wrote:
> Move all slice/subslice/eu related properties to the sseu_dev_info
> struct.
>
> No functional change.
>
> Signed-off-by: Imre Deak
Reviewed-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915
attributes {
u8 slice_count;
u8 eu_total; /* This is sort of useless since if eu_total isn't
trivially
* eu_per_subslice * subslice_count * slice_count, then we
* need to know exactly which subslice is missing EUs. */
str
gt; >
> > tools/null_state/gen9: Send atleast one valid component in VF state
> >
> > to honor the Reviewed-by, send all four components as noted by
> > Ben in his review.
> >
> > Cc: Ben Widawsky
> > Cc: Arun Siluvery
> > Signed
This prevents the simulator from barfing when it sees commands from another
ring. I've been using this locally for a very long time.
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
tools/aubdump.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/aubdump.c b/
On Tue, Oct 06, 2015 at 08:51:13PM +, Rodrigo Vivi wrote:
> cc'ing Ben to get his opinion...
>
Of course anything is possible wrt the delta of KBL features vs SKL. With the
knowledge we have, we can make a pretty educated guess that there will be no
changes, and with an equally high level of
On Fri, Oct 02, 2015 at 01:58:13PM +0300, Imre Deak wrote:
> On Thu, 2015-10-01 at 16:00 -0700, Ben Widawsky wrote:
> > On Wed, Sep 30, 2015 at 11:00:46PM +0300, Imre Deak wrote:
> > > From: Ben Widawsky
> > >
> > > Signed-off-by: Ben Widawsky
> > >
On Wed, Sep 30, 2015 at 11:00:46PM +0300, Imre Deak wrote:
> From: Ben Widawsky
>
> Signed-off-by: Ben Widawsky
>
> ---
> Changes (Imre):
> - use the new INSTDONE capturing by default on new GENs (On Ben's request)
> - keep printing the render ring INSTDONE to
On Wed, Sep 30, 2015 at 11:00:46PM +0300, Imre Deak wrote:
> From: Ben Widawsky
>
> Signed-off-by: Ben Widawsky
>
> ---
> Changes (Imre):
> - use the new INSTDONE capturing by default on new GENs (On Ben's request)
> - keep printing the render ring INSTDONE to
0x02070 /* 965+ only */
> -#define INSTDONE10x0207c /* 965+ only */
> +#define GEN4_INSTDONE1 0x0207c /* 965+ only, aka INSTDONE_2 on SNB */
> #define ACTHD_I965 0x02074
> #define HWS_PGA 0x02080
> #define HWS_ADDRESS_MASK 0xf000
1-3 a
On Tue, Aug 18, 2015 at 05:25:55PM +0300, Joonas Lahtinen wrote:
> Hi,
>
> On pe, 2015-08-14 at 10:58 +0200, Daniel Vetter wrote:
> > On Thu, Aug 13, 2015 at 03:49:35PM -0700, Ben Widawsky wrote:
> > > On Thu, Aug 13, 2015 at 10:33:00AM +0300, Joonas La
t; to honor the Reviewed-by, send all four components as noted by
> Ben in his review.
>
> Cc: Ben Widawsky
> Cc: Arun Siluvery
> Signed-off-by: Mika Kuoppala
Thanks. (STILL in favor of just dropping it :P )
Reviewed-by: Ben Widawsky
--
Ben Wid
On Thu, Aug 13, 2015 at 10:33:00AM +0300, Joonas Lahtinen wrote:
> Hi,
>
> On ke, 2015-08-12 at 18:35 -0700, Ben Widawsky wrote:
> > On Wed, Aug 12, 2015 at 03:10:18PM +0300, Joonas Lahtinen wrote:
> > > On ke, 2015-08-12 at 12:26 +0100, Arun Siluvery wrote:
> >
understand why this actually causes a hang on the IGT test? I
certainly don't. The docs are pretty clear that the constant command is not
committed until the BTP command, but I can't make any sense of how it related to
a GPU hang.
[snip]
---
Ben Widawsky, Intel Open Source Te
ill need to
> apply this WA because userspace may set it. If userspace really need it
> to be set then they need to do in every batch.
>
> Cc: Ben Widawsky
> Cc: Mika Kuoppala
> Signed-off-by: Arun Siluvery
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> driver
On Wed, Aug 05, 2015 at 11:13:46AM +0300, Mika Kuoppala wrote:
> Ben Widawsky writes:
>
> > On Fri, Jul 31, 2015 at 04:27:07PM +0100, Arun Siluvery wrote:
> >> A programming restriction exists for this instruction, atleast one
> >> component
> >> of o
On Fri, Jul 31, 2015 at 04:28:45PM +0100, Arun Siluvery wrote:
> Atleast one component of one valid vertex element must be enabled.
>
> Cc: Ben Widawsky
> Cc: Chris Wilson
> Signed-off-by: Arun Siluvery
> ---
> drivers/gpu/drm/i915/intel_renderstate_gen9.c | 2 +-
On Fri, Jul 31, 2015 at 04:27:07PM +0100, Arun Siluvery wrote:
> A programming restriction exists for this instruction, atleast one component
> of one valid vertex element must be enabled.
>
> Cc: Ben Widawsky
> Cc: Chris Wilson
> Signed-off-by: Arun Siluvery
> ---
&g
ader bit can be specified by
> two different registers, use a better option (Ben).
>
> Cc: Ben Widawsky
> Cc: Joonas Lahtinen
> Signed-off-by: Arun Siluvery
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +
> drivers/gpu/drm/i915/intel_lrc.c| 8
>
On Mon, Aug 03, 2015 at 08:24:57PM +0100, Arun Siluvery wrote:
> This WA is implemented in init_context as well as WA batch init.
> There are also some dependent bits need to be set in other registers
> for this to be complete.
>
> Cc: Ben Widawsky
> Cc: Joonas Lahtinen
>
On Mon, Aug 03, 2015 at 08:24:56PM +0100, Arun Siluvery wrote:
> Cc: Ben Widawsky
> Cc: Joonas Lahtinen
> Signed-off-by: Arun Siluvery
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 6 ++
> 2 files changed, 9 insertions(+)
>
&g
On Thu, Jun 25, 2015 at 07:11:21PM +0100, Chris Wilson wrote:
> On Thu, Jun 25, 2015 at 11:01:44AM -0700, Ben Widawsky wrote:
> > On Wed, Jun 24, 2015 at 08:28:13AM +0100, Chris Wilson wrote:
> > > On Tue, Jun 23, 2015 at 04:44:52PM -0700, Anuj Phogat wrote:
> > > > O
On Wed, Jun 24, 2015 at 08:28:13AM +0100, Chris Wilson wrote:
> On Tue, Jun 23, 2015 at 04:44:52PM -0700, Anuj Phogat wrote:
> > On Mon, Jun 22, 2015 at 1:04 PM, Chris Wilson
> > wrote:
> > > On Mon, Jun 22, 2015 at 09:51:08PM +0200, Daniel Vetter wrote:
> > >> On Mon, Jun 22, 2015 at 11:47:02AM
Hi. Feel free to Cc me on patches of this nature. I am far behind on mesa-dev,
and no longer read intel-gfx. I'm probably one of the sensible people to look at
this...
On Tue, Jun 23, 2015 at 01:21:27PM +0100, Michel Thierry wrote:
> Gen8+ supports 48-bit virtual addresses, but some objects must a
0;
> > bufmgr_gem->exec_bos[index] = bo;
> > bufmgr_gem->exec2_objects[index].flags = 0;
I was about to argue this should be part of patch 1, but nope, it should be a
separate patch :-)
I started digging into whether we have a reasonable way to determine if a
On Fri, Jun 19, 2015 at 03:50:44PM -0700, Anuj Phogat wrote:
> +Ben.
>
> On Fri, Apr 10, 2015 at 5:20 PM, Anuj Phogat wrote:
> > and use it to initialize the align variable in drm_intel_bo.
> >
> > In case of YF/YS tiled buffers libdrm need not know about the tiling
> > format because these buffe
entifying the right culprit).
>
> Signed-off-by: Chris Wilson
> Cc: Daniel Vetter
> Cc: Ben Widawsky
> ---
> intel/intel_bufmgr_gem.c | 27 ---
> 1 file changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/intel/intel_bufmgr_gem.c b/in
On Wed, 03 Jun 2015 09:49:43 +0300
Jani Nikula wrote:
> On Wed, 03 Jun 2015, Ben Widawsky wrote:
> > in
> > commit 65ca7514e21adbee25b8175fc909759c735d00ff
> > Author: Damien Lespiau
> > Date: Mon Feb 9 19:33:22 2015 +
> >
> > drm/i915/skl: I
x27;t know if this fixes anything
since I have many other problems with my platform.
Cc: Damien Lespiau
Cc: Nick Hoath
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm
On Thu, Mar 26, 2015 at 12:44:19PM -0700,
intel-gfx-requ...@lists.freedesktop.org wrote:
> Send Intel-gfx mailing list submissions to
> intel-gfx@lists.freedesktop.org
>
> To subscribe or unsubscribe via the World Wide Web, visit
> http://lists.freedesktop.org/mailman/listinfo/intel-g
rapid turnover in working sets. The
> issue is that even a 2 second window is enough for an application to
> fill all of memory with inactive buffers (and we would rely on the
> oom-killer identifying the right culprit).
>
> Signed-off-by: Chris Wilson
> Cc: Daniel Vetter
we switch to default context and when we resume we can
> > force a restore if default is really there and object is bound.
> >
> > Cc: Ben Widawsky
> > Cc: U. Artie Eoff
> > Signed-off-by: Rodrigo Vivi
>
> Bleh, you don't need to overload enable as the c
t we were
last using at freeze. The force is required because the LRCA might be [*should
be*] be the same across suspend resume."
> Cc: Ben Widawsky
> Cc: U. Artie Eoff
> Signed-off-by: Rodrigo Vivi
Debugged-by?: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_gem_contex
commit 06fda602dbca ("drm/i915: Create page table allocators")
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89350
> Tested-by: Valtteri Rantala
> Cc: Michel Thierry
> Cc: Ben Widawsky
> Cc: Ville Syrjälä
> Signed-off-by: Mika Kuoppala
&
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6fa22db..49bc296 100644
--- a/drivers/gpu
t's hard to tell how useful this is/would be.
Cc: Paulo Zanoni
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 11 +--
drivers/gpu/drm/i915/intel_uncore.c | 11 ++-
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i91
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_debugfs.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index b315f01..e0fd3ba 100644
--- a/drivers/gpu/drm/i915
do not know). I also didn't check that I rebased
things properly.
Do what you want with them...
Ben Widawsky (6):
drm/i915: Remove the useless flush_chipset
drm/i915: Pass eb_vmas to execbuffer implementations
drm/i915: Opportunistically reduce flushing at execbuf
drm/i915: Add
separate.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h| 13 +++--
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 26 ++
drivers/gpu/drm/i915/intel_lrc.c | 8 +---
drivers/gpu/drm/i915/intel_lrc.h | 3 ++-
4 files
. Unless I missed something in the
code, it should only effect non-LLC i915 platforms.
I haven't yet run any numbers for other benchmarks, nor have I attempted to
check if various conformance tests still pass.
v2: Rewrite the patch to be i915 only
Obtain whether or not we wbinvd up front.
Sig
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem.c | 53 +++--
1 file changed, 30 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5bfb332..4d5a69d 100644
--- a/drivers/gpu/drm
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/i915_gem.c | 32
drivers/gpu/drm/i915/i915_gem_gtt.c | 13 ++---
3 files changed, 42 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915
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