Add the support macros to define/extract bits as 16bits.
v2: checkpatch fixes
Reviewed-by: Gustavo Sousa
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_reg_defs.h | 48
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
Use computed C20 HDMI TMDS pixel clocks to support 25.175MHz to 594000MHz
modes. Add 16 Bit mask operators to support C20 phy programming.
v2: checkpatch fixes
BSPEC: 64568
Cc: Imre Deak
Cc: Mika Kahola
Cc: Radhakrishna Sripada
Cc: Gustavo Sousa
Signed-off-by: Clint Taylor
Clint Taylor (2
Use algorithm to generate HDMI C20 PLL clock frequencies.
i
v2: checkpatch fixes
BSPEC: 64568
Cc: Radhakrishna Sripada
Cc: Mika Kahola
Cc: Anusha Srivatsa
Reviewed-by: Gustavo Sousa
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 89
Use algorithm to generate HDMI C20 PLL clock frequencies.
BSPEC: 64568
Cc: Radhakrishna Sripada
Cc: Mika Kahola
Cc: Anusha Srivatsa
Cc: Gustavo Sousa
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 89 +--
.../gpu/drm/i915/display
Use computed C20 HDMI TMDS pixel clocks to support 25.175MHz to
594000MHz modes. Add 16 Bit mask operators to support C20 phy
programming.
BSPEC: 64568
Cc: Imre Deak
Cc: Mika Kahola
Cc: Radhakrishna Sripada
Cc: Gustavo Sousa
Signed-off-by: Clint Taylor
Clint Taylor (2):
drm/i915: Add
Add the support macros to define/extract bits as 16bits.
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/i915_reg_defs.h | 49
1 file changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
b/drivers/gpu/drm/i915/i915_reg_defs.h
index
);
+ intel_ddi_init(dev_priv, PORT_TC3);
+ intel_ddi_init(dev_priv, PORT_TC4);
Reviewed-by: Clint Taylor
-Clint
} else if (IS_DG2(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
BSPEC has updated the cdclk audio keepalives AUD_TS_CDCLK_M value to 60
for all supported platforms and refclks.
BSPEC: 54034
BSPEC: 55409
BSPEC: 65243
Cc: Kai Vehmanen
Cc: Uma Shankar
Cc: Ville Syrjälä
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_audio.c | 6 +-
1
From: "Taylor, Clinton A"
Use BSPEC values for the Audio Keep alive M and N values as included in
the cdclk BSPEC pages for display > 13
BSPEC: 54034, 55409
Cc: Kai Vehmanen
Cc: Uma Shankar
Cc: Ville Syrjälä
Signed-off-by: Taylor, Clinton A
---
drivers/gpu/drm/i915/display/intel_audio.c |
DDC pin mapping for DGFX cards uses direct VBT pin mapping
Cc: Lucas De Marchi
Cc: Matt Roper
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_bios.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers
Matches BSPEC for DKL Phy.
Reviewed-by: Clint Taylor
-Clint
On 1/13/22 9:48 AM, José Roberto de Souza wrote:
TC voltage swing programming sequence was updated with a new step.
BSpec: 54956
Cc: sta...@vger.kernel.org
Cc: Jani Nikula
Cc: Clint Taylor
Cc: Imre Deak
Signed-off-by: José
matches BSPEC.
Reviewed-by: Clint Taylor
-Clint
On 1/13/22 8:04 AM, José Roberto de Souza wrote:
EHL table was recently updated with some minor fixes.
BSpec: 21257
Cc: Clint Taylor
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 10
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
From: Matt Atwood
Extend existing workaround 1409120013 to DG2.
Cc: José Roberto de Souza
Signed-off-by: Matt Atwood
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
From: Ramalingam C
Invalidate IC cache through pipe control command as part of the ctx
restore flow through indirect ctx pointer.
v2:
- Move pipe control from xcs indirect context to the rcs indirect
context
Correct,
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
Coarse power gating for render should not be enabled on some DG2
steppings.
Bspec: 52698
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 15 +++
1 file changed, 11
Looks correct.
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
This workaround is documented a bit strangely in the bspec; it's listed
as an A0 workaround, but the description clarifies that the workaround
is implicitly handled by the hardware and what the driver
Reviewed-by: Clint Taylor
-Clint
On 11/2/21 3:25 PM, Matt Roper wrote:
From: Stuart Summers
Add the initial set of workarounds for Xe_HP SDV.
There are some additional workarounds specific to the compute engines
that we're holding back for now. Those will be added later, after
general
Reviewed-by: Clint Taylor
-Clint
On 11/2/21 3:25 PM, Matt Roper wrote:
The bspec's performance guide suggests programming specific values into
a few registers for optimal performance. Although these aren't
workarounds, it's easiest to handle them inside the GT workaround
functions (which
Appears to match latest BSPEC
Reviewed-by: Clint Taylor
-Clint
On 9/3/21 5:35 PM, Matt Roper wrote:
From: Lucas De Marchi
Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a
dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to
memory for L3 des
psr2(dev_priv, crtc_state->cpu_transcoder)) {
drm_dbg_kms(_priv->drm,
"PSR2 not supported in transcoder %s\n",
Reviewed-by: Clint Taylor
-Clint
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Intel-gf
_A ||
- dig_port->base.port != PORT_A)
+ if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
return;
/*
Reviewed-by: Clint Taylor
-Clint
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ls = max_t(u8, 1, dev_priv->dram_info.num_channels);
int deinterleave;
int ipqdepth, ipqdepthpch;
int dclk_max;
Reviewed-by: Clint Taylor
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ld(struct intel_digital_port
*dig_port);
void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy);
+bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port);
+
#endif /* __INTEL_TC_H__ */
Reviewed-by: Clint Taylor
-Clint
_
, wakeref);
+ mutex_unlock(_port->tc_lock);
drm_WARN_ON(>drm, val == 0x);
Reviewed-by: Clint Taylor
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Values match current BSPEC.
Reviewed-by: Clint Taylor
-Clint
On 5/14/21 8:10 PM, Matt Roper wrote:
From: Mika Kahola
Define and use DP voltage swing and pre-emphasis translation tables
for ADL-P.
v2:
- Update according to recent bspec updates; there are now separate
tables for RBR
Reviewed-by: Clint Taylor
-Clint
On 5/14/21 8:10 PM, Matt Roper wrote:
From: Anusha Srivatsa
The clocks in ALD_P is similar to that of TGL.
The combo PLLs use the same DPLL0, DPLL1 and TBT_PLL.
This patch adds the helper function intel_mg_pll_enable_reg()
which is similar
Reviewed-by: Clint Taylor
-Clint
On 5/14/21 8:10 PM, Matt Roper wrote:
From: Anusha Srivatsa
When scalers are enabled, we need to program underrun
bubble counter to 0x50 to avoid Soft Pipe A underruns.
Make sure other bits dont get overwritten.
Cc: Matt Roper
Cc: Clint Taylor
Cc: José
drm_dbg_kms(_priv->drm,
+ "plane %d pitch (%d) must be power of two for
tiled buffers\n",
+ i, mode_cmd->pitches[i]);
+ goto err;
+ }
+
Reviewed-by: Clint Taylo
t it would be consistent.
Feel free to change the name or leave it. The code appears to match the
current BSPEC table.
Reviewed-by: Clint Taylor
-Clint
+ /* NT mV Trans mV db*/
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 },/* 350 35
image quality */
wa_masked_en(wal,
Reviewed-by: Clint Taylor
-Clint
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Reviewed-by: Clint Taylor
-Clint
On 2/8/19 12:05, Ville Syrjala wrote:
From: Ville Syrjälä
Currently we're only dumping out the ddb allocation changes, let's do
the same for the watermarks. This should help with debugging underruns
and whatnot.
First I tried one line per plane per wm
Oops, failure caused by ICL_PORT_TX_DW7 not being defined yet. Still
waiting on r-b for a patch that includes the DW7 definition.
-Clint
On 12/14/18 10:15, Patchwork wrote:
== Series Details ==
Series: drm/i915/dsi: Add PORT_TX_DW7 programming to DSI vswing sequence
URL :
On 12/03/2018 04:19 AM, Ville Syrjälä wrote:
On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
BSpec: 21257
Cc: Ville
On 11/30/2018 03:15 PM, Imre Deak wrote:
On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
BSpec: 21257
Cc: Ville Syrjälä
since our MST HW readout is incomplete.
+*/
+ if (WARN_ON(is_mst))
+ return;
+ }
if (clk_enabled == !!encoder->base.crtc)
return;
Fixes the mDP lock up issue.
Reviewed-by: Clint
Gen9:all */
+ if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
return true;
return false;
Looks good.
Reviewed-by: Clint Taylor
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On 10/15/2018 04:31 AM, Jani Nikula wrote:
On Mon, 15 Oct 2018, Jani Nikula wrote:
On Fri, 05 Oct 2018, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N
value mode instead of HDMI specification values.
Signed-off
On 10/15/2018 06:41 AM, Ville Syrjälä wrote:
On Fri, Oct 12, 2018 at 01:14:45PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Initialize SCDC Source Version and TDMS_Config_0 registers to nominal
values during intel_hdmi_detect(). The i915 driver currently doesn't
implement
On 10/08/2018 03:33 AM, Ville Syrjälä wrote:
On Fri, Oct 05, 2018 at 03:18:44PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests
HF1-12 and HF1-13 to fail. Added "Source Shall" entries from SC
On 06/29/2018 02:09 AM, Imre Deak wrote:
On Thu, Jun 28, 2018 at 11:14:30AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.
When measured on a scope
On 06/25/2018 03:33 AM, Imre Deak wrote:
On Wed, Jun 13, 2018 at 02:48:49PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.
When measured on a scope
On 06/08/2018 06:31 AM, Imre Deak wrote:
Hi Clint,
nice debugging!
On Thu, Jun 07, 2018 at 04:12:39PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal
tel.com (2018-04-12 00:13:26)
From: Clint Taylor <clinton.a.tay...@intel.com>
In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP
if available."), the patch was always selecting the alternate refresh rate
even though user space was asking for the higher rate
L_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
+ INTEL_VGA_DEVICE(0x591C, info), /* Mobile GT2 */ \
KBL-R Y 2+2 should actually be labeled as ULX GT2 instead of Mobile GT2.
Of course this information is conveniently missing from the spec.
With that change:
Reviewed-by: Clint Taylor &l
irmware
loaded. Customer was concerned about the fix being in DRM instead of
i915. However, there are no other SOCs that use this DRM function.
Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com>
Tested-by: Clint Taylor <clinton.a.tay...@intel.com>
-Clint
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On 03/13/2018 06:11 AM, Ville Syrjälä wrote:
On Tue, Mar 13, 2018 at 10:28:55AM +0100, Maarten Lankhorst wrote:
On fi-cnl-y3 we have 2 modes that differ only by crtc_clock. This means
that if we request the normal mode, we automatically get the downclocked
mode.
This can be seen during boot:
On 04/11/2018 04:11 PM, Chris Wilson wrote:
Quoting clinton.a.tay...@intel.com (2018-04-12 00:13:26)
From: Clint Taylor <clinton.a.tay...@intel.com>
In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP
if available."), the patch was always selecting the a
On 03/02/2018 10:10 AM, Rodrigo Vivi wrote:
On Thu, Mar 01, 2018 at 11:36:12AM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor <clinton.a.tay...@intel.com>
DisplayPort Phy compliance test patterns register definitions.
Hi Clint,
what's the current plan to add the actu
On 08/16/2017 02:19 PM, Rodrigo Vivi wrote:
It seems this quirk is randomly masking the real issue.
It could be masking the real issue. The most likely cause of this issue
is a slow power fall off to the panel when the PPS requests power-off.
We would need physical access to the platform
This patch fixes the alignment. I spotted another issue with teh
structure and will fix it once this one is merged.
Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com>
Tested-by: Clint Taylor <clinton.a.tay...@intel.com>
On 08/16/2017 07:20 AM, ville.syrj...@linux.intel.com
On 08/14/2017 07:40 AM, Daniel Vetter wrote:
On Thu, Aug 10, 2017 at 10:50:19AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor <clinton.a.tay...@intel.com>
Current 50ms max threshold timing for an EDID read is very close to the
actual time for a 2 block HDMI EDID read.
stedt, Marta <marta.lofst...@intel.com>
Subject: [PATCH v4 i-g-t] tests/kms: increase max threshold time for edid
read
From: Clint Taylor <clinton.a.tay...@intel.com>
Current 50ms max threshold timing for an EDID read is very close to the
actual time for a 2 block HDMI EDID read. Adjust the t
com>; Lofstedt, Marta <marta.lofst...@intel.com>
Subject: [PATCH v3 i-g-t] tests/kms: increase max threshold time for
edid read
From: Clint Taylor <clinton.a.tay...@intel.com>
Current 50ms max threshold timing for an EDID read is very close to
the actual time for a 2 block HDMI EDID re
Of clinton.a.tay...@intel.com
Sent: Friday, August 4, 2017 9:23 PM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH i-g-t] tests/kms: increase max threshold time for
edid read
From: Clint Taylor <clinton.a.tay...@intel.com>
Current 50ms max threshold timing for an EDID read is very
On 07/12/2017 04:47 PM, Rodrigo Vivi wrote:
Version 1.05 is now available for CNL.
According to its release notes the only difference is:
- Change from aux A pwrreq always turn on during restore,
to saving and restoring aux A pwrreq.
Reviewed-by: Clinton Taylor
On 07/11/2017 07:10 AM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12
On 07/09/2017 11:53 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12
On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville
On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12
On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
v4: Review comments by Ville addressed
Removed the
On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch updates scaler max limit support for NV12
v2: Rebased (me)
Needs rebase again.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch adds NV12 to format_is_yuv() function and
made it available for both primary and sprite planes
small nit on the commit message:
static function in intel_sprite.c is not available
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
-Clint
On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch sets appropriate scaler mode for NV12 format.
In this mode,
for
this information.
Cc: Clint Taylor <clinton.a.tay...@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
---
drivers/gpu/drm/i915/intel_bios.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_
Reviewed-by: Clinton Taylor <clinton.a.tay...@intel.com>
-Clint
On 07/06/2017 02:01 PM, Rodrigo Vivi wrote:
Cannonlake has same color setup as Geminilake.
Legacy color load luts doesn't work anymore on Cannonlake+.
Cc: Clint Taylor <clinton.a.tay...@intel.com>
Cc: Ander Conselvan
Reviewed-by: Clinton Taylor
-Clint
On 06/29/2017 02:34 PM, Rodrigo Vivi wrote:
By the Spec all CNL Y skus are 2+2, i.e. GT2.
This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")
v2: Add kernel commit id for
Reviewed-by: Clinton Taylor
-Clint
On 06/29/2017 02:34 PM, Rodrigo Vivi wrote:
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.
This is a copy
Matches i915 support PCI device IDs
Reviewed-by: Clinton Taylor
-Clint
On 06/29/2017 02:18 PM, Rodrigo Vivi wrote:
By the Spec all CNL Y skus are 2+2, i.e. GT2.
This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for
Reviewed-by: Clinton Taylor
-Clint
On 06/29/2017 02:18 PM, Rodrigo Vivi wrote:
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.
This is also
Identical to other platforms.
Reviewed-by: Clinton Taylor
On 06/29/2017 10:18 AM, Rodrigo Vivi wrote:
Coffeelake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.
It is Gen9 graphics based platform on top of CNP PCH.
On following patches we
Looks Good.
Reviewed-by: Clinton Taylor
-Clint
On 06/28/2017 05:14 PM, Manasi Navare wrote:
This patch fixes the DP AUX CH timeouts observed during CI IGT
tests thus fixing the CI failures. This is done by adding a
quirk for a particular PCI device that requires
On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
Add the PCI IDs for U SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
intel/intel_chipset.h | 12 +++-
1 file changed, 11
On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
Add the PCI IDs for H SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
intel/intel_chipset.h | 8 +++-
1 file changed, 7
On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
Add the PCI IDs for S SKU IN CFL by following the spec.
v2: Update IDs.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
intel/intel_chipset.h | 17 -
1 file changed, 16
On 06/22/2017 09:28 AM, Anusha Srivatsa wrote:
From: anushasr
Follow the spec and add ID for U SKU
v2: Update IDs in accordance to the kernel commit:
d29fe702c9cb682df99146d24d06e5455f043101 (Chris)
Cc: Rodrigo Vivi
Signed-off-by: Anusha
On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
Add the PCI IDs for U SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
intel/intel_chipset.h | 12 +++-
1 file changed, 11
On 06/21/2017 09:34 AM, Anusha Srivatsa wrote:
From: anushasr
Follow the spec and add ID for U SKU
v2: Update IDs.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
lib/i915_pciids.h | 9 -
1 file
EVICE(0x3E96, info) /* SRV GT2 */
+
Matches current documentation
Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com>
+#define INTEL_CFL_IDS(info) \
+ INTEL_CFL_S_IDS(info)
+
#endif /* _I915_PCIIDS_H */
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 199fa2d..
EVICE(0x3E96, info) /* SRV GT2 */
+
+#define INTEL_CFL_H_IDS(info) \
+ INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
+
Device ID's Matches current documentation
Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com>
#d
Matches pseudo code in BSpec.
Reviewed-by: Clint Taylor <clinton.a.tay...@intel.com>
On 06/08/2017 04:03 PM, Rodrigo Vivi wrote:
From: "Kahola, Mika" <mika.kah...@intel.com>
Enable wrpll computation for Cannonlake platform to support
pll's required for HDMI outp
On 06/08/2017 04:45 AM, Szwichtenberg, Radoslaw wrote:
On Wed, 2017-06-07 at 10:45 -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor <clinton.a.tay...@intel.com>
RGB565 Pixel format planes can now be rotated at 90 and 270 degrees
Signed-off-by: Clint Taylor <clin
On 06/07/2017 10:55 AM, Ville Syrjälä wrote:
On Wed, Jun 07, 2017 at 10:45:25AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor <clinton.a.tay...@intel.com>
RGB565 Pixel format planes can now be rotated at 90 and 270 degrees
"now" == since when?
GLK, I will u
On 04/06/2017 12:15 PM, Rodrigo Vivi wrote:
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.
This is also the new Spec style what makes the review much
more easy and
On 05/31/2017 03:16 AM, Jani Nikula wrote:
Print DID not VID on the DID error path. Looks like a copy-paste error
from the VID error path. Clarify and clean up error logging, making them
distinguishable from each other, while at it.
Reviewed-by: Clinton Taylor
Reviewed-by: Clinton Taylor
-Clint
On 05/30/2017 03:42 PM, Rodrigo Vivi wrote:
As for BXT, PP_DIVISOR was removed from CNP PCH and power
cycle delay has been moved to PP_CONTROL.
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
On 05/26/2017 12:18 AM, Daniel Vetter wrote:
On Thu, May 25, 2017 at 05:06:25PM +0200, Hans Verkuil wrote:
From: Hans Verkuil
This adds support for the DisplayPort CEC-Tunneling-over-AUX
feature that is part of the DisplayPort 1.3 standard.
Unfortunately, not all
On 05/30/2017 02:29 PM, Hans Verkuil wrote:
On 05/30/2017 10:32 PM, Clint Taylor wrote:
On 05/30/2017 09:54 AM, Hans Verkuil wrote:
On 05/30/2017 06:49 PM, Hans Verkuil wrote:
On 05/30/2017 04:19 PM, Clint Taylor wrote:
On 05/30/2017 12:11 AM, Jani Nikula wrote:
On Tue, 30 May 2017
On 05/30/2017 09:54 AM, Hans Verkuil wrote:
On 05/30/2017 06:49 PM, Hans Verkuil wrote:
On 05/30/2017 04:19 PM, Clint Taylor wrote:
On 05/30/2017 12:11 AM, Jani Nikula wrote:
On Tue, 30 May 2017, Hans Verkuil <hverk...@xs4all.nl> wrote:
On 05/29/2017 09:00 PM, Daniel Vetter
On 05/30/2017 09:49 AM, Hans Verkuil wrote:
On 05/30/2017 04:19 PM, Clint Taylor wrote:
On 05/30/2017 12:11 AM, Jani Nikula wrote:
On Tue, 30 May 2017, Hans Verkuil <hverk...@xs4all.nl> wrote:
On 05/29/2017 09:00 PM, Daniel Vetter wrote:
On Fri, May 26, 2017 at 12:20:48PM +0200
On 05/29/2017 04:06 AM, Jani Nikula wrote:
On Thu, 18 May 2017, Clint Taylor <clinton.a.tay...@intel.com> wrote:
On 05/18/2017 04:10 AM, Jani Nikula wrote:
Face the fact, there are Display Port sink and branch devices out there
in the wild that don't follow the Display Port specific
On 05/30/2017 12:11 AM, Jani Nikula wrote:
On Tue, 30 May 2017, Hans Verkuil wrote:
On 05/29/2017 09:00 PM, Daniel Vetter wrote:
On Fri, May 26, 2017 at 12:20:48PM +0200, Hans Verkuil wrote:
On 05/26/2017 09:15 AM, Daniel Vetter wrote:
Did you look into also wiring
ille Syrjälä <ville.syrj...@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
Cc: Clint Taylor <clinton.a.tay...@intel.com>
Cc: Adam Jackson <a...@redhat.com>
Cc: Harry Wentland <harry.wentl...@amd.com>
Signed-off-by: Jani Nikula <jani.nik...@int
devices ended up in regressions for other
devices. So here we are.
v2: Rebase on DRM DP desc read helpers
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
Cc: Clint Taylor <clinton.a.tay...@intel.com>
Cc: Adam Jackson &l
On 05/11/2017 03:03 AM, Jani Nikula wrote:
On Wed, 10 May 2017, clinton.a.tay...@intel.com wrote:
From: Clint Taylor <clinton.a.tay...@intel.com>
The Analogix 7737 DP to HDMI converter requires reduced N and M values when
to operate correctly at HBR2. Detect this IC by its OUI
On 05/11/2017 02:57 AM, Jani Nikula wrote:
From: Clint Taylor <clinton.a.tay...@intel.com>
The Analogix 7737 DP to HDMI converter requires reduced M and N values
when to operate correctly at HBR2. Detect this IC by its OUI value of
0x0022B9 via the DPCD quirk list.
v2 by Jani: R
properly. Naturally, the workaround of reducing
main link attributes for all devices ended up in regressions for other
devices. So here we are.
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
Cc: Clint Taylor <clinton.a.tay..
a: https://bugs.freedesktop.org/show_bug.cgi?id=93578
Tested-by: Mads <m...@ab3.no>
Tested-by: PJ <foo...@pjmodos.net>
Tested-by: François Guerraz <kubr...@fgv6.net>
Tested-by: Lev Popov <l...@nabam.net>
Tested-by: Igor Krivenko <igor.s.krive...@gmail.com>
Cc: Clint Taylor &
On 03/24/2017 04:25 AM, Jani Nikula wrote:
On Thu, 23 Mar 2017, Clint Taylor <clinton.a.tay...@intel.com> wrote:
I would prefer a solution for B (rules for M/N), but the code doesn't
appear to be broken and I don't believe we should "Fix" something that
is working. The d
On 03/23/2017 10:23 AM, Jani Nikula wrote:
On Thu, 23 Mar 2017, Clint Taylor <clinton.a.tay...@intel.com> wrote:
On 03/23/2017 05:30 AM, Jani Nikula wrote:
On Thu, 23 Mar 2017, clinton.a.tay...@intel.com wrote:
From: Clint Taylor <clinton.a.tay...@intel.com>
Several major vendor
On 03/23/2017 05:30 AM, Jani Nikula wrote:
On Thu, 23 Mar 2017, clinton.a.tay...@intel.com wrote:
From: Clint Taylor <clinton.a.tay...@intel.com>
Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane
signal if the Data Link N is greater than 0x8.
Patch detec
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