Re: [Intel-gfx] [RFC PATCH] drm/i915/guc: New interface files for GuC starting in Gen11

in the right direction? Signed-off-by: Oscar Mateo Cc: Joonas Lahtinen Cc: Kevin Rogovin Cc: John A Spotswood Cc: Anusha Srivatsa Cc: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: Michel Thierry Cc: Chris Wilson Cc: Michał Winiarski Cc: Tomasz Lis Cc: Jon Ewins Cc: Sujaritha Sundaresan

[Intel-gfx] [PATCH] drm/i915/guc: Don't read SOFT_SCRATCH(15) on MMIO error

mechanism for sending events to host. While here, upgrade error message to DRM_ERROR. Signed-off-by: Michal Wajdeczko Cc: Michel Thierry Cc: Joonas Lahtinen Cc: Chris Wilson --- drivers/gpu/drm/i915/intel_guc.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu

[Intel-gfx] [PATCH v5] drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c

Some functions already use i915 name instead of dev_priv. Let's rename this param in all remaining functions, except those that still use legacy macros. v2: don't forget about function descriptions (Sagar) v3: rebased v4: rebased v5: rebased, pulled out from the series Signed-off-by: Michal

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Keep guc submission permanently engaged

sts sneak back in temporarily on unwedging leading to an unbalanced park/unpark. Testcase: igt/gem_eio Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michał Winiarski <michal.winiar...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> --- drivers/gpu/drm/

Re: [Intel-gfx] [PATCH v12 16/17] drm/i915/guc/slpc: Add SLPC banner to RPS debugfs interfaces

ase. v8: Rebase. Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.sz

Re: [Intel-gfx] [PATCH v12 14/17] drm/i915/guc/slpc: Add debugfs support to read/write/revert the parameters

faces to i915_debugfs.c. Added error handling to the range of parameters and parsing. Making use of intel_guc_slpc_enabled instead of accessing status variable. Optimized token parsing. (Michal Wajdeczko) s/i915_slpc_paramlist/i915_guc_slpc_params and s/i915_slpc_param_ctl/i915_guc_slpc_param_ctl

Re: [Intel-gfx] [PATCH v12 12/17] drm/i915/guc/slpc: Add enable/disable controls for SLPC tasks

m> Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com&

Re: [Intel-gfx] [PATCH v12 10/17] drm/i915/guc/slpc: Add parameter set/unset/get, task control/status functions

e same in intel_guc_slpc_send_mmio. (Michal Wajdeczko) v10: Rebase. Added kernel documentation to the task control functions. Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joona

Re: [Intel-gfx] [PATCH v12 08/17] drm/i915/guc/slpc: Send SHUTDOWN event to stop SLPC tasks

-off-by: Tom O'Rourke <Tom.O'rou...@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.c

Re: [Intel-gfx] [PATCH v12 07/17] drm/i915/guc/slpc: Send RESET event to restart/enable SLPC tasks

emoved intel_slpc_get_status and waiting for maximum of 5ms for SLPC state to turn RUNNING instead of hiding the latency across uc_init_hw and init_gt_powersave. s/if..else/switch..case in intel_guc_slpc_get_state_str. Removed SLPC sanitization from init_gt_powersave. (Michal Wajdeczko

Re: [Intel-gfx] [PATCH] drm/i915/guc: Don't store runtime GuC log level in modparam

Signed-off-by: Piotr Piórkowski <piotr.piorkow...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Michał Winiarski <michal.winiar...@intel.com> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> ---

Re: [Intel-gfx] [PATCH v12 06/17] drm/i915/guc/slpc: Allocate/initialize/release SLPC shared data

m...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sujaritha Sundaresan <sujaritha.sun

Re: [Intel-gfx] [PATCH v12 03/17] drm/i915/guc/slpc: Lay out SLPC init/enable/disable/fini helpers

ges due to creation of intel_guc.h. Updates in intel_guc_cleanup w.r.t slpc cleanup. v11: s/intel_slpc/intel_guc_slpc. Adjusted place for slpc struct inside guc struct. (Michal Wajdeczko) Updated comment about intel_slpc_enable as we plan to not defer the SLPC status check on enabling

Re: [Intel-gfx] [PATCH v3 3/4] drm/i915: Add code to accept valid locked WOPCM register values

On Mon, 16 Apr 2018 20:43:39 +0200, Yaodong Li <yaodong...@intel.com> wrote: On 04/13/2018 09:20 PM, Michal Wajdeczko wrote: On Tue, 10 Apr 2018 02:42:19 +0200, Jackie Li <yaodong...@intel.com> wrote: In current code, we only compare the locked WOPCM register values with th

Re: [Intel-gfx] [PATCH v3 2/4] drm/i915: Always set HUC_LOADING_AGENT_GUC bit in WOPCM offset register

On Mon, 16 Apr 2018 19:43:52 +0200, Yaodong Li <yaodong...@intel.com> wrote: On 04/13/2018 07:26 PM, Michal Wajdeczko wrote: On Tue, 10 Apr 2018 02:42:18 +0200, Jackie Li <yaodong...@intel.com> wrote: The enable_guc modparam is used to enable/disable GuC/HuC FW uploading

Re: [Intel-gfx] [PATCH v4 1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

dparam. This will guarantee that the WOPCM layout will be always be calculated correctly without making any assumptions to the GuC and HuC firmware sizes. v3: - Rebase v4: - Renamed the new parameter add to intel_uc_fw_fetch (Michal) Signed-off-by: Jackie Li <yaodong...@intel.com> Cc: Mich

Re: [Intel-gfx] [PATCH v3 1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

On Mon, 16 Apr 2018 19:28:04 +0200, Yaodong Li <yaodong...@intel.com> wrote: On 04/13/2018 07:15 PM, Michal Wajdeczko wrote: On Tue, 10 Apr 2018 02:42:17 +0200, Jackie Li <yaodong...@intel.com> wrote: After enabled the WOPCM write-once registers locking status checkin

Re: [Intel-gfx] [PATCH] drm/i915: Call i915_perf_fini() on init_hw error unwind

priv) ret = intel_gvt_init(dev_priv); if (ret) - goto out_ggtt; + goto err_ggtt; return 0; -out_ggtt: +err_ggtt: i915_ggtt_cleanup_hw(dev_priv); - +err_perf: + i915_perf_fini(dev_priv);

Re: [Intel-gfx] [PATCH v3 3/4] drm/i915: Add code to accept valid locked WOPCM register values

g even if the locked register values are different from the calculated ones. v2: - Update WOPCM register only if it's not locked Signed-off-by: Jackie Li <yaodong...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal

Re: [Intel-gfx] [PATCH v3 2/4] drm/i915: Always set HUC_LOADING_AGENT_GUC bit in WOPCM offset register

locked with HUC_LOADING_AGENT_GUC bit set to 1 which will guarantee successful uploading of both GuC and HuC FW. We will further take care of the locked values in the following enhancement patch. Signed-off-by: Jackie Li <yaodong...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc:

Re: [Intel-gfx] [PATCH v3 1/4] drm/i915: Always do WOPCM partitioning based on real firmware sizes

he other end as proposed in [1] [1] https://patchwork.freedesktop.org/patch/212471/ v3: - Rebase Signed-off-by: Jackie Li <yaodong...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Winiarski <michal.winiar

Re: [Intel-gfx] [PATCH] drm/i915/guc: Replace %phn with %phN

hmm, I can't see these warnings, how to get them? Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> with s/%phN/%ph Reviewed-by: Michal Wajdeczko <michal.w

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v8,01/12] drm/i915: Park before resetting the submission backend

On Mon, 09 Apr 2018 17:09:18 +0200, Patchwork wrote: == Series Details == Series: series starting with [v8,01/12] drm/i915: Park before resetting the submission backend URL : https://patchwork.freedesktop.org/series/41365/ State : failure == Summary

Re: [Intel-gfx] [PATCH v8 08/12] drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw

On Mon, 09 Apr 2018 14:47:24 +0200, Chris Wilson <ch...@chris-wilson.co.uk> wrote: Quoting Michal Wajdeczko (2018-04-09 13:23:28) As we always call intel_uc_sanitize after every call to intel_uc_fini_hw we may drop redundant call and sanitize uC from the fini_hw function. Sign

Re: [Intel-gfx] [PATCH] drm/i915/guc: Check that the breadcrumb irq is enabled

ed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Michał Winiarski <michal.winiar...@intel.com> --- drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc_

[Intel-gfx] [PATCH v8 05/12] drm/i915: Add i915_gem_fini_hw to i915_gem_suspend

By calling i915_gem_init_hw in i915_gem_resume and not calling i915_gem_fini_hw in i915_gem_suspend we introduced asymmetry in init_hw/fini_hw calls. Let's fix that. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chri

[Intel-gfx] [PATCH v8 11/12] drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c

Some functions already use i915 name instead of dev_priv. Let's rename this param in all remaining functions, except those that still use legacy macros. v2: don't forget about function descriptions (Sagar) v3: rebased Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Re

[Intel-gfx] [PATCH v8 12/12] HAX: Enable GuC for CI

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index c963603..53037b5 100644 --- a/drivers/gpu/dr

[Intel-gfx] [PATCH v8 10/12] drm/i915/uc: Use helper functions to detect fw load status

We don't have to check load status values. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/

[Intel-gfx] [PATCH v8 06/12] drm/i915: Add i915_gem_fini_hw to i915_reset

By calling in i915_reset only i915_gem_init_hw without previous i915_gem_fini_hw we introduced asymmetry. Let's fix that. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --

[Intel-gfx] [PATCH v8 07/12] drm/i915/guc: Restore symmetric doorbell cleanup

up, as GuC should be still active by now. Suggested-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Winiarski <michal.winiar...@intel.com> Cc: Chris Wilson &

[Intel-gfx] [PATCH v8 08/12] drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw

As we always call intel_uc_sanitize after every call to intel_uc_fini_hw we may drop redundant call and sanitize uC from the fini_hw function. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chr

[Intel-gfx] [PATCH v8 03/12] drm/i915: Move i915_gem_fini to i915_gem.c

We should keep i915_gem_init/fini functions together for easier tracking of their symmetry. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i9

[Intel-gfx] [PATCH v8 04/12] drm/i915: Introduce i915_gem_fini_hw for symmetry with i915_gem_init_hw

We have i915_gem_init_hw function that on failure requires some cleanup in uC and then in other places we were trying to do such cleanup directly. Let's fix that by adding i915_gem_fini_hw for nice symmetry with init_hw and call it on cleanup paths. Signed-off-by: Michal Wajdeczko <michal.waj

[Intel-gfx] [PATCH v8 09/12] drm/i915/uc: Use correct error code for GuC initialization failure

v3: update comments (Sagar) use sanitize functions on failure in init_hw (Michal) and also sanitize guc/huc fw in fini_hw (Michal) v4: rebase v5: rebase Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Winia

[Intel-gfx] [PATCH v8 02/12] drm/i915: Correctly handle error path in i915_gem_init_hw

In function gem_init_hw() we are calling uc_init_hw() but in case of error later in function, we missed to call matching uc_fini_hw() Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.

[Intel-gfx] [PATCH v8 01/12] drm/i915: Park before resetting the submission backend

trying to modify the engine vfuncs pointer on a live system after reset (not just wedging). We will just have to hope that the system is balanced. v3: Rebase onto __i915_gem_park and improve grammar. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajd

Re: [Intel-gfx] [PATCH] drm/i915: Park before resetting the submission backend

he system is balanced. > v3: Rebase onto __i915_gem_park and improve grammar. > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Michal Wajdeczko <michal.wajdec...@intel.com> > Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> > Cc: Tvrtko Urs

Re: [Intel-gfx] [PATCH v3] drm/i915: Split out parking from the idle worker for reuse

g them as being notify_cb. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Mika Kuoppala <mika.kuopp...@linux.inte

Re: [Intel-gfx] [PATCH] drm/i915: Split out parking from the idle worker for reuse

makes it more forgiving to use by future callers. Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com> Cc: Mika Kuoppala

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Park before resetting the submission backend

tch backends (reset_default_submission on wedge > recovery, or on enabling the guc) while parked. > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Michal Wajdeczko <michal.wajdec...@intel.com> > Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> > Cc: Tvrtko Ursuli

[Intel-gfx] [PATCH v6 04/12] drm/i915: Add i915_gem_fini_hw to i915_gem_suspend

By calling i915_gem_init_hw in i915_gem_resume and not calling i915_gem_fini_hw in i915_gem_suspend we introduced asymmetry in init_hw/fini_hw calls. Let's fix that. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chri

[Intel-gfx] [PATCH v6 11/12] drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c

Some functions already use i915 name instead of dev_priv. Let's rename this param in all remaining functions, except those that still use legacy macros. v2: don't forget about function descriptions (Sagar) v3: rebased Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Re

[Intel-gfx] [PATCH v6 06/12] drm/i915/guc: Ignore dev_priv->gt.awake while disabling submission

In next patch we will also try to disable GuC submission during reset path, where where we don't wait for idle_work to complete. Remove GEM_BUG_ON to allow new scenario. While here fix order to match symmetry with enable function. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com&

[Intel-gfx] [PATCH v6 09/12] drm/i915/uc: Use correct error code for GuC initialization failure

v3: update comments (Sagar) use sanitize functions on failure in init_hw (Michal) and also sanitize guc/huc fw in fini_hw (Michal) v4: rebase v5: rebase Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Winia

[Intel-gfx] [PATCH v6 08/12] drm/i915/uc: Fully sanitize uC within intel_uc_fini_hw

As we always call intel_uc_sanitize after every call to intel_uc_fini_hw we may drop redundant call and sanitize uC from the fini_hw function. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chr

[Intel-gfx] [PATCH v6 07/12] drm/i915/guc: Restore symmetric doorbell cleanup

up, as GuC should be still active by now. Suggested-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Winiarski <michal.winiar...@intel.com> Cc: Chris Wilson &

[Intel-gfx] [PATCH v6 12/12] HAX: Enable GuC for CI

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index c963603..53037b5 100644 --- a/drivers/gpu/dr

[Intel-gfx] [PATCH v6 01/12] drm/i915: Correctly handle error path in i915_gem_init_hw

In function gem_init_hw() we are calling uc_init_hw() but in case of error later in function, we missed to call matching uc_fini_hw() Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.

[Intel-gfx] [PATCH v6 03/12] drm/i915: Introduce i915_gem_fini_hw for symmetry with i915_gem_init_hw

We have i915_gem_init_hw function that on failure requires some cleanup in uC and then in other places we were trying to do such cleanup directly. Let's fix that by adding i915_gem_fini_hw for nice symmetry with init_hw and call it on cleanup paths. Signed-off-by: Michal Wajdeczko <michal.waj

[Intel-gfx] [PATCH v6 10/12] drm/i915/uc: Use helper functions to detect fw load status

We don't have to check load status values. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/

[Intel-gfx] [PATCH v6 02/12] drm/i915: Move i915_gem_fini to i915_gem.c

We should keep i915_gem_init/fini functions together for easier tracking of their symmetry. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i9

[Intel-gfx] [PATCH v6 05/12] drm/i915: Add i915_gem_fini_hw to i915_reset

By calling in i915_reset only i915_gem_init_hw without previous i915_gem_fini_hw we introduced asymmetry. Let's fix that. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --

Re: [Intel-gfx] [PATCH v12 05/17] drm/i915/guc/slpc: Add SLPC communication interfaces

.@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sujaritha Sundaresan <sujaritha.sundare...@in

Re: [Intel-gfx] [PATCH v12 01/17] drm/i915/guc/slpc: Add SLPC control to enable_guc modparam

t; Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenb...@intel.com> Cc: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sujaritha Sundaresan <sujaritha.sundare...@intel.com> Cc: Jeff McGee <jeff.mc...@intel.com> --- d

[Intel-gfx] [PATCH v7 10/12] drm/i915/guc: Handle default action received over CT

: filter disabled messages (Daniele) Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Michel Thierry <michel.thie...@intel.com> #1 Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> --- drivers/

Re: [Intel-gfx] [PATCH v5 10/12] drm/i915/guc: Handle default action received over CT

On Tue, 27 Mar 2018 22:03:23 +0200, Michel Thierry <michel.thie...@intel.com> wrote: On 3/27/2018 11:25 AM, Daniele Ceraolo Spurio wrote: On 26/03/18 12:48, Michal Wajdeczko wrote: When running on platform with CTB based GuC communication enabled, GuC to Host event data will be del

[Intel-gfx] [PATCH v5 4/8] drm/i915/uc: Fully sanitize uC in uc_fini_hw

Today uc_fini_hw is subset of uc_sanitize, but remaining code in sanitize function is also desired for uc_fini_hw. Instead of duplicating the code, just call uc_sanitize, but leave as separate function to maintain symmetry with uc_init_hw. Signed-off-by: Michal Wajdeczko <michal.waj

[Intel-gfx] [PATCH v5 5/8] drm/i915/uc: Use correct error code for GuC initialization failure

v3: update comments (Sagar) use sanitize functions on failure in init_hw (Michal) and also sanitize guc/huc fw in fini_hw (Michal) v4: rebase Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Winiarski <mich

[Intel-gfx] [PATCH v5 3/8] drm/i915/guc: Restore symmetric doorbell cleanup

up, as GuC should be still active by now. Suggested-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Michal Winiarski <michal.winiar...@intel.com> Cc: Chri

[Intel-gfx] [PATCH v5 6/8] drm/i915/uc: Use helper functions to detect fw load status

We don't have to check load status values. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/

[Intel-gfx] [PATCH v5 7/8] drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c

Some functions already use i915 name instead of dev_priv. Let's rename this param in all remaining functions, except those that still use legacy macros. v2: don't forget about function descriptions (Sagar) v3: rebased Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Re

[Intel-gfx] [PATCH v5 8/8] HAX: Enable GuC for CI

v2: except running with HYPERVISOR Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> --- drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_uc.c| 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/d

[Intel-gfx] [PATCH v5 1/8] drm/i915: Correctly handle error path in i915_gem_init_hw

In function gem_init_hw() we are calling uc_init_hw() but in case of error later in function, we missed to call matching uc_fini_hw() Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.

[Intel-gfx] [PATCH v5 2/8] drm/i915/uc: Disable GuC submission during sanitize

We should not leave GuC submission enabled after sanitize, as we are going to reset all GuC/HuC hardware. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/d

Re: [Intel-gfx] [PATCH v4 3/7] drm/i915/uc: Fully sanitize uC in uc_fini_hw

On Mon, 26 Mar 2018 13:23:21 +0200, Sagar Arun Kamble <sagar.a.kam...@intel.com> wrote: On 3/23/2018 8:44 PM, Michal Wajdeczko wrote: Today uc_fini_hw is subset of uc_sanitize, but remaining code in sanitize function is also desired for uc_fini_hw. Instead of duplicating the code

Re: [Intel-gfx] [PATCH v4 2/7] drm/i915/uc: Disable GuC submission during sanitize

On Mon, 26 Mar 2018 12:36:05 +0200, Sagar Arun Kamble <sagar.a.kam...@intel.com> wrote: On 3/23/2018 8:44 PM, Michal Wajdeczko wrote: We should not leave GuC submission enabled after sanitize, as we are going to reset all GuC/HuC hardware. Signed-off-by: Michal Wajdeczko <mich

[Intel-gfx] [PATCH v6 08/12] drm/i915/guc: Implement response handling in send_ct()

documentation (Michal) Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Reviewed-by: Michel Thierry <michel

Re: [Intel-gfx] [PATCH v5 01/12] drm/i915/guc: Add documentation for MMIO based communication

On Tue, 27 Mar 2018 12:05:21 +0200, Sagar Arun Kamble <sagar.a.kam...@intel.com> wrote: On 3/27/2018 1:18 AM, Michal Wajdeczko wrote: As we are going to extend our use of MMIO based communication, try to explain its mechanics and update corresponding definitions. v2: fix chec

[Intel-gfx] [PATCH v5 07/12] drm/i915/guc: Use better name for helper wait function

-by: Michal Wajdeczko <michal.wajdec...@intel.com> Reviewed-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/intel_guc_ct.c | 25 + 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/

[Intel-gfx] [PATCH v5 11/12] drm/i915/guc: Trace messages from CT while in debug

During debug we may want to investigate all communication from the Guc. Add proper tracing macros in debug config. v2: convert remaining DRM_DEBUG into new CT_DEBUG (Michal) v3: use dedicated Kconfig (Daniele) v4: checkpatch Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com&

[Intel-gfx] [PATCH v5 09/12] drm/i915/guc: Prepare to process incoming requests from CT

) and fix checkpatch add some documentation (Michal) Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> -

[Intel-gfx] [PATCH v5 06/12] drm/i915/guc: Prepare to handle messages from CT RECV buffer

: misc improvements (Michal) v3: change response detection (Michal) invalid status is protocol error (Michal) v4: rebase v5: fix checkpatch (Michel) don't use fields before check (Jani) add some documentation (Michal) Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc:

[Intel-gfx] [PATCH v5 03/12] drm/i915/guc: Prepare send() function to accept bigger response

This is a preparation step for the upcoming patches. We already can return some small data decoded from the command status, but we will need more in the future. v2: add explicit response buf size v3: squash with helper patch Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc:

[Intel-gfx] [PATCH v5 04/12] drm/i915/guc: Implement response handling in send_mmio()

We're using data encoded in the status MMIO as return value from send function, but GuC may also write more data in remaining MMIO regs. Let's copy content of these registers to the buffer provided by caller. v2: new line (Michel) v3: updated commit message Signed-off-by: Michal Wajdeczko

[Intel-gfx] [PATCH v5 12/12] HAX: Enable GuC for CI

Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index c963603..53037b5 100644 --- a/drivers/gpu/dr

[Intel-gfx] [PATCH v5 10/12] drm/i915/guc: Handle default action received over CT

. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Reviewed-by: Michel Thierry <michel.thie...@intel.com> --- drivers/gpu/drm/i915/intel_guc.c| 5 + drivers/gpu/drm/i915/intel_guc.h| 1 + drivers/gpu/drm/i915/intel_guc_ct.

[Intel-gfx] [PATCH v5 08/12] drm/i915/guc: Implement response handling in send_ct()

-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Reviewed-by: Michel Thierry <michel.thie...@intel.com> #2.5 Cc: M

[Intel-gfx] [PATCH v5 05/12] drm/i915/guc: Make event handler a virtual function

On platforms with CTB based GuC communications, we will handle GuC events in a different way. Let's make event handler a virtual function to allow easy switch between those variants. Credits-to: Oscar Mateo <oscar.ma...@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdec...@inte

[Intel-gfx] [PATCH v5 00/12] drm/i915/guc: Support for Guc responses and requests

With this series we will be able to receive more data from the Guc. New Guc firmwares will be required to actually use that feature. v4: respin series after 1/2 year break v5: updated after review comments Michal Wajdeczko (12): drm/i915/guc: Add documentation for MMIO based communication

[Intel-gfx] [PATCH v5 01/12] drm/i915/guc: Add documentation for MMIO based communication

As we are going to extend our use of MMIO based communication, try to explain its mechanics and update corresponding definitions. v2: fix checkpatch MACRO_ARG_REUSE Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com&g

[Intel-gfx] [PATCH v5 02/12] drm/i915/guc: Add support for data reporting in GuC responses

message (Daniele) v3: rebase Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> Cc: Michel Thierry <michel.thie...@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> Reviewed-by: Michel Thierry <michel.thie

Re: [Intel-gfx] [PATCH v4 08/13] drm/i915/guc: Implement response handling in send_ct()

On Mon, 26 Mar 2018 17:35:00 +0200, Jani Nikula <jani.nik...@linux.intel.com> wrote: On Mon, 26 Mar 2018, Michał Winiarski <michal.winiar...@intel.com> wrote: On Fri, Mar 23, 2018 at 02:47:23PM +0000, Michal Wajdeczko wrote: Instead of returning small data in response status dw

Re: [Intel-gfx] [PATCH v4 08/13] drm/i915/guc: Implement response handling in send_ct()

On Mon, 26 Mar 2018 17:29:32 +0200, Michał Winiarski <michal.winiar...@intel.com> wrote: On Fri, Mar 23, 2018 at 02:47:23PM +, Michal Wajdeczko wrote: Instead of returning small data in response status dword, GuC may append longer data as response message payload. If caller pr

Re: [Intel-gfx] [PATCH v4 05/13] drm/i915/guc: Make event handler a virtual function

On Fri, 23 Mar 2018 23:25:58 +0100, Michel Thierry <michel.thie...@intel.com> wrote: On 3/23/2018 7:47 AM, Michal Wajdeczko wrote: On platforms with CTB based GuC communications, we will handle GuC events in a different way. Let's make event handler a virtual function to allow easy

Re: [Intel-gfx] [PATCH v4 04/13] drm/i915/guc: Implement response handling in send_mmio()

On Fri, 23 Mar 2018 22:55:09 +0100, Michel Thierry <michel.thie...@intel.com> wrote: On 3/23/2018 7:47 AM, Michal Wajdeczko wrote: We're using data encoded in the status MMIO as return value from send function, but GuC may also write more data in remaining MMIO regs. Let's copy c

Re: [Intel-gfx] [PATCH v4 01/13] drm/i915/guc: Add documentation for MMIO based communication

On Fri, 23 Mar 2018 22:29:21 +0100, Michel Thierry <michel.thie...@intel.com> wrote: On 3/23/2018 7:47 AM, Michal Wajdeczko wrote: As we are going to extend our use of MMIO based communication, try to explain its mechanics and update corresponding definitions. Signed-off-by:

Re: [Intel-gfx] [CI 1/2] drm/i915/guc: Fix null pointer dereference when GuC FW is not available

On Fri, 23 Mar 2018 19:40:10 +0100, Yaodong Li <yaodong...@intel.com> wrote: On 03/23/2018 11:26 AM, Michal Wajdeczko wrote: On Fri, 23 Mar 2018 19:03:47 +0100, Yaodong Li <yaodong...@intel.com> wrote: On 03/23/2018 05:27 AM, Michal Wajdeczko wrote: On Fri, 23 Mar 2018 13

Re: [Intel-gfx] [CI 1/2] drm/i915/guc: Fix null pointer dereference when GuC FW is not available

On Fri, 23 Mar 2018 19:03:47 +0100, Yaodong Li <yaodong...@intel.com> wrote: On 03/23/2018 05:27 AM, Michal Wajdeczko wrote: On Fri, 23 Mar 2018 13:07:15 +0100, Sagar Arun Kamble <sagar.a.kam...@intel.com> wrote: On 3/23/2018 4:53 PM, Piotr Piórkowski wrote: If

[Intel-gfx] [PATCH v4 3/7] drm/i915/uc: Fully sanitize uC in uc_fini_hw

Today uc_fini_hw is subset of uc_sanitize, but remaining code in sanitize function is also desired for uc_fini_hw. Instead of duplicating the code, just call uc_sanitize, but leave as separate function to maintain symmetry with uc_init_hw. Signed-off-by: Michal Wajdeczko <michal.waj

[Intel-gfx] [PATCH v4 5/7] drm/i915/uc: Use helper functions to detect fw load status

We don't have to check load status values. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Reviewed-by: Sagar Arun Kamble <sagar.a.kam...@intel.com> --- drivers/gpu/

[Intel-gfx] [PATCH v4 6/7] drm/i915/uc: Trivial s/dev_priv/i915 in intel_uc.c

Some functions already use i915 name instead of dev_priv. Let's rename this param in all remaining functions, except those that still use legacy macros. v2: don't forget about function descriptions (Sagar) v3: rebased Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Re

[Intel-gfx] [PATCH v4 2/7] drm/i915/uc: Disable GuC submission during sanitize

We should not leave GuC submission enabled after sanitize, as we are going to reset all GuC/HuC hardware. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/d

[Intel-gfx] [PATCH v4 1/7] drm/i915: Correctly handle error path in i915_gem_init_hw

In function gem_init_hw() we are calling uc_init_hw() but in case of error later in function, we missed to call matching uc_fini_hw() Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Sagar Arun Kamble <sagar.a.kam...@intel.com> Cc: Chris Wilson <ch...@chr

[Intel-gfx] [PATCH v4 7/7] HAX: Enable GuC for CI

v2: except running with HYPERVISOR Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> --- drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_uc.c| 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/d

[Intel-gfx] [PATCH v4 4/7] drm/i915/uc: Use correct error code for GuC initialization failure

v3: update comments (Sagar) use sanitize functions on failure in init_hw (Michal) and also sanitize guc/huc fw in fini_hw (Michal) v4: rebase Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Chris Wilson <ch...@chris-wilson.co.uk> Cc: Michal Winiarski <mich

[Intel-gfx] [PATCH v4 11/13] drm/i915/guc: Handle default action received over CT

. Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Oscar Mateo <oscar.ma...@intel.com> --- drivers/gpu/drm/i915/intel_guc.c| 5 + drivers/gpu/drm/i915/intel_guc.h| 1 + drivers/gpu/drm/i915/intel_guc_ct.c | 9 + 3 files changed, 15 insertions(+) diff --g

[Intel-gfx] [PATCH v4 04/13] drm/i915/guc: Implement response handling in send_mmio()

We're using data encoded in the status MMIO as return value from send function, but GuC may also write more data in remaining MMIO regs. Let's copy content of these registers to the buffer provided by caller. v2: new line (Michel) v3: updated commit message Signed-off-by: Michal Wajdeczko

[Intel-gfx] [PATCH v4 05/13] drm/i915/guc: Make event handler a virtual function

On platforms with CTB based GuC communications, we will handle GuC events in a different way. Let's make event handler a virtual function to allow easy switch between those variants. Credits-to: Oscar Mateo <oscar.ma...@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdec...@inte

[Intel-gfx] [PATCH v4 12/13] drm/i915/guc: Trace messages from CT while in debug

During debug we may want to investigate all communication from the Guc. Add proper tracing macros in debug config. v2: convert remaining DRM_DEBUG into new CT_DEBUG (Michal) v3: use dedicated Kconfig (Daniele) Signed-off-by: Michal Wajdeczko <michal.wajdec...@intel.com> Cc: Daniele C

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